VHDL constant range declaration

Question

I have a bunch of network packets and I am trying to specify fields in them, something like

constant UPPER_BOUND : natural := 15;
constant LOWER_BOUND : natural := 7;

I know that this syntax is CORRECT

The range does not change throughout the application and I was thinking if it is possible in the VHDL syntax to declare a constant range if you will. Something to the effect of:

constant FIELD_RANG : natural range := (15 downto 7);

I know that this syntax is WRONG

But, I was trying to understand, if specifying a generic range is possible ? Is the 1st mentioned syntax the only way to do this ?

Answer 1

I think the second line should be

constant LOWER_BOUND : natural := 7;

above. (OK, it is now! :-) But anyway... welcome to a language with a proper type system! Learn to use it, and you will love it. Or learn to fight it, and you will hate it. Your choice...

What you are looking for is either

type Field_Range is new Natural range UPPER_BOUND downto LOWER_BOUND;

or

subtype Field_Range is Natural range UPPER_BOUND downto LOWER_BOUND;

according to whether you want type safety, or easy mixing of Field_Range with other integer quantities.

Either way you can say

Field : Array(Field_Range) of Something;

for i in Field_Range loop
   ...
end loop

and (almost!) never worry about bounds errors again.

What is the difference between Type and Subtype? That'll take a little learning, but here's a start:

if you have the following,

constant N : Natural := 7;
constant F : Field_Range := N;

the subtype will allow it, the new type will not, you would need to convert:

constant F : Field_Range := Field_Range(N);