What is better: No solder mask at all under the fine pitch component with thermal pad or shrink the thermal pad to leave room for a solder mask ridge around the thermal pad?
I am making the layout for a surface mount DFN 12+1 pin package (Dual Flat No-lead 3x3mm) from Linear Technology (similar to QFN). The recommended pad layout leaves a clearance of 0.225 mm (8.9mill) between the thermal pad and the periphery pads. With a solder mask expansion of 0.1mm (3.9mill) this leaves a ridge of solder mask (solder mask sliver) of only 0.225mm-2*0.1mm = 0.025mm (1 mill) - clearly not a size which can be produced. In fact the PCB fab house has 0.1mm (3.9 mill) as minimum ridge width. I see two options: 1: Keep the solder mask by: Shrinking the thermal pad's copper land pattern in order to increase the solder mask ridge to >0.1mm (3.9mill). 2: Remove the solder mask entirely (ridge width=0). This is already the case between the periphery pads them selves (pitch 0.5mm (20mill))
I am in doubt as to what is the best option. With option one I have a solder pad which is smaller than the components pad. With option two there is effectively no solder mask at all under the 12+1 pad's of the component and I would fear short circuits.
Any advice would be appreciated.