Kind of late to the discussion, but for anyone reading it after a search....
One thing I did not see mentioned, which is absolutely critical when programming SPI Flash chips is control of the Chip Select (CS_) pin. The Chip Select pin is used to punctuate commands to the SPI Flash. In particular, a transition from CS_ high to CS_ low must immediately precede the issuance of any Write operation op code (WREN, BE, SE, PP). If there is activity between the CS_ transition (i.e. after CS_ has gone low) and before the write op code is transmitted, the write op code will usually be ignored.
Also, what's not commonly explained in SPI Flash datasheets, because it's an inherent part of the SPI protocol, which is also critical, is that for every byte one transmits on the SPI bus, one receives a byte in return. Also, one cannot receive any bytes, unless one transmits a byte.
Typically, the SPI Master that the user is commanding, has a Transmit Buffer, which sends bytes out on the MOSI line of the SPI bus and a Receive Buffer, which receives bytes in from the MISO line of the SPI bus.
In order for any data to appear in the Receive buffer, some data must have been sent out the Transmit Buffer. Similarly, any time one sends data out of the Transmit buffer, data will appear in the Receive Buffer.
If one is not careful about balancing Transmit writes and Receive reads, one will not know what to expect in the Receive buffer. If the Receive buffer overflow, data is usually just spilled and lost.
So, when one sends a read command, which is a one byte op code and three address bytes, one will first receive four bytes of "garbage" in the SPI Master Receive buffer. These four bytes of garbage correspond to the op code and three address bytes. While those are being transmitted, the Flash does not yet know what to Read, so it just returns four words of garbage.
After those four words of garbage are returned, in order to get anything else in the Receive Buffer, you must Transmit an amount of data equal to the amount that you want to Read. After the op code and address, it doesn't matter what you transmit, it's just filler to push the Read DAta from the SPI Flash to the Receive Buffer.
If you didn't keep careful track of those first four returned garbage words, you might think that one or more of them is part of your returned Read Data.
So, in order to know what you are actually getting from the receive buffer, it's important to know the size of your buffer, know how to tell whether it's empty or full (there's usually register status bit to report this) and keep track of how much stuff you've transmitted and how much you've received.
Before starting any SPI Flash operation, it's a good idea to "drain" the Receive FIFO. This means check the status of the receive buffer and empty it (usually done by performing a 'read' of the Receive Buffer) if it is not already empty. Usually, emptying (reading) an already empty Receive Buffer does no harm.
The following information is available from the timing diagrams in datasheets of SPI Flashes, but sometimes folks overlook bits. All commands and data are issued to the SPI flash using the SPI bus. The sequence to read a SPI Flash is:
1) Start with CS_ high.
2) Bring CS_ low.
3) Issue "Read" op code to SPI Flash.
4) Issue three address bytes to SPI Flash.
5) "Receive" four garbage words in Receive Buffer.
6) Transmit as many arbitrary bytes (don't cares) as you wish to receive.
Number of transmitted bytes after address equals size of desired read.
7) Receive read data in the Receive Buffer.
8) When you've read the desired amount of data, set CS_ high to end the Read command.
If you skip this step, any additional transmissions will be interpreted as
request for more data from (a continuation of) this Read.
Note that steps 6 and 7 must be interleaved and repeated depending on the size of the read and the size of your Receive and Transmit Buffers. If you Transmit a larger number of words at one go, than your Receive Buffer can hold, you'll spill some data.
In order to preform a Page Program or Write command perform these steps. Page Size (typically 256 bytes) and Sector Size (typically 64K) and associated boundaries are properties of the SPI Flash you are using. This information should be in the datasheet for the Flash. I will omit the details of balancing the Transmit and Receive buffers.
1) Start with CS_ high.
2) Change CS_ to low.
3) Transmit the Write Enable (WREN) op code.
4) Switch CS_ to high for at least one SPI Bus clock cycle. This may be tens or
hundreds of host clock cycles. All write operations do not start until CS_ goes high.
The preceding two notes apply to all the following 'CS_ to high' steps.
5) Switch CS_ to low.
6) Gadfly loop: Transmit the 'Read from Status Register' (RDSR) op code and
one more byte. Receive two bytes. First byte is garbage. Second byte is status.
Check status byte. If 'Write in Progress' (WIP) bit is set, repeat loop.
(NOTE: May also check 'Write Enable Latch' bit is set (WEL) after WIP is clear.)
7) Switch CS_ to high.
8) Switch CS_ to low.
9) Transmit Sector Erase (SE) or Bulk Erase (BE) op code. If sending SE, then follow
it with three byte address.
10) Switch CS_ to high.
11) Switch CS_ to low.
12) Gadfly loop: Spin on WIP in Status Register as above in step 6. WEL will
be unset at end.
13) Switch CS_ to high.
14) Switch CS_ to low.
15) Transmit Write Enable op code (again).
16) Switch CS_ to high.
17) Switch CS_ to low.
18) Gadfly loop: Wait on WIP bit in Status Register to clear. (WEL will be set.)
19) Transmit Page Program (PP = Write) op code followed by three address bytes.
20) Transmit up to Page Size (typically 256 bytes) of data to write. (You may allow
Receive data to simply spill over during this operation, unless your host hardware
has a problem with that.)
21) Switch CS_ to high.
22) SWitch CS_ to low.
23) Gadfly loop: Spin on WIP in the Status Register.
24) Drain Receive FIFO so that it's ready for the next user.
25) Optional: Repeat steps 13 to 24 as needed to write additional pages or
Finally, if your write address is not on a page boundary (typically a multiple of 256 bytes) and you write enough data to cross the following page boundary, the data that should cross the boundary will be written to the beginning of the page in which your program address falls. So, if you attempt to write three bytes to address 0x0FE. The first two bytes will be written to 0x0fe and 0x0ff. The third byte will be written to address 0x000.
If you transmit a number of data bytes larger than a page size, the earlies bytes will be discarded and only the final 256 (or page size) bytes will be used to program the page.
As always, not responsible for consequences of any errors, typos, oversights, or derangement in the above, nor in how you put it to use.