Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free.

Sign up
Here's how it works:
  1. Anybody can ask a question
  2. Anybody can answer
  3. The best answers are voted up and rise to the top

Groundhog is a open source SATA host bus adapter core written in Verilog. I was wondering if anyone had tips on how to begin to understand how it operates? Is it to go from the high-level to low-level? or vice versa? Do I draw FSM diagrams for everything I see? What are some of the handy tips and tricks?

Note: This question is in the context of an individual who understands Verilog or VHDL already, but just has trouble getting his or her head around largish HDL designs.

share|improve this question
Do you have documentation? Test benches? – Brian Carlton Dec 14 '12 at 22:39

This is a very open-ended question, and will be difficult to answer properly in the SE format. However, I just went through an exercise like this myself recently, so I'll throw out a few thoughts.

Definitely take a top-down, outside-in approach. Make sure you know what the core is supposed to do and how the external interfaces are supposed to behave in a fair amount of detail. Think a bit about how you'd approach implementing it. Then, look at the implementation of the top-level module and see how it's broken up (hopefully :-) into functional sub-modules that make sense.

Keep going, making notes, drawing block diagrams — and yes, state diagrams where applicable — as you go. When looking at the interfaces among sub-modules, there will likely be little documentation, so you're going to have to reverse-engineer many of the details from the implementations inside the submodules. Hopefully, there will be consistent patterns that get used in multiple places.

A simulator can be invaluable for picking apart details, which is another reason you should have a good handle on the external interfaces. This allows you to write a meaningful testbench to exercise the module (assuming one doesn't already exist).

share|improve this answer

Your Answer


By posting your answer, you agree to the privacy policy and terms of service.

Not the answer you're looking for? Browse other questions tagged or ask your own question.