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There are packages as thin as 0.3 mm (maybe even less), so I was wondering how thin the actual die/wafer inside them are. I guess the package top and bottom will also need a certain thickness to be useful, so how much is left for the die?

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Downvoter, can you tell why? –  Federico Russo Dec 16 '12 at 13:02
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I guess it was down voted because it was a bit vague, but who knows, I knocked it up for you. I also suggested an edit to make it a bit more readable. –  Garrett Fogerlie Dec 16 '12 at 17:01
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2 Answers

up vote 11 down vote accepted

Very thin, ~700µm (0.7mm) is close to the upper limit. Around 100µm (0.1mm) is about as thin as they get. However the size varies a lot, depending on multiple things, like the package it's made for, quality, price, and the overall size of the wafer.

Update After further research, I found that for certain applications, the wafer may be as thin as 50µm.

guess the package top and bottom will also need a certain thickness to be useful, so how much is left for the die?

An incredibly small amount, take a look at this picture and the others at the bottom.

Yamaha YMF262 audio IC decapsulated High quality decapsulated surface mount Yamaha YMF262 audio IC photo

It varies with the size of the wafer, according to wiki,

  • 2-inch (51 mm). Thickness 275 µm.
  • 3-inch (76 mm). Thickness 375 µm.
  • 4-inch (100 mm). Thickness 525 µm.
  • 5-inch (130 mm) or 125 mm (4.9 inch). Thickness 625 µm.
  • 150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.
  • 200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.
  • 300 mm (11.8 inch, usually referred to as "12 inch"). Thickness 775 µm.
  • 450 mm (17.7 inch, usually referred to as "18 inch"). Thickness 925 µm.

Basically they take a slice of silicon that's about .6mm thick (on average,) grind it, smooth it, etch it, then grind the back side.

Here's a good video to watch, How Silicon Wafers are Made. And to see how a chip is decapsulated, watch Chris Tarnovsky's video How to Reverse-Engineer a Satellite TV Smart Card.

If your interested in decapsulating chips, and close up images and probing of the die, FlyLogic's blog has some awesome posts, and great pictures!

And a few pictures of decapsulated chips,

Machine Decapsulated ST Microchip Fly Logic decapsulated surface mount IC photo CGI internal ball gate array IC Several decapsulated large processors IC Diagram

The following 2 images are of a ADXL345 3mm × 5mm × 1mm LGA package. The first is a side X-ray. The X-ray clearly shows the presence of a separate ASIC die and MEMS die, with a hermetic cap. The internal structure of the device is more clearly seen in the SEM micrograph of the decapsulated device, in the second image. ADXL345 Package X-Ray ADXL345 Package SEM micrograph

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Prime wafers (which is a specification) nominally 720μ, additional processing for metal layers may add as much as 7μ. There is some variation in thickness. Some devices are thinned through a process known as back-grinding but that thickness is usually only taken to 300μ total thickness. This is used in cases where thickness matters, like in image sensor modules (which only use the die - the die are not packaged) or in the case of stacked die where one die is placed on top of another, like the combination of Flash memory and DRAM, used in mobile handsets.

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