I am designing a system where a DSP (like the TMS320VC5501) processes some video data and outputs it to a PSP screen (the ones sold on sparkfun). The issue I'm having here is designing the video output interface. I'm thinking that I should have a video buffer and maybe a CPLD to read data and spit it out to the PSP screen, but the exact details haven't been completely worked out.
My main concern is timing. The DSP will be writing image data to the video buffer as fast as possible which might not leave enough room for data reads on the output side. I've looked around and it seems like GPUs these days use fast SDRAM which suggests that I should use it (since it's obviously working for them), but if I do then I'm blanking on how to read from it to output to the display. (The DSP has an SDRAM controller, but I don't want to load it with constant display requests. I want to use it's processing power for actual processing as opposed to memory games) Another alternative is VRAM, but this is a really old method and seems to be going out of style. Might be my best option though...
As another thought, I can use DMA to burst-write 11520 bits (480pix x 8bits x 3colors) to a shift register during hsync via an interrupt (hsync/vsync will be PLD controlled). From there, the PLD will control that shift register to output the data using the correct timing. I have to double check the numbers, but this seems like a plausible solution.
Anybody have any insight on this?