# PN512 not starting?

I got a PN512 IC (NFC controller from NXP) interfacing with a MCU over SPI and ChibiOS. Everything seems to be working fine, i can read the registers and they returned value matches with the reset value specified on the datasheet. This means that there is no problem on the SPI (As the IC is answering my commands sucessfully). The problem arises when i try to read the CommandReg register (at address 01h), the reset value must be 20h (or 00100000b) but it returns me 3Fh (or 00111111b) meaning that it has the PowerDown and SoftReset enabled at the same time and the datasheet says that this is not possible ("The bit Power Down cannot be set, when the command SoftReset has been activated"). At this point i'm stuck as the PowerDown bit must be set to 0 (by the IC itself) to do any other operation on it.

Anyone have a clue or hint on what may be happening here? I checked every VDD pin and all of them gets feed by a nice filtered 3.3v, the AVDD pin is connected with a inductance in series with the VDD line plus a smoothing cap.

Any help will be highly appreciated!

-
The values you mention suggest that the first 1 that is read somehow dominates the subsequent bits (SPI transfers are MSB-first). Maybe this gives you a clue. –  Wouter van Ooijen Dec 30 '12 at 20:13
Do you have a logic analyzer/oscilloscope handy? These can be life savers. The communication might work, but marginally and so when it comes time to have it run on other things, it fails. If you can, run a statistical communication test by reading all registers thousands of times and checking that the results stay the same and that they're correct. If they're changing and shouldn't, communications aren't reliable for some reason. –  Gustavo Litovsky Dec 30 '12 at 20:15
@WoutervanOoijen Even if the received value doesn't match with only one register? Everything else is read fine. @GustavoLitovsky Thanks, i tested it on a for of 10k of loops and 100% of the values were read equally. I tested with my scope and the clock line and MOSI/MISO seems good. What bugs me is that only THAT is not read fine, maybe the chip itself is damaged? –  kR105 Dec 31 '12 at 1:38