Take the 2-minute tour ×
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It's 100% free, no registration required.

I am attempting to build a ringer interface circuit, and I’m running into problems that are over my head. The purpose of the circuit is to buffer the output of a central telephone system that goes to several ringers spaced throughout the building. The reason for the circuit is that whenever the line rings, it overloads and needs to be reset, thus this circuit will buffer the line and offer a lot more output capability.

The schematic is below:

link to better picture


EDIT: R7 goes to +24V, not +12V

Now, my problem is this: when everything is on, and the line is ringing (4N27 triggered), I only get 12V out , instead of 24. I went through and checked voltages, and it seems like none of the transistors are turning on (or off as the case may be) completely. When I tie the base resistor of the first (closest to the 4N27) signal transistor to ground (turning it 100% off), I then get the correct 24V out.

Also, it exhibits the same problem with a 5V supply, so I don’t think that’s it.

Anyone have any ideas as to what may be causing this? I’m a bit of a novice at circuit design, so any and all help is much appreciated.

share|improve this question
The text on your schematic is so small it's hard to read, but it looks like the output of the opto is being pulled up to 12V. Why do you expect 24V there? Actually it should be considerably less due to that node being loaded thru R3 and the B-E junction of left transistor (Q1? it's hard to read). –  Olin Lathrop Jan 10 '13 at 19:01
I meant the output from the TIP32 power transistor at the end, sorry for the confusion. Also, I will try and upload a better picture. thanks! –  Scott Jan 10 '13 at 19:08
It would really make a whole lot more sense if you were to use a PNP at Q1 instead of an NPN. Take advantage of the gain of the transistor to reduce the current that the opto needs to sink. –  Dave Tweed Jan 10 '13 at 19:48
So, in that case, would that mean that since the power transistor is PNP, I could just hook that up instead of Q1, and do away with Q1 & Q2? thanks for the help! –  Scott Jan 10 '13 at 20:18
@OlinLathrop Right click -> view image to get the full size schematic with readable text. –  Phil Frost Jan 10 '13 at 21:46
show 4 more comments

Your Answer


By posting your answer, you agree to the privacy policy and terms of service.

Browse other questions tagged or ask your own question.