# How can one label a node with more than one name in SPICE/ LTspice

Update: node name "alias" (aka synonym) resolution seems to work fine in simple circuits... even though one of the two names "goes away" it's doing what I'd expect by namely referring everything to the correct single node. It's circuits involving subcircuits and models that aren't resolving synonyms as expected (particularly synonyms that appear within the library). At this point I'm trying to determine if it's a quirk of the libraries I'm using or if it's a limitation of SPICE when it comes to subcircuits and libraries.

I am working in LTspice though this question probably applies to SPICE as well. I have a small circuit I'm creating, however some components want VCC defined while others want VDD defined. In this case they are the same voltage (VCC=VDD=5V) from a single output power supply.

You cannot apply more than one label directly to a node. If you take a node, add a short trace and label one VCC and the other VDD, you of still end up with only one of those names actually getting defined in the netlist, since it's equivalent to one node and only one name is allowed per node.

There are hacky workarounds but I'd like to label my circuit correctly without any trickery (e.g., I could use an infinitesimally tiny resistance to create a second node to apply the "duplicate" label to).

Is there a mechanism in SPICE / LTspice for aliasing a node name to another name, such that the two may be used interchangeably?

Bonus: if not, why not? If SPICE can collapse a complex circuit into equivalent nodes (not exactly a trivial task) I'd think it could easily deal with simple name aliases...

Edit2: Perhaps a better bonus question would've been: why doesn't creating what appears to be an alias (either directly, by labeling the same node with two names, or indirectly by labeling each side of a jumper) throw an error in LTspice? For that matter, does it even throw an error in SPICE? (I suspect it does not given they are related at the core...) I came here because I spent a fair amount of time scratching my head wondering why one of the two names would get ignored as if it was never there... an error message from SPICE / LTspice would've helped immensely.)

Edit: The circuit is based on functional models of 7400- and 4000-series chips, not DIP models of them (thus there are no "pins" on the blocks for VCC / VDD (7400 uses VCC, 4000 uses VDD by convention)... you simply define them for the circuit as a whole and in this case I'm modeling the power supply as well). In short, drawing the power wires isn't an option anyway.

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Why not just simply route the wires? This seems like a lot of investigative work to simplify a schematic where the purpose is simply to simulate and not share with others. – Toby Lawrence Jan 14 '13 at 21:17
Do they need to be separate nets? Why are you choosing some nets to be called VCC and others to be VDD? – W5VO Jan 14 '13 at 21:29
Well, there's nothing to route the wires to... these are 4000- and 7400-series circuits that are functional blocks (e.g., they are not DIP models but block models and so power connections are done via the net list). And the 4000s use VDD while the 7400s use VCC. – MartyMacGyver Jan 14 '13 at 21:37
If you plan to use the same voltage supply for each logic block, then there is no point in having separate nets for "VCC" and "VDD" - they are synonymous. – W5VO Jan 14 '13 at 21:39
Read the updated description. Some elements require VDD to be defined and some require VCC to be defined. I'm sourcing from a power supply circuit and so I want to lay it out as such. Drawing wires (were it even possible in this case) doesn't answer the question of how to actually create an alias (this is a simple case but I can see aliases being useful in much larger circuits too). – MartyMacGyver Jan 14 '13 at 21:43

Easy solution: Just add a 0-V voltage source between VDD and VCC. It will not affect your simulation results at all.

But a better solution is to get better models. If you wanted to know how will a voltage difference in the supply between two gates affect the circuit, or the effect of inductance or resistance in the power supply lines, etc., you'll have problems doing it with these models. Get some models (or edit the models you have) to expose the power nets as pins on the model.

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Good point though tangential to the question - if you have any sources for better IC models please reply here. What I'm currently using is from the [tech.groups.yahoo.com/group/LTspice/](LTspice Yahoo! group). They do the job well but I definitely see your point about being able to model the individual IC power inputs. In THIS case I am more interested in modeling semi-ideal circuits as I do the logic work so what I have is working, except the alias thing (which apparently isn't do-able without adding extra components). – MartyMacGyver Jan 14 '13 at 22:00
Did you try the 0-V source? It should not collapse the nodes like it did with the jumper, because another reason to do this is to be able to measure the current through the source, which wouldn't work if the two nodes were combined. – The Photon Jan 14 '13 at 22:14
I'm waiting to see if aliases are at all possible. What are the possible side-effects? What if I'm modeling a noisy base power supply - will this extra source introduce anything usual? Adding a source seems like it'd be more complex than a trivially tiny resistor as I originally noted but perhaps not... – MartyMacGyver Jan 14 '13 at 22:18
Also, this works in a particular case (power supply aliases)... but what about general aliases? What if I'm using a logic output to feed CLKin and FOOin? (That's a contrived example but if a given model restricts my options with regard to node naming, would the 0V power source idea work better than a very tiny resistance - which is sightly more realistic anyway?) – MartyMacGyver Jan 14 '13 at 22:21
What do you mean by aliases. Two nodes that are absolutely always at the same potential are as good as aliases, aren't they? And it will work just as well for any kind of node --- the voltage source in SPICE is a totally ideal mathematical object that sets the potential difference between two nodes. – The Photon Jan 14 '13 at 22:50

There is a "jumper" component you add to a node (under the misc. folder). This lets you have multiple names for a net.

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While it seems to me that giving a node more than one name ought to be very trivial, I'm getting the impression SPICE is simply incapable of doing this. A jumper is about as simple as it gets if there's way to do actual aliases with no extra components... I'll give it a try! – MartyMacGyver Jan 14 '13 at 22:03
I tried it but evidently LTspice (or SPICE in general) is too clever and collapses jumpers as if they are just wires. Adding it as VDD made VCC disappear from the netlist, just as if it were the same node. – MartyMacGyver Jan 14 '13 at 22:10

Use subckt and abstract the internal model into a higher level module that then connects these pins up with a 1:1 mapping. At the very top level you can attach any node label to that voltage.

You then call the device using X and common voltage rail.

To answer the question: The answer is NO. The reason is that the each node in the circuit is a row/column in the circuit matrix that is used during computation.

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You answered my main question (evidently aliases are not possible) though I've yet to see an explanation of why SPICE doesn't flag this as some kind of error (instead of randomly suppressing the "aliases" one tried to create. As for subckt, I'll keep it in mind though it's not straightforward. – MartyMacGyver Jan 16 '13 at 7:29