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I am having issues with JTAG with my Cyclone IV, specifically the JTAG clock. I am trying to change the JTAG clock frequency somewhere, but can't find where this is done in Quartus II.

How can I change the JTAG frequency in Quartus II?

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Are you using Altera's Byte Blaster or your own? If so, which version of Altera? I don't have Quartus II in front of me to check where to change the speed, but I know that version B (and version A) of the altera byte blaster had signal integrity issues at high speeds. Rev C was created to resolve this and my understanding is that it did. –  Gustavo Litovsky Jan 16 '13 at 17:07
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I have the USB Blaster. I don't think it is the problem because I can program the CPLD fine with it, but not the FPGA. –  Randomblue Jan 16 '13 at 17:12
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What is the error that you're getting when you try and program the FPGA? –  Gustavo Litovsky Jan 16 '13 at 17:59

1 Answer 1

up vote 3 down vote accepted

According to this page, unfortunately the answer appears to be no:

Solution ID: rd11142008_293 Last Modified: Sep 11, 2012 Product Category: Devices Product Area: Download Cables/Hardware Product Sub-area: USB Blaster Device Family: MISC Title

Can I change the TCK frequency when using the USB-Blaster download cable? Description

No, the USB-Blaster™ download cable does not support the ability to change the TCK frequency.

Also here the same is mentioned.

Before you do any of the below, try to figure out what your dealing with here. Scope the signal (set to 10x with a tip ground clip - don't use the ground lead.

Quick thoughts on getting it to work (assuming you find some nasty ringing) - I'm guessing you can't shorten the distance of the signal route easily, so try a small capacitor (possibly with a series resistor) to ground on the line (I'd try at the receiving end) to attempt to terminate it roughly (at least enough for it to work)
Or a series resistor at the transmitting end (though this may involve cutting the trace and scraping away some mask for pads - I have done similar for hacks with 0603 resistors, not pleasant but possible with a wide enough trace and careful/delicate touch - set soldering iron lower than normal to avoid lifting trace)
You will need to work out the values according to estimated trace impedance and driver output impedance (should be some details in the docs for this)

Let us know how it goes if you do attempt any of this (scope shots are always handy) and good luck.

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I've found the problem. One of the FPGA power pins was not connected. JTAG now works! Thanks. –  Randomblue Jan 17 '13 at 10:08
    
Ah-ha! great, glad it's working now. –  Oli Glaser Jan 17 '13 at 16:51

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