FPGA power usage estimate

I've put together a power usage estimate for the FPGA board I'm developing and these are the numbers:

Voltage     Expected Current     Possible Supply?        Notable Peripherals
1.2V        1.578 A              2A     3A               ETH PHY
1.8V        0.754 A              1A     1.5A             DDR2 SDRAM
2.5V        1.124 A              1.5A   2A               ETH PHY
3.3V        0.903 A              1A     1.5A   2A        DVI


Do you think these numbers are reasonable in your experience?

I know that FPGA power usage varies a lot with the firmware application, so I used the Xilinx Spartan 6 excel spreadsheet for that and the datasheets for everything else, however the Xilinx 601 dev board on which I'm basing my design has 8A (!) ratings for all major rails (1.2,1.8,2.5,3.3), which seems quite excessive to me (and is making me quite concerned that my calculations are incorrect). Does the current usage by an FPGA really get this high?

The only extra thing it's using that I'm not is the SERDES + SFP connector which probably does use a bit of current (I can't imagine more than an amp?)

Also, I guess it's prudent to give myself a bit of PSU headroom. I'm not 100% sure on my figures so I'm going almost double in some places, still a lot less than 8A!

Also, chip recommendations? Is there anying I should be looking for in a regulator chip specifically for FPGA usage (low noise, etc?)

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Give more to DDR2 RAM... E.g. I know a project, when DDR3 80bit bus memory ate up to 10A during a read burst. –  Socrates Jan 17 '13 at 7:32
@Socrates: woah. I got 440mA for my device (MT47H64M16-25E: download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf) on page 29 for my cycle time (-25E/2.5ns). Is there anything else I need to take into account (16 bit wide bus, only 1 DDR2 SDRAM chip)? –  Stacey Jan 17 '13 at 8:00
Count in termination currents, pull-ups, pull-downs plus add some safe space of current, because huge current burst would decrease the voltage and require even more current then. –  Socrates Jan 17 '13 at 8:19
How much DDR2 (bit width, number of chips)? How are you terminating the data lines? –  Martin Thompson Jan 17 '13 at 17:33
@martinthompson: 1 chip, 16 bit bus, I think my case is borderline capable of getting away with no parallel termination but will probably be safe and parallel terminate the address lines with isolated vtt anyway. I'm just unsure how much current that termination will draw. I know it can be big. running at 312.5 mhz (625 mhz datarate) –  Stacey Jan 18 '13 at 1:22

In one of my recent project, I worked on a FPGA/ASIC running 10GHz SERDES. Our board comprised of 10 power supplies with various voltage and current requirements. It would be a good estimate to keep the current requirement double than the required unless board space is a constraint.

More attention needs to be paid on the ripple than any other factor in power supply. Noise plays a big factor on FPGA power supplies. Make sure you put enough ground plane layers to minimize noise. I have seen FPGA boards not working due to noise.

For noise insensitive rails, you can use LTC DC-DC power modules. They deliver a lot of current in a small package.

For noise sensitive rails like SERDES IO, a LDO with low ripple should be used along with a suitable DC-DC module in the back-end. Check your FPGA datasheet for ripple tolerance on different rails.

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