When using D latches for a shift register, it's absolutely imperative that the guaranteed minimum propagation time for each flop exceeds the maximum required hold time for the next. If that condition were not met, it would indeed be possible for one clock pulse to end up trashing the contents of all the bits. For some reason, manufacturers often don't specify the timings for their parts in such a way as to guarantee that those timing constraints will be met (minimum guaranteed propagation time is often zero, while hold times are sometimes positive) but in practice, for flops within a chip, and usually for all the flops within a batch of chips, any factors which would cause the hold time to be at the high end of its range will cause the propagation time to also be at the high end of its range, and vice versa.
Incidentally, when implementing a shift register within a CPLD or FPGA, the normal approach is to use D latches; when implementing them in silicon, though, other approaches may be more efficient. In many cases, a device will use two transparent latches per bit, with alternate latches activated by different non-overlapping clocks. One could further improve upon the spacial efficiency of this by having groups of N bits each represented using N+1 latches strobed by N+1 clocks [the common method has N=1, but going to N=2 would represent a 33% reduction in the number of latches] but I'm not aware of that being done in practice.
Also, FYI, if one can guarantee that data will be continuously shifted at some minimum rate, it's possible to reduce the transistor count to 3 per latch [or two transistors and a passive pull-up]. The video memory for the original Apple I computer used 1Kbit shift registers which were in 8-pin DIP packages and were, from what I've read, by far the cheapest form of memory available. I don't think such techniques are used much anymore, since they rely upon a certain relationship between transistor leakage and gate-source, gate-drain, and gate-substrate capacitances, but I still find them interesting.