I have a big design implemented in Verilog. The design has FIFO as shown in the image below. Due to some reason I have to add a new "Consumer" block shown.
The issue is, this block needs all the rows from the source block (FIFO in this case, which I cannot modify) simultaneously in single clock. What should I do? what intermediate block I can implement that will satisfy the requirement of the Consumer block. Right now the read pointer is reading data sequentially.