# In which cases should I use Z as output in HDL?

I created a simple multiplexer which feeds different input into output depending on statemachine. Now there are states when I do not need the output so I usually set it to 0.

INST <= "01" WHEN fsm_state =  read_first_half
OR fsm_state =  read_second_half
OR fsm_state =  next_r ELSE
"10" WHEN fsm_state =  write_first_half
OR  fsm_state =  write_second_half
OR  fsm_state =  next_w
ELSE  "00";


As far as I remember there was a third syntetisable value 'Z'. I far as I remember it's floating value with high impedance. When do I use it and is it safe to use? Will it be syntetisable on all FPGAs?

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When you don't care about an output value given a set of inputs, use '-' which means "don't care". The synthesizer will simply assign values that optimize resources/performance. Note that a simulator however has the option of keeping '-' as an actual value, and this will actually help you in making sure that having a "don't care" in there will not impact the relevant parts of your design.

'Z' or "high impedance" in FPGAs is only used for tri-state outputs, which nowadays are only available at the actual pins of the chip, not for internal logic. Modern FPGAs manufacturers simply don't allocate internal routing resources for them, and are only intended for interfacing with external chips/components. For internal logic the same functionality (such as bus arbitration) can be achieved with regular logic gates instead.

These definitions can be found in the IEEE std_logic_1164.vhdl library: http://standards.ieee.org/downloads/1076/1076.2-1996/std_logic_1164.vhdl

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I2C is a good example. The ACK bit requires a high-Z output state since the slave will be sending a logic high back. See prodigytechno.com/blog/wp-content/uploads/2011/12/… for reference. –  Matt Young Jan 19 '13 at 20:46
@Martin Thompson Fixed. Thanks for the comment. I've also edited the answer to include a link to the ieee library that defines std_logic. –  apalopohapa Jan 21 '13 at 17:54
@apalopohapa: Thanks - it would also be worth mentioning that - is a value in its own right, so to get it to actually behave as a don't care in a comparison you have to use the std_match() function... –  Martin Thompson Jan 21 '13 at 17:57

There isn't really a reason to put an output in tristate ('Z') if the IO is only an output and not an 'inout'. Also, having a '1' or a '0' at the output makes debugging (measuring) easier.

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REALLY? What would you do when you connect to I2C bus? –  FarhadA Jan 20 '13 at 0:46
@FarhadA Then I think that would fall under 'inout' case that vermaete mentioned. –  W5VO Jan 20 '13 at 5:03
Ofcourse, my point is only valid if it's a normal output at the FPGA connected to somewhere a normal input. –  vermaete Jan 20 '13 at 8:51
Even for a tristate buffer, I would prefer to have a set of input, output and output enable at the entity of the component and inserting the bidirectional buffer at toplevel. –  vermaete Jan 20 '13 at 8:53
So you make the ACK signal of the I2C as input? Well, I believe you will up to a big surprise when debugging your design. –  FarhadA Jan 20 '13 at 11:39

I can think of many cases where you would use the Z on signals, both internal and on the pins. For example, if you have a bus that is driven from multiple sources, you can control it by putting all the other driving signals to Z. Some FPGAs support this internally, but no all of them.

As for output signals, many times, you do not want to drive signals, such as data out of your FPGA, because those signals maybe shared between multiple devices. Some choose to change the direction of the signals instead of putting the output to Z, which makes it easier to debug.

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INST <= "01" WHEN fsm_state =  read_first_half
OR fsm_state =  read_second_half
OR fsm_state =  next_r ELSE
"10" WHEN fsm_state =  write_first_half
OR  fsm_state =  write_second_half
OR  fsm_state =  next_w
ELSE  "--"; -- don't cares


The synthesizer should come up with something optimal (but not necessarily predicatable)

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