# n bit shift register (Serial in Serial out) in VHDL

I'm creating an n bit shift register. When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low. I've put a for loop to shift n times inside a process. My code is given below.

I don't think the for loop is working, as the shifting is not restricted to n times. Where am I going wrong?

library ieee;
use ieee.std_logic_1164.all;

entity SReg is

generic (
n  : integer := 4
);

port(
clk:              in std_logic;
reset:            in std_logic;
enable:           in std_logic;    --enables shifting
parallel_in:      in std_logic_vector(n-1 downto 0);
s_in:             in std_logic;    --serial input
s_out:            out std_logic   --serial output
);
end SReg;

architecture behavioral of SReg is
signal temp_reg: std_logic_vector(n-1 downto 0) := (Others => '0');
begin
process (clk,reset)
begin
if (reset = '1') then
temp_reg <= parallel_in;
elsif (clk'event and clk='1') then
if (enable ='1') then
--shifting n number of bits
for i in 0 to n-1 loop
s_out <= temp_reg(0);
temp_reg <= s_in & temp_reg(n-1 downto 1);
end loop;
end if;
end if;
end process;
end behavioral;

-

In VHDL, a for loop executes in zero time. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. This is what's happening in your code. The entire loop is executing in a single clock cycle, and the value of s_out is only going to change once - to the value it was when the loop ended, which in this case is s_in shifted by 4.

What you really want is a loop where each iteration occurs on a new clock edge. This allows for s_in to be shifted out of s_out ever clock cycle.

Performing a loop where each iteration occurs on a clock edge does not require a for loop command, instead it takes advantage of the sensitivity list of the process. Here's how:

A process is triggered every time one of the signals on the sensitivity list ("clk, reset" in this case) changes. This means that the process is already looping every clock cycle (if a clock is in the sensitivity list). You can use this to your advantage in order to perform a for-loop type operation, where every iteration of the loop occurs on a clock cycle.

First you need a counter:

process(clk,reset)
variable shift_counter: integer := 0;
begin


shift_counter keeps track of how many iterations (or shifts) have occurred so far. you'll compare shift_counter to n-1 to see if you're done yet.

Next it might be a good idea to think of the states your process will be in. Perhaps a wait state for when the process is not shifting, and a shifting state for when it is.

The state signal definition:

 TYPE POSSIBLE_STATES IS (waiting, shifting);
signal state : POSSIBLE_STATES;


In the process proper:

case state is
when waiting =>


Ok, so what happens when we're waiting for an enable? It would be a good idea to set all (driven) variables to a known value. This means that maybe something like this is a good idea:

shift_counter := 0;
temp_reg <= parallel_in;
s_out <= '0';


This is useful to do because then you know exactly what your signal values are when enable goes high. Also, at the end of the shift, you can change states back to "waiting" in order to get ready for enable again.

So what is going to trigger a state change from waiting to shifting ? That's easy:

if(enable = '1') then
state <= shifting;
else
state <= waiting;
end if;


Ok, so next state. shifting.

First, we want to increment the shift counter, and perform the actual shift:

when shifting =>
shift_counter := shift_counter + 1;
s_out <= temp_reg(0);
temp_reg <= s_in & temp_reg(n-1 downto 1);


And then also detect when the shifting is done, in order to leave the shift state and go back to waiting:

if (shift_counter >= n-1) then
state <= waiting;
else
state <= shifting;
end if;


And that's it!

In the below chunk of code, note that the "reset" state and the "waiting" state are distinct. This is useful because generally the asynchronous reset only occurs at startup and is not expected to process any data during this time. By moving the temp_reg <= parallel_in to the waiting state (outside of the asynchronous reset), we are allowing the module driving parallel_in to start up correctly without having to send data during reset. Also, now the waiting state can be entered as necessary, without having to perform an asynchronous reset.

Also notice that I'm only driving 3 signals (4 counting the variable) in my process, and only those signals. If a signal is driven in one process, it shouldn't be driven anywhere else but that process. Not outside the process, not in another process. A signal is driven inside one process and one process only. You can compare the signal to other signals in other places (if statements, and such), but don't give the signal a value anywhere except in one process. And generally, it is defined in the reset portion, and then wherever necessary in the process proper. But only 1 process. If I'd been told this, it would have saved me tons of time while I was learning.

Here's the whole code in one chunk:

library ieee;

use ieee.std_logic_1164.all;

entity SReg is

generic ( n : integer := 4);

port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic; --enables shifting
parallel_in: in std_logic_vector(n-1 downto 0);
s_in: in std_logic; --serial input
s_out: out std_logic --serial output

);
end SReg;

architecture behavioral of SReg is

signal temp_reg: std_logic_vector(n-1 downto 0) := (Others => '0');
TYPE POSSIBLE_STATES IS (waiting, shifting);
signal state : POSSIBLE_STATES;
begin

process(clk,reset)
variable shift_counter: integer := 0;
begin

if(reset = '1') then
temp_reg <= (others => '0');
state <= waiting;
shift_counter := 0;
elsif(clk'event and clk='1') then
case state is
when waiting =>
shift_counter := 0;
temp_reg <= parallel_in;
s_out <= '0';
if(enable = '1') then
state <= shifting;
else
state <= waiting;
end if;
when shifting =>
shift_counter := shift_counter + 1;
s_out <= temp_reg(0);
temp_reg <= s_in & temp_reg(n-1 downto 1);
if (shift_counter >= n-1) then
state <= waiting;
else
state <= shifting;
end if;
end case;
end if;
end process;

end behavioral;

-
Stacey Anne Rieck, that taught me alot. I sincerely thank you for your help. – Orange Feb 6 '13 at 14:35

@StaceyAnnRieck's answer is impresively thorough and quite accurate... if I may summarize/clarify the first statement though, the 'for' statement in an HDL simply expresses 'syntactic replication' not 'sequential execution'.

That is to say, it simply generates more hardware elements (gates), and does not inform process flow. I would say the loop is expanded at elaboration time (compilation), not that it 'executes in zero time', after all at runtime there will still be propagation delay through the elements generated by the 'for' construct.

Don't start by writing VHDL code, start by drawing logic schematics (at least at some level of abstraction). At the end of the day HDL is just a text-based way of expressing the content of logic schematics.

-
Thanks vicatcu! – Orange Feb 6 '13 at 14:36
Although people have different approaches to digital design, your description of the for statement is not entirely correct. If you consider the generate statement then your description is true, but if you consider the loop statement inside a process, this is sequential code. If you loop contain signal assignments to the same signal then the previous assignment is overwritten by the next one, but if your dealing with variable it behaves just like regular sequential code. – trondd Jan 20 '14 at 12:37

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