What disadvantages can i run into when using weak internal pullups (100k) on microcontrollers. I'm wondering how susceptible lines (with only parasitic trace/component capacitance) become to EMI transients with these weak pullups. Digital filtering with a 3-4ms window may decrease the odds of transients having an effect but is there anything else to keep in mind on a professional pcb ?
If this is a concern to you, then the only real answer is to model the end result. You have to understand how much coupling capacitance there is to an aggressor signal, and you have to understand how much swing is acceptable on the input pin before it causes problems.
While this sounds hard to do, usually if you use simple capacitor formulaes and ensure that you over estimate the coupling most rules of thumb indicate that there isn't anything that needs to be done. This is what probably informed the manufacturer to choice the size of PU that they did.
Kudos to you for thinking about these things, it's attention to details like this, that when you work it through give you a good background to do good designs.
protected by W5VO♦ Feb 24 '13 at 16:34
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