# CMOS Inverter Voltage Transfer Function

So let's say I have a perfectly symmetrical Voltage transfer function curve for my CMOS inverter. The curve looks like this:

The question is, how would this curve change if the size of the NMOS transistor was reduced.

My answer: The curve would still be symmetric but would start shifting right.

But I just know that from my textbook, I don't understand WHY the curve would shift right.

So why exactly will it maintain symmetry and shift right?

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The voltage shifts because additional over drive voltage is required to generate additional $I_{ds}$ to match the $I_{ds}$ of the PMOS. This arises because of the reduction of W reduces the $g_m$ of the NMOS transistor.

The curve will have it's roughly sigmoid shape, which is dictated by how the transistors transition from triode to full active, but they will not be perfectly symmetrical. $V_{th}$ , $g_m$ are very unlikely to be perfectly matched.

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What would happen if VDD were less than the sum of the threshold voltages for the NMOS and PMOS transistors? My instinct would be that the inverter would show some vague hysteresis behavior, but a mushy signal passed through multiple inverters would remain mushy (unlike Schmidt trigger inverters which add hysteresis and give clean outputs). I could imagine that metastability would be a bigger problem at low voltages, requiring something more than a double synchronizer, but I don't really know. –  supercat Nov 25 '13 at 18:51