XOR gate; transistor level design [duplicate]

Question

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What would a transistor level design of an XOR gate look like?

The design of a logic gate doesn't fall under our scope, I think. I'm inclined to agree with @Qmechanic that this might go better on EE.
Possible duplicate: electronics.stackexchange.com/q/53142/17592
The answer to this question depends on what kind of interfacing you want: how are logic levels represented on the inputs and outputs.

rawbrawb · Answer 1 · 2013-03-15 19:10:09Z

up vote 2 down vote

Given XOR = /A*B + A*/B you can build it out of the following:

AND:

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OR:

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NOT:

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But my favorite is:

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where:

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But the TG based design has limitations. You can't cascade them and must have a driven input and a CMOS load.

answered Mar 15 at 19:10

rawbrawb
8,53311045

	In NMOS technology, if one needs an XOR gate and the inputs come from logic that isn't driving anything else, one could get by with two transistors and one passive pull-up: simply connect the drains of the two transistors to the pull-up, connect A to the source of one and gate of the other, and B to the remaining source and drain. Even if one had to add inverters before the XOR gate which served no purpose except to drive it, it would still be more compact than other realizations. I wonder if any NMOS chips used such a design? – supercat Mar 15 at 19:37
	@supercat My guess is: they must have, since most of those designs were done in the ruby-lith days, they'd be looking to minimize the # of transistors. – rawbrawb Mar 15 at 19:51
	It's possible that they did so, but in the schematics I've seen of NMOS devices XOR gates are implemented in other ways. – supercat Mar 15 at 20:02

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