The simple point I'm trying to make for an essay Im writing. I'm completely at a loss as to how to answer this. Any help available? Sorry, I know this is not a well formed question but I've got no other places I know of to ask left.
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\$\begingroup\$ Which device are you referring to? \$\endgroup\$– Andy akaMay 5, 2013 at 20:45
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1\$\begingroup\$ Is this for an assignment? Hints: What have you learned about simple latches? How many clock cycles does it take to latch data into it? What do you know about multiplexer/demultiplexers? Do you need a clock to make muxes/demuxes work? \$\endgroup\$– shimofuriMay 5, 2013 at 20:49
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\$\begingroup\$ This is a great question about fundamentals of computer architecture. It most likely reflects academic chalkboard designs rather than those you can buy, but with FPGAs it's practical to build one for fun... that is as long as you forgo using the block RAMS which have registered address inputs as a performance optimization rather that out of ultimate necessity - older discrete RAMs do not, nor would a 3-port register file implemented in the FPGA logic fabric. \$\endgroup\$– Chris StrattonMay 6, 2013 at 1:05
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1\$\begingroup\$ You are right in that this is not a well formed question as it is right now, so needs to be closed in its current form. However, you should be able to fix it. For one, never rely on the title to understand the question. It is also unclear if you are trying to design the architecture or asking how to use the instruction set of some existing architecture. \$\endgroup\$– Olin LathropMay 6, 2013 at 12:28
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von Neumann's cycle, fetching, decoding and executing (sometimes a separate writeback) cannot be done in a single clock cycle. That is probably what you are referring to.
What is happening is a technique called 'pipelining'. While one instruction is executed, a second one is decoded and a third one is fetched from memory. All three in parallel during the same clock cycle. A single instruction still takes 3 clock cycles, but the parallel mechanism averages to 1 cycle per instruction.
Some instructions like branches/jumps take disproportionate many clock cycles (3 or 3) because they break the pipeline. The instructions being decoded and fetched have to be flushed and the pipeline has to reload.
Some modern processors are even more optimized than this. They can predict what will happen and hence the technique is called 'branch prediction'.
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\$\begingroup\$ Perfect!! thank you, it was simply a matter of me mis understanding what the question wanted it seems! pipe-lining was the keyword i need to remember aha, thanks again. \$\endgroup\$– BroakMay 5, 2013 at 21:06
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\$\begingroup\$ This opening assertion of answer is incorrect. It can be done, by using a multiport register file and a design that is entirely combinatorial and registers nothing until the results are written back at the concluding clock edge. However, this is very slow - a pipelined design is almost always chosen since it can have throughput approaching the reciprocal of the longest register-to-register combinatorial delay in a process which can now be broken up into smaller (and thus quicker) combinatorial paths. \$\endgroup\$ May 5, 2013 at 23:06
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\$\begingroup\$ Granted, a von Neumann architecture with a single-port memory used for both program and data storage cannot access it for data during the same cycle in which it fetches any instruction, but then a sequential pipeline as described here does not by itself solve that problem since instruction fetching will have to be suspended during some cycle so that data access can take place. The question itself could be satisfied by a Harvard architecture with distinct program and data memories, and thus immunity to this problem. \$\endgroup\$ May 6, 2013 at 1:00