Edge triggering seems to me leaving every circuit in an inconsistent state?

Question

I was informed on this forum that edge triggering could be a solution for multiple propagation in a circuit with feedback (the output wired back to the input).

But to me edge triggering seems to leave a circuit in a completely inconsistent state. Look at this one (one-element JK flip flop ripple counter).

Let the clock input be edge-triggering signal and look at the first NAND field at J when all inputs at J are high but the clock. At the moment the clock gets high the propagation starts. The edge lasts for a nanosecond so it will probably end before the value propagates through the NAND. Anyway, a nanosecond-long low signal will travel through the output of the first NAND, preceded and followed by long intervals of high signal. That composition will get to the the second upper NAND and the NAND will change values accordingly, further branch-wired to another NAND plus an input, and it all looks like a great example of an inconsistent state of a circuit to me - who knows what is going to happen there?

I don't get properly something about edge triggering. What is that? Thank you for the time!

Answer 1

It is difficult to understand what are you asking about without some sort of timing diagram.

However, I'll try to guess what your issue is:

There is broad interchangeable misuse of terms "gated latch", "flip flop" and "edge-triggered flip-flop". The schematic you provided is not JK edge-triggered flip-flop, but JK gated latch, commonly referred as JK flip-flop.

As opposed to edge triggered flip-flops which change state only on the rising edge of the clock signal, gated latches can change state during the whole positive phase of the clock signal. This means that if either J or K inputs change while the clock is high, the output of gated latch may change too (which is not true for edge-triggered flip-flops).

However, if J and K inputs are held constant during a positive phase of the clock, the output of JK gated latch will settle to a known value (with one exception described below), which may be derived from the values of J, K and Q at the rising edge of the clock. NOTE: the fact that we are looking at the values of the signals at the rising edge does not imply that this JK gated-latch is edge triggered, because we assumed that the inputs will not change during positive phase of the clock!!!

Now, to your question: it seems that you can't grasp how exactly the output may settle to a known (and deterministic) value, taking into account the two feedback loops present. Well, the only way you can convince yourself is to assume some initial conditions on the output and trace what happens for each possible combination of inputs (except J=1,K=1).

The following two points will make your life easier:

1. While the implementation with NAND gates is the most area effective, for the purpose of understanding the concepts it is best to investigate this (functionally equivalent) circuit:
2. Note that when the clock is high, the outputs of AND gates will be determined by the values of J and K inputs, and the value of Q. It means that you may erase the clock signal from the diagram in order to understand what's going on during the positive phase of the clock.

EDIT: So what about J=1, K=1 case? Well, in this case JK gated-latch becomes a multivariator (I hope the term is correct) - its outputs will be changing periodically during the positive phase of the clock. In logic circuits this combination of inputs is illegal, therefore the usual practice is to tie them together in the following manner (which is called D gated-latch):

Note that there are no need in feedback in this circuit, because the outputs are completely determined by the value of D input.

In order to construct edge-triggered JK flip-flop, one can put two JK gated-latches in series in the following way (there are also other configurations). Note that the feedback paths are from the output of the second gated latch to the input of first:

In this configuration there are no more restriction on J=1, K=1 input combination - this combination of inputs means "toggle the output". The so-called T edge-triggered flip-flop is usually derived from the above JK edge-triggered flip-flop by tying J and K inputs together.

Answer 2

The basic J K flip flop suffers from a timing problem called race where the trigger pulse is too long and the the circuit sends back confusing signals which is what I think you are describing.

To get around this the trigger or clock pulse has to be kept very short so that it returns to a '0' before the change in the output can be propagated back to the input gates.

The J-K flip flop operation can be improved by adding a second R-S flip flop and is known as a master-slave J-K.

At the rising edge of the clock signal, the J and K input values are propagated to and stored in the master flipflop, while the slave flipflop (which is controlled by the inverted clock) remains unchanged. On the falling edge of the clock signal, the output values of the master flip flops are propagated to and stored in the slave flipflop, which in turn drives the flipflop Q and Not Q outputs.

Answer 3

Most real circuits use D flip-flops, which have two relevant constraints: a "setup" time during which the signal must be constant before the edge arrives, and a "hold" time after the edge during which it does not arrive.

The design is then simulated and adjusted so that each signal arrives within the setup time and not earlier than the hold time. Yes, you can insert a delay element (e.g. pair of inverters) to meet the hold constraints.

Some designs of D flop can have a zero hold time, so that as soon as the edge arrives their input is locked in and stable.

("Edge lasts for a nanosecond": that feels rather high to me!)

Answer 4

Master-Slave flipflops, synchronous clocked switching and the like exist for a reason. Edge triggering can be designed to be statistically highly reliable in practice, but the hazards and shortcomings are well known. Edge triggering and asynchronous operation are usually cheaper and easier to design overall. As with most of life it is a tradeoff between many factors and can be made to work "entirely well enough" in many cases. You'll be less likely to find it in life support & fire control systems and, one hopes, satellite launchers.