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According to this paper http://www.fairchildsemi.com/an/AN/AN-9742.pdf

"However, a transformer may cause half bridge crossconduction due to the offset voltage of gatepulse deadtime stage."

Page 9 section "Gate driver design". looking at waveforms on page 10 figure 33 that shows the waveforms with a pulse-transformer, I think we can assume that the windings are from the same transformer, as is in some designs.

But if use only one transformer per IGBT, or just for the top side, I think the problem is solved, as the transformer will just reverse the current without the near "0V" space on dead-time, I'm right?

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If you use one transformer per IGBT only, then flux walk will become a problem depending on duty cycle. Then you usually add a capacitor in series on the driver output line - for achieving better results even the IGBT side will get an AC coupling circuit.

Take Lazlo Balogh's AN and look for AC coupled transformer gate drive for a discussion in detail. Here the corresponding excerpt: AC coupled gate drive transformer, Lazlo Balogh

Using this approach, i.e. 1 transformer to drive 2 transistors (one high, one low side) I wonder how a delay circuit would perform to ensure the proper switching delay. I quickly put together an example: Delay circuit example, created using KiCAD

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  • \$\begingroup\$ You could also mix one transformer for high side as there the transistor's source terminal can float with a usual low side driver as long as the high side is no direct transformer drive, i.e. if the transformer only supplies the gate drive voltage/current and another driver is used for control/switching this voltage supply on and off. The inductance must generally not be too different for High and low side if you are not using the dead time/delay circuit I added at the end of my answer. Inductance must be even for High and Low side switches. \$\endgroup\$ Nov 11, 2013 at 0:33
  • \$\begingroup\$ Your response was some contradictions like "Using this approach, i.e. 1 transformer to drive 2 transistors I wonder how a delay circuit (...)" this is explained in the paper and is what I'm trying to avoid. But I will give a correct one for the flux walk that I have not remembered when I made the question. \$\endgroup\$ Jan 7, 2014 at 21:33

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