Digital circuits that adds values

learn more… | top users | synonyms

0
votes
1answer
40 views

Why is a half adder implemented with XOR gates instead of OR gates?

Half adder circuits are implemented with XOR gates for the summing. Why can't the adding function be implemented with OR gates? What is the difference between using XOR gates and OR gates?
0
votes
1answer
22 views

Carry look ahead adder with 2-input gates?

I would like to make a 8 bit adder, with carry look ahead, but i only have 2-input logic gates. All I've heard about use some at least 4-input gates. Or do I need to use a totally different method, ...
2
votes
1answer
31 views

How does a half adder made of crossbar latches operate?

I am researching memristors, and one application that's frequently cited is a crossbar latch that sandwiches memristors between two layers of wires to form a grid. In most examples, this is configured ...
1
vote
1answer
34 views

How to use an H-clock tree in a pipelined adder

This is for a lab at my university. Normally I don't have a problem with these things, but this one is poorly written and the professor hasn't discussed the H-clock tree, which is where I'm getting ...
3
votes
1answer
70 views

Half Adder and Two Function, A Contest Questions?

I ran into a 2013 contest question on computer-science filed. What is the following True about F and G function. (The output ...
-5
votes
0answers
40 views

full adder - subtractor using two 4x1 multiplexers and external gates

Implement a full adder - subtractor using two 4x1 multiplexers and external gates. Hint: Once you design your full adder, you can improve it to an adder – subtractor circuit I try to draw can u ...
0
votes
1answer
41 views

Implementation of 4-bit subtractor

How to implement subtractor of two 4-bit numbers using subtractors of two 1-bit numbers as a module(no assembler coding, just expressions in boolean algebra)? If there are four 1-bit subtractors, how ...
0
votes
0answers
22 views

Voting System With Binary Adders

I found a design of voting system with using binary adders. In this implementation, they used 4-bit parallel adder to add results from full adders. As seen on picture, inputs 3-4 and Carry input ...
-1
votes
0answers
49 views

serial adder written in vhdl code (structural behavior)

How to write a code in VHDL using structural behavior --i try to write the code for the structure but can't connect them to each other the design like this image exactly...with clk for each register ...
0
votes
2answers
128 views

How to make 2 bit or more half adder circuit

I have no idea about electronics, this semester school gave us a strange and confusing lecture about circuits which we shouldn't take because we are no engineer or something close. Question is we ...
1
vote
2answers
257 views

Binary Adder and Parallel Adder

Are binary adder and parallel adder same thing? I couldn't find any information about parellel adder in my book. Does anybody have an idea?
3
votes
1answer
60 views

adding two 64-bits number with m-bit carry ripple adder and multiplexer, a questions?

I ran into a question from computer architecture class. The professor says that for adding two 64-bit numbers A and B we use m-bit carry ripple adders and multiplexers such as following: and that ...
1
vote
2answers
79 views

Using iSim to simulate 16-bit CLA schematic on Xilinx, all inputs and outputs on the waveform are 'X'. How can I debug?

I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers. Here is the ...
2
votes
2answers
64 views

Muxes, Adders, Comparators, and Gates

This question is actually from one of my previous discussions, which I still don't understand how to implement. The goal is to use abstraction to design a circuit, which converts two-digit ASCII ...
1
vote
2answers
60 views

Bit Slice Checker

I'm attempting to use bit-slice design, to implement a circuit which checks if an n-bit binary number A has an even number of 1's in its binary representation. I've decided that the circuit should ...
1
vote
2answers
111 views

Which 4-bit Binary Number Is Greater?

My Task I'm working on an extra work question our teacher assigned us from the book. Design a combinatorial circuit that compares two 4-bit unsigned numbers A and B to see whether B is greater than ...
0
votes
2answers
513 views

What would be the output of A = 0100 and B = 0111 with S = 1 in a 4-bit binary adder-subtractor?

I understand S = 1 means subtraction and S = 0 means addition. So then, the output would be the result of 0100 - 0111. But since it's negative, I'm not sure how it would be represented. I know the ...
1
vote
1answer
61 views

How to find gate delay for 4-bit look-ahead carry adder?

How can I find Gate Delay for bit 1 of the sum by a 4-bit look-ahead carry adder?
1
vote
1answer
156 views

Design a full adder of two 1-bit numbers using multiplexers 4/1

How can i implement the full adder of two 1-bit numbers using only multiplexers 4/1? I created a truth table for a one-bit full adder, which looks like this: A = first bit B = second bit Pu = bit ...
3
votes
6answers
198 views

Batteries in parallel vs voltage signals in parallel

From a practical point of view, when you connect two audio signals to one speaker the result is that both audio signals can be heard. That means the two voltage waves were added, correct? However, ...
0
votes
0answers
194 views

How can I use 3-input NAND gates to create a 1-bit full adder?

I have already implemented a 1-bit full adder with 9 2-input NAND gates. Out of curiosity, if the number of inputs on a NAND gate changed, say from 2 to 3, would the truth table and full adder ...
-4
votes
2answers
84 views

Design of a basic half-adder

I know that a half-adder is a combination of the gates: XOR, AND. But how are they combined? And can you give a example and explain which one is the XOR and which one is the AND.
1
vote
1answer
573 views

Signed Addition of two std logic vectors while looking for overflow and carry

I have what I think to be a working implentation for finding the sum of two signed 32 bit (std_logic_vector) vectors in which I chose to expand the result to always have 33 bits so as to preserve the ...
0
votes
1answer
55 views

Adder-Subtractor Circuit

For the above question I got the answers: a. SUM = 0110 | C = 1001 b. SUM = 0100 | C = 1010 Are these answers correct and how is the overflow calculated?
0
votes
1answer
72 views

Truth Table, Full-adder

I'm trying to solve two questions that I am unsure how to approach. I know boolean means true/false but that's about it. The question reads: "A boolean equation in sum-of-products can be minimized ...
0
votes
1answer
60 views

Building a 2-bit adder with a propagation delay of at most 2 gates

An XOR-gate itself counts as 2 gates, so if I use an XOR-gate the delay would already be 2. I have no idea how to do this, as a full adder for one bit already contains 2 XOR-gates (or 1 XOR-gate, 1 ...
1
vote
1answer
139 views

How would you make a 3-bit binary adder that adds two instead of 1?

I am trying to make an asynchronous adder that holds three bits and adds two to the number. Can someone help? A Google search shows nothing and I'm having a hard time visualizing how to make the ...
0
votes
1answer
56 views

Help designing a serial adder [closed]

I need to build a circuit that adds two n-bit 2's complement numbers. the two numbers have to be stored in shift registers. The circuit should start with the least significant bits of each number and ...
0
votes
0answers
97 views

4:2 compressors gate count increasing but area decreasing, How?

From literature's I got below definition, ...
-1
votes
1answer
121 views

Parallel MAC unit based on modified booth algorithm

The below diagram is the parallel MAC structure. In parallel MAC both partial product addition and accumulation take place at same time. The partial product summation + accumulation unit of above ...
0
votes
1answer
90 views

OLA adder and signed digit vhdl design problem

I have implemented the following online adder for signed digit using vhdl code and I have simulated my design according to the example table shown in the figure attached the problem is I am not ...
0
votes
2answers
793 views

2-bit adder implementation

How can I implement this 2-bit adder circuit: (source) Onto http://www.neuroproductions.be/logic-lab/ or logic.ly? After several attempts (and in spite of the half adder and full adder working) I ...
0
votes
0answers
298 views

Spikes in full adder Spice netlist

I currently have a 1 bit full adder waveform which has the following circuit and here is the following netlist which I will simulate via Hspice ...
0
votes
0answers
252 views

How ALU Perform decrement operation using LOGIC Zero

I google many ALU Block diagram for decrement operation.all same as shown below. This 1 bit alu perform 8 operation depending upon select line status Theoretically all operation seems works ...
0
votes
2answers
97 views

Find x cubed with half adder

My excercise is the following: Make a circuit which outputs X^3 of two bit input of X. Use the lowest number of HALF ADDERS as you can. I don't really understand ...
0
votes
1answer
82 views

Sum 4 numbers, 1 bit each, with three full adders

My excercise is the following: Make a circuit which sums 4 binary numbers, one bit each, with three full adders. My solution was the following (sorry I can't ...
1
vote
2answers
205 views

How can I add three AC signals?

I have three light sensors which outputs appropriate AC currents with respect to light intensities. I only have one pin left for my ADC IC that I have on my board so I can't sample three sensors using ...
1
vote
0answers
145 views

ALU using full adder and MUX [closed]

I am trying to implement a 1 bit ALU on Tanner EDA. I have a separate full adder and 2:1,4:1 MUX circuits. My question is: How do I interconnect the full adder to the MUXes, so that it work as an ALU? ...
0
votes
0answers
121 views

Integrated Circuit Multiplier Circuit Problem

I'm developing an 8bit x 8bit IC signed multiplier using FULL adder cells. Once I get partial products, I add them together. The problem I have occurs in this stage, adding of the products. This is ...
1
vote
1answer
154 views

Can anyone explain to me how a carry select adder works?

Doesn't get more complex then the question above. I've been looking through textbooks and using google and I feel like the explanations are not suffice or unclear. Can anyone explain this to me well?
0
votes
2answers
941 views

1bit Full Adder Cell in IC not working as supposed?

I got an adder cell, which in IC mirror layout is this: EDIT: Transistor-level, standard adder circuit: Which I actually made in IC like this: It's not working as it should! I labelled it ...
2
votes
1answer
147 views

Synchronizing multiplier with adder to form mac

I have designed an 8-bit multiplier in Verilog which takes a maximum of 8 clock cycles to give the product. I have also coded a 16 bit adder based on combinational logic. I now want to integrate the ...
0
votes
1answer
92 views

Why is my adder giving me the wrong output?

So I made this circuit right from my professor's notes. It is a carry ripple adder. I've been testing it out and one of the problems it has is this: When you turn on all three inputs, it does not ...
0
votes
0answers
71 views

How do I minimize the size of a 3-input parallel adder?

Currently this alu uses 24 logic elements, most likely from the adders. I'm wondering if there is any tool in Altera/Quartus I can use to minimize this? For my design, multiplier and RAM modules are ...
2
votes
1answer
164 views

How do carry save adders work?

I thought I understood the concept but wikipedia has confused me. There are two outputs because one's for a partial sum and one's the carry bits. But why must it be used to "compute the sum of three ...
1
vote
1answer
3k views

Design of a 1-bit adder-subtractor with additional carry/borrow input

I have to design a 1-bit binary adder/subtractor unit that can both add or subtract two input values A and B depending on a control input C (it is assumed that two's complement is used). Also, the ...
-1
votes
2answers
151 views

does this design look suitable for a 4-bit adder

I am working on a project that will include a basic 4-bit adder, I have designed a layout is Adobe Illustrator and would like people to check over it to see if it looks like it should work. I am very ...
3
votes
1answer
193 views

Building a small 4-bit adder on a breadboard

I am very new to using IC and basically a breadboard in general, but I am doing a project on how computers add and thought it would be nice to have a practical demonstration. My main question is, for ...
0
votes
1answer
174 views

Working of Prefix Adder

I am trying to understand the working of Brent Kung adder, but I have not been able to. All that I see in tutorials is just the figure above for carry generation. Can anybody explain it to me with ...
0
votes
0answers
41 views

3 bit x 3 bit multiplier. How to add the 3 partial products? [duplicate]

I want to implement a circuit for a 3 bit x 3 bit multiplier and i am confused as of how im supposed to add the 3 partial products. I know it should be like that : ...