Digital circuits that adds values

learn more… | top users | synonyms

0
votes
1answer
20 views

Full adder (FA) base 8(Octal)

Please give me some help or tip about this question, I need to make a simulation of this on proteus: " Using full adder(FA) design a adder for numbers in base 8(octal) 6(8) + 4(8) = 12(8) " As ...
0
votes
1answer
19 views

8 bit adder with 2 CLA

I need to make an 8 bit adder with 2 4-bit look ahead adders.I spent a lot of time reading about it and I think I get the gist of how it works, but I can't seem to get this. I spent a lot of time ...
-5
votes
0answers
55 views

3 Bit Adder with only AND & OR

The design must have 6 input. 3 inputs represent 3 bits of a number x, and 3 inputs represent 3 bits of a number y. There are 4 outputs in this design. How do you design the 3-bit adder with only AND ...
-1
votes
1answer
31 views

Multiplier 4-bit with verilog using just full adders

I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right. here's a pic to give you some idea of what i am ...
0
votes
2answers
55 views

Which gate is better in buildiing the Full Adder ? XOR or OR

So this is question asked in one of the exams. As you know there are 2 ways to get the boolean expression for the Sum of the fully adder Given X and Y are inputs, C0 is the carry from previous adder ...
0
votes
1answer
56 views

calculate clock cycle of ripple Carry and lookahead adder

How would you find the number of clock cycles it takes to produce sum, the carry out, and overflow flag using ripple carry or lookahead adder. Can someone please explain me how would we go on finding ...
0
votes
1answer
78 views

How to create a 64 bit Carry Look ahead adder?

I am trying to implement the verilog code using generate statement.There is issue with taking four bits for calculating P and G values.Added the code below for reference. Cin is taken as Zero. ...
1
vote
2answers
78 views

Design an ALU that only adds

I need some help designing a simple ALU that only can add (4-bit) numbers. For the design I can only use 4-bit full adders and 4-bit edge-triggered flip-flops. I am stuck as I do not even know where ...
1
vote
2answers
204 views

VHDL serial adder test bench return UUUU

I've designed some week ago this serial adder, then i let it go for a while and now i would like to state if it works or not... So the design is this one this one And i report to you the testbench ...
1
vote
3answers
67 views

How does Instruction Code tell an automated adder what to do? (Charles Petzold Code book, Chapter 17 Automation)

I'm reading Chapter 17 of Charles Petzold book Code (which is excellent) and in it he's describing an automated adder which he's adding different Operation Codes or Instruction Codes. In the ...
1
vote
0answers
451 views

Serial Adder vhdl design

I've a design problem in VHDL with a serial adder. The block diagram is taken from a book. Since i'm not skilled enough in design with clock (except some silly flip flop i've found on the web, and ...
1
vote
1answer
57 views

Multioperand pipelined adder

in order to explain how to a pipelined multioperand adder could be implemented my book shows the image reported below. The idea is to use three adder with 4 stage pipeline. However i tried to make a ...
0
votes
0answers
51 views

Difference between the Carry Ripple adder and Carry Sensing Completion Detection Adder, how to implement in vhdl?

I don't understand how the carry completion adder works. My book says that it is very similar to a ripple adder, but it achieves better perfomance since it exploits average carry propagation times ...
-1
votes
1answer
134 views

Implementing this Full Adder circuit

For my class, I have to implement the following circuit on a breadboard but I don't really have an idea on how to start. Basically, I have a 4-bit Full Adder and I will input two 4-bit binary numbers ...
0
votes
1answer
62 views

4 bit subtractor using 2's complement of an adder

currently having problem with my carry in to carry out. i have used this for my LSB assign S=A^(~B+1)^Cin; assign COUT=(A&~B)|((CIN+1)&(A^~B)); and this for my 3 higher bits. ...
0
votes
3answers
117 views

Is there a way to count the number of high inputs with logic gates?

I have \$2^n\$ inputs \$a_{0}, a_{1} .. a_{2^n}\$, these can be either hich or low, and \$n\$ outputs \$z_{0}, z_{1} .. z_{n}\$, these give out a binary number of how many of the inputs are high. Is ...
0
votes
2answers
78 views

Half Adder Using 4069 and 4011 Chips

I am having trouble designing a wiring diagram for a half adder using the following two chips: CD4069 (hex inverter) HEF4011 (quad 2-input NAND) Can someone guide me in the right direction?
0
votes
2answers
77 views

VHDL - Cheapest-Fastest unsigned to signed binary number converter

We know that to convert unsigned to signed (precisely, I want to convert a pure binary into CA2 number) we must negate the unsigned number adding, then, + 1. In VHDL I can implement an inverter and an ...
0
votes
0answers
105 views

NCO synthesis with VHDL

I'm trying to build a function generator with an FPGA. I can generate different waves at different frequencies but the problem is that I have a lot of jitter. I think the problem is the overflow of ...
-1
votes
1answer
230 views

My output in verilog is high impedance all the time. Why is that?

I am new to verilog and I have been writing code for 4 bit adder/substractor in structural model. My values of x0,x1,x2,x3,c1,c2,c3,cb and ...
4
votes
3answers
629 views

What is the purpose of a “carry in”?

I'm currently trying to learn how binary adders work, but I don't understand what a "carry in" is for. What is the purpose of a "carry in"?
0
votes
1answer
73 views

Arithmetic Circuits (ADDERS!)

I usually only become a passive reader in this forum, but today I decided to ask my first question. How many logic gates required for a 4-bit Carry Look Ahead adder and Prefix adder? I know that ...
1
vote
1answer
56 views

Working with borrow save signed digit arithmetic output mismatch

I am working with OLA adders the borrow save module for signed digit addition I implemented the added in vhdl modeling the following picture I have run the following example as given in the table ...
0
votes
1answer
692 views

Why is a half adder implemented with XOR gates instead of OR gates?

Half adder circuits are implemented with XOR gates for the summing. Why can't the adding function be implemented with OR gates? What is the difference between using XOR gates and OR gates?
0
votes
1answer
71 views

Carry look ahead adder with 2-input gates?

I would like to make a 8 bit adder, with carry look ahead, but i only have 2-input logic gates. All I've heard about use some at least 4-input gates. Or do I need to use a totally different method, ...
2
votes
1answer
81 views

How does a half adder made of crossbar latches operate?

I am researching memristors, and one application that's frequently cited is a crossbar latch that sandwiches memristors between two layers of wires to form a grid. In most examples, this is configured ...
1
vote
1answer
137 views

How to use an H-clock tree in a pipelined adder

This is for a lab at my university. Normally I don't have a problem with these things, but this one is poorly written and the professor hasn't discussed the H-clock tree, which is where I'm getting ...
3
votes
1answer
165 views

Half Adder and Two Function, A Contest Questions?

I ran into a 2013 contest question on computer-science filed. What is the following True about F and G function. (The output ...
0
votes
1answer
150 views

Implementation of 4-bit subtractor

How to implement subtractor of two 4-bit numbers using subtractors of two 1-bit numbers as a module(no assembler coding, just expressions in boolean algebra)? If there are four 1-bit subtractors, how ...
1
vote
2answers
1k views

How to make 2 bit or more half adder circuit

I have no idea about electronics, this semester school gave us a strange and confusing lecture about circuits which we shouldn't take because we are no engineer or something close. Question is we ...
2
votes
2answers
5k views

Binary Adder and Parallel Adder

Are binary adder and parallel adder same thing? I couldn't find any information about parellel adder in my book. Does anybody have an idea?
3
votes
1answer
224 views

adding two 64-bits number with m-bit carry ripple adder and multiplexer, a questions?

I ran into a question from computer architecture class. The professor says that for adding two 64-bit numbers A and B we use m-bit carry ripple adders and multiplexers such as following: and that ...
1
vote
2answers
266 views

Using iSim to simulate 16-bit CLA schematic on Xilinx, all inputs and outputs on the waveform are 'X'. How can I debug?

I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers. Here is the ...
2
votes
2answers
154 views

Muxes, Adders, Comparators, and Gates

This question is actually from one of my previous discussions, which I still don't understand how to implement. The goal is to use abstraction to design a circuit, which converts two-digit ASCII ...
1
vote
2answers
154 views

Bit Slice Checker

I'm attempting to use bit-slice design, to implement a circuit which checks if an n-bit binary number A has an even number of 1's in its binary representation. I've decided that the circuit should ...
1
vote
2answers
280 views

Which 4-bit Binary Number Is Greater?

My Task I'm working on an extra work question our teacher assigned us from the book. Design a combinatorial circuit that compares two 4-bit unsigned numbers A and B to see whether B is greater than ...
0
votes
2answers
2k views

What would be the output of A = 0100 and B = 0111 with S = 1 in a 4-bit binary adder-subtractor?

I understand S = 1 means subtraction and S = 0 means addition. So then, the output would be the result of 0100 - 0111. But since it's negative, I'm not sure how it would be represented. I know the ...
1
vote
1answer
479 views

How to find gate delay for 4-bit look-ahead carry adder?

How can I find Gate Delay for bit 1 of the sum by a 4-bit look-ahead carry adder?
1
vote
1answer
4k views

Design a full adder of two 1-bit numbers using multiplexers 4/1

How can i implement the full adder of two 1-bit numbers using only multiplexers 4/1? I created a truth table for a one-bit full adder, which looks like this: A = first bit B = second bit Pu = bit ...
3
votes
6answers
301 views

Batteries in parallel vs voltage signals in parallel

From a practical point of view, when you connect two audio signals to one speaker the result is that both audio signals can be heard. That means the two voltage waves were added, correct? However, ...
-4
votes
2answers
117 views

Design of a basic half-adder

I know that a half-adder is a combination of the gates: XOR, AND. But how are they combined? And can you give a example and explain which one is the XOR and which one is the AND.
1
vote
1answer
2k views

Signed Addition of two std logic vectors while looking for overflow and carry

I have what I think to be a working implentation for finding the sum of two signed 32 bit (std_logic_vector) vectors in which I chose to expand the result to always have 33 bits so as to preserve the ...
0
votes
1answer
72 views

Adder-Subtractor Circuit

For the above question I got the answers: a. SUM = 0110 | C = 1001 b. SUM = 0100 | C = 1010 Are these answers correct and how is the overflow calculated?
0
votes
1answer
129 views

Truth Table, Full-adder

I'm trying to solve two questions that I am unsure how to approach. I know boolean means true/false but that's about it. The question reads: "A boolean equation in sum-of-products can be minimized ...
0
votes
1answer
76 views

Building a 2-bit adder with a propagation delay of at most 2 gates

An XOR-gate itself counts as 2 gates, so if I use an XOR-gate the delay would already be 2. I have no idea how to do this, as a full adder for one bit already contains 2 XOR-gates (or 1 XOR-gate, 1 ...
1
vote
1answer
233 views

How would you make a 3-bit binary adder that adds two instead of 1?

I am trying to make an asynchronous adder that holds three bits and adds two to the number. Can someone help? A Google search shows nothing and I'm having a hard time visualizing how to make the ...
0
votes
1answer
72 views

Help designing a serial adder [closed]

I need to build a circuit that adds two n-bit 2's complement numbers. the two numbers have to be stored in shift registers. The circuit should start with the least significant bits of each number and ...
-1
votes
1answer
147 views

Parallel MAC unit based on modified booth algorithm

The below diagram is the parallel MAC structure. In parallel MAC both partial product addition and accumulation take place at same time. The partial product summation + accumulation unit of above ...
0
votes
1answer
109 views

OLA adder and signed digit vhdl design problem

I have implemented the following online adder for signed digit using vhdl code and I have simulated my design according to the example table shown in the figure attached the problem is I am not ...
0
votes
2answers
2k views

2-bit adder implementation

How can I implement this 2-bit adder circuit: (source) Onto http://www.neuroproductions.be/logic-lab/ or logic.ly? After several attempts (and in spite of the half adder and full adder working) I ...