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2
votes
2answers
45 views

How do I build and use my own VHDL library?

I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a ...
2
votes
3answers
594 views

Aldec Active-HDL - No Default Binding

I'm getting some errors when I try to compile my design in Aldec's Active-HDL. ...
0
votes
1answer
67 views

List of files needed to rerun Aldec simulation?

There are bunch of files needed to run an Aldec simulation. What is the minimum set? Clearly this must include the Verilog/VHDL source, any testbenchs, and a project file. It also needs to include ...