I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a ...
I'm getting some errors when I try to compile my design in Aldec's Active-HDL. ...
There are bunch of files needed to run an Aldec simulation. What is the minimum set? Clearly this must include the Verilog/VHDL source, any testbenchs, and a project file. It also needs to include ...