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A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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1answer
56 views

Adjustable clock in HDL

I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag - there is no need to recompile the code). ...
1
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1answer
109 views

Is De0-Nano an alternative to Arduino/RaspberryPi?

Arduino and Raspberry Pi are touted as ideal programming boards for beginners and hobbyists. Could De0-Nano fit in that role, too? What does Arduino or RaspberryPi have that De0-Nano does not?
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48 views

OpenCL for Altera FPGAs

Recently I have been quite interested in OpenCL of the Khronos Group, and already gained some experiences with the language. I'm excited to know that OpenCL now works with Altera FPGA. ...
0
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1answer
22 views

What to change when migrating designs from Altera DE2 to DE2-115?

I'm migrating a working design from Altera DE2 to Altera DE2-115 and I'm running into problems. First everything works with DE2 just like mentioned in the exercises doing what is instructed. Now I ...
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2answers
82 views

Can we run Quartus II on Ubuntu?

I can compile digital components and download them to the boards DE2 and DE2-115 I got. I do it from Windows 7 but I want to enable this on ubuntu while the files from Altera are for Red Hat Linux. ...
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0answers
78 views

USB bare metal on ARM Cortex A9

We are envisioning developing a new project using a Cyclone V SoC with a hardcore ARM Cortex A9 dual core processor. We are seriously considering going bare metal, but one of the main questions right ...
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3answers
67 views

Simulating Altera FPGAs with an old version of ModelSim?

I'm hoping to do some development work on Altera FPGAs that will likely be larger than is supported by the free edition of ModelSim. I have an old copy of the full version hanging around (version ...
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2answers
75 views

FPGA Synthesis = 0 LE (Altera Quartus II)

Just starting with FPGAs and stuck with a synthesis issue. Basically, the circuit I am designing is coming out with 0 logic units and 0 for all resources except for the pins assignment. The code ...
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2answers
59 views

symbols for ep3c5e144 and ep3c25e144 in Eagle

I am using ep3c5e144 to design a PCB board. Sadly, in Eagle I cant find the exact library and symbol for this device, but only its near relative ep3c25e144. I have some questions: How different is ...
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2answers
67 views

create Eagle library for bsdl file

I am designing a PCB Board for Altera Cyclone III EP3C5E144. However, I cant find any library for this device in Eagle. Is there anyways I could create the library and symbol for this device, based ...
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1answer
104 views

CORDIC hardware accelerator for mathematical application [closed]

I have an application which has many mathematical operations. I want to ask what is better: To have an accelerator function (convert C code to VHDL)? To use CORDIC algorithmic? If I want to use ...
0
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2answers
167 views

PCB design for Altera FPGA

I want to design a brand new PCB board for Altera Cyclone III FPGA with 144 IO pins, such as ep3c25e144. However, I am clueless of how the process can be done in Eagle Cadsoft. Even when they ...
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1answer
97 views

Leaving target processor paused nios ii multiprocessor application

I m using the multiprocessor tutorial, to have a MPSOC application, but when i finish all steps and running the nios application I have this message in the terminal, ...
2
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3answers
102 views

View more than 100 worst-case paths in Quartus II

I am using Quartus II to compile Verilog for my FPGA project. For debug, I use SignalTap, which introduces a lot of timing warnings. When I go to the TimeQuest report, and look at the worst-case ...
1
vote
1answer
186 views

How can I avoid “Minimum Pulse Width” slack violations in Quartus FPGA synthesis?

I am synthesizing a toy application on DE2, but I hit a timing problem (despite every inputs and outputs are clocked in my design). These violations are related to "minimum pulse width"... How can I ...
3
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1answer
78 views

Set toggle rate in Quartus II

According to this document, I need to: assign 0 MHz toggle rate to Toggle Rate assignments for the pin in the Assignment Editor to place a non-differential pin ...
0
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1answer
50 views

SignalTap II: OR trigger conditions, instead of AND

I'm using the Altera SignalTap II that comes with Quartus II. As far as I understand, each pin can be assigned a trigger condition. It seems that acquisition only stops when all the trigger conditions ...
1
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1answer
101 views

Different Altera DE2 boards do not behave the same way

I have a simple VHDL file which can be simulated correctly and that synthesizes with Quartus II-11.0 (web edition). I can interact with switches,leds, seven segments and push buttons. My problem is ...
5
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1answer
161 views

Altera: Change JTAG clock speed

I am having issues with JTAG with my Cyclone IV, specifically the JTAG clock. I am trying to change the JTAG clock frequency somewhere, but can't find where this is done in Quartus II. How can I ...
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0answers
54 views

How to set system library properties in Nios II IDE v12?

I'm encountering a problem with NIOS 2 ide Version: 12. After making a project in IDE one could rightclick the folder and specify hardware specs like jtag connection, using on-chip memory etc. But in ...
1
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1answer
107 views

Starting FPGA project on Xilinx - trouble with some basics! Coming from Altera background

I'm just looking for a bit of help getting started with Xilinx FPGAs. Specifically, I'm looking for the analogue to Altera's HEX and ...
0
votes
1answer
119 views

Why is carry on for an adder that is simply on? [closed]

I've understood that the behaviour is correct when I make a simple adder: But why does carry on light up just because I switch on the + operation for my 4-bit system? ...
-1
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2answers
130 views

Need Quartis II CPLD tutorial for learning VHDL from ZERO [closed]

I am learning VHDL from zero using Altera CPLD. Already got Quartis II 12.1 and a 15-lines example VHDL (like Hello World for C learner). To avoid learning bad coding style or digging too deep too ...
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2answers
267 views

Learn CPLD from zero [closed]

a) Should I learn VHDL or Verilog? Is one excel in some area while the other better fit another area? For simple "glue logic", says, 5 to 30 TTL chips equivalant, which is better? b) First ...
1
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1answer
55 views

Avalon-ST interface properties of 10G MAC MegaFunction

I have an instance of the 10G MAC MegaFunction that contains an Avalon-ST interface. Reading through the Avalon-ST specification, I see that every Avalon-ST instance has "interface properties" (see ...
1
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1answer
187 views

Upgrading from Altera DE2 to DE2-115

I got a DE2 board that failed so they sent me a replacement board which is the finer DE2-115. But my config file (.sof) is not forward compatible. How can I migrate existing projects that I have for ...
2
votes
1answer
168 views

My design is not meeting timing. What can I do?

I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one. Now one isolated module in my design, which deals with ...
1
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2answers
147 views

Alternate programming software to program Altera CPLD

I am using a Altera MAX V CPLD. When I try to program the CPLD using QUARTUS II, it is reading the device ID and silicon ID correctly, but it failing during verification. I tried to isolate the ...
2
votes
2answers
85 views

Measuring Power from Altera Dev. Kit (CycloneIII)

The Altera CycloneIII starter kit that I have provides a jumper (J6) that is connected to VCCINT of the CycloneIII FPGA core for what seems to be the purpose of measuring the core's power consumption. ...
1
vote
2answers
164 views

Do I need to solder on my DE2 board to replace a broken segment?

I've already posted a question here about this when I realized that all things were not right with my Altera DE2 board: Is this display broken or is it a bug? After verifying that the segment indeed ...
1
vote
1answer
180 views

What is the I/O standard for the PCIe data lines?

I am entering the pin information of my FPGA design using the Altera Quartus II PinPlanner. One of the components of my design is PCIe, and I am having troubles understanding the "I/O standard" ...
2
votes
1answer
317 views

Quartus II ignoring synthesis attribute noprune

There is a register in my design that I am using for debug purposes with zero fan-out. Since it isn't driving any logic, the synthesizer optimizes it away. However, as far as my knowledge goes, ...
4
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2answers
160 views

Quartus II: Customise compiler messages

I am working with the Altera Quartus II compiler for my Cyclone IV. I am not happy with what is considered Info, Warning, ...
4
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1answer
277 views

Specify include path in Quartus II

I'm compiling Verilog using the Quartus II for the Altera platform. In my Verilog, I have a Verilog header global.vh, and Quartus II cannot find it: ...
6
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2answers
256 views

Specify exact pin locations on FPGA

I have an Altera Cyclone IV FPGA, and I use the Quartus II software as the compiler. In the "PinPlanner" it is possible to specify groups of pins (e.g. data buses). For each group, an I/O bank and an ...
3
votes
1answer
234 views

Does it always make sense to constrain an I/O port?

I am following an Altera online course on their timing analyzer software called TimeQuest. In it, their recommend that, at the very least, all clock and I/O ports be constrained. In my FPGA design, I ...
2
votes
1answer
193 views

Is this display broken or is it a bug?

After being fine for several days and picked up after transport, I found that one part of the Altera DE2 display is not working, you see where it is a 9 there should be an 8 so it is just like that ...
4
votes
3answers
1k views

What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24): To ...
4
votes
4answers
1k views

Using both edges of a clock

I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
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2answers
123 views

Cycle-Accurate Power Estimation for Altera Devices

I'll be doing some analysis which requires at least cycle-accurate power estimations. From what I gather, the PowerPlay tool only calculates total power consumption. I've also looked into Synplify, ...
2
votes
2answers
197 views

Merge a differential pair into one signal

I have an LVDS ADC connecting to an Altera Cyclone IV FPGA. The data pins come in 7 differential pair channels, for a total of 14 pins. Although each differential pair is physically 2 pins, my ...
4
votes
3answers
330 views

Altera optimisation: “Stuck at GND due to stuck port data_in”

I am compiling Verilog code with the Quartus II compiler, and it seems that almost all my code is being optimised away. The "compilation report" says that many of my registers are being removed during ...
2
votes
0answers
59 views

Why is my carry-in activated by operation1?

I made schematics for a 4-bit ALU which performed perfectly in simulation but when downloaded to the Altera DE2 board the operation1 switch also enables carry-in for the first of the four 1 bit ALUs. ...
3
votes
1answer
984 views

What's wrong with this 4-bit ALU?

I've put together a 4-bit ALU that seemed to perform correct in simulation but when downloaded to the board it is not behaving correctly. The operation OR behaves correctly while addition and AND are ...
0
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2answers
604 views

How to make Quartus II find the Altera DE2 board?

I use Quartus II web edition and using that driver my computer can find the card: And the card appears in the device manager so it indeed looks correct so far. But when I start Quartus ...
1
vote
1answer
127 views

Altera Cyclone IV memory block Verilog module

This document explains the various characteristics of the Altera Cyclone IV memory blocks (known as "M9K"). However, there is no mention as to how these modules should be instantiated in Verilog. ...
3
votes
1answer
212 views

Cyclone II FPGA Starter Kit Configuration Seems to be Giving Bogus Results

I've been trying to get my Cyclone II FPGA (from the Starter Kit, EP2C20) to work. I've gotten the Quartus II software to work on my Ubuntu setup and it' ALMOST working - I can write some Verilog, ...
4
votes
2answers
811 views

Why do I get a failure in Quartus while trying to programming my FPGA?

I followed with this tutorial into the end of it, but I got an error while trying to programming my DE2 altera kit. the design is input pin output pin (pin_name1 ...
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0answers
175 views

Any good tutorials for Altera DE2 with cyclone II? [closed]

Is there any good tutorials for verilog and the university board of altera DE2, I found this list, but are they any good video tutorials? or printed as well?
3
votes
1answer
48 views

Does FLEX10k support SignalTap? [closed]

Can I make an embedded logic analyzer for FLEX (flex10k) devices using SignalTap by JTAG?

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