A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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How would you implement a System like this easily using Altera Tools and the DE1-SOC

I want to implement a system as follows: Four cores (Processing Elements) to read a black and white image of 240x240 pixels = 57.600 pixels in total (each pixel with a intensity integer value of 0 to ...
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26 views

Timing Requirements - Worst case Removal Slack

I have a critical warning for Worstcase Negative removal slack of -2.461. From node: - altera_reserved_tck To node: pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967 I am not sure if I ...
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2answers
24 views

How to make an .sof upload to an Altera Max10 stick

I have a Max10 dev board with a 10m08 chip on it. I made a simple counter to blink the LED's. My counters have asynchronous resets, and my asynchronous reset has a circuit to keep it low for two clock ...
5
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1answer
72 views

Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are ...
0
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1answer
28 views

Cyclone V LVTTL GPIO Termination

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO. The cyclone V datasheet show that no external termination is required as shown ...
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2answers
72 views

How can I set a delay in Verilog using a clock?

I'm trying to write an always block that will open a valve and then keep it open for a few seconds and then close it if needed. The valve opens when the input is 1 and it closes when it's zero. How ...
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1answer
55 views

how to set pin in verilog (atera)

I am beginner in Altera DE2-115. I am asked to make a project using Verilog language. My idea was connect an infrared sensor and if it is cut with something, a buzzer starts. The infra has 3 ...
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2answers
86 views

verilog error left-hand side of assignment must have a variable data type

I have a verilog as module I get the error Error (10137): Verilog HDL Procedural Assignment error object "result" on ...
0
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1answer
81 views

Active serial configuration flash (EPCS & EPCQ) vs normal SPI flash

Is there a difference between the serial configuration devices from Altera and any other SPI flash memories? I see Terasic uses S25FL256S in their development board instead of EPCQ256, so I wondered ...
0
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1answer
141 views

Loading and displaying on VGA monitor a Background image in DE2-115's SDRAM

I would like to load a background image which I currently have saved as a .bmp into the DE2-115's SDRAM. I would then like to display this background image on a VGA-monitor (640x480). I will then be ...
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1answer
133 views

How can I generate a 1 Hz clock from 50 MHz clock coming from an Altera board? [duplicate]

I have an Altera DE2 board that outputs a 50 MHz clock and I'm trying to write a verilog module that can bring it down to 1 Hz. How can I do this?
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54 views

NIOS II Flash Programmer

I am trying to program and configure the HW (time_limited.sof file) using the Quartus II Programmer (v11.1) and to generate and flash the SW (.ELF) using the Flash Programmer. Unfortunately I am ...
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48 views

Altera “fiftyfivenm” and “twentynm” - What is that?

I know many Altera products from Arria, Cyclon, Stratix and co, but what are the: fiftyfivenm twentynm devices? I assume these are devices, because there are ...
0
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0answers
35 views

Is it possible to use external pull ups with altera cplds

If one is using an Altera CPLD that has lower output voltage than the LED forward voltage that it is to drive, one simple solution would be to use an external pull up to drive the LED. The CPLD is ...
0
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3answers
158 views

Implementing an ADC Interface to connect to a FPGA

I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to implement it in VHDL. I already have an ADC Interface for a 10 bit ADC (MAX 1030) and a ...
2
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1answer
46 views

Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and ...
2
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1answer
122 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
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1answer
55 views

Altera FPGA Pinout help

I recently bought an Altera FPGA Cyclone II board off of ebay, it says BAIXUN on the LCD display. It didnt come with any documentation. I'm trying to program the FPGA board but I have no idea what pin ...
0
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1answer
173 views

hexadecimal seven segment display verilog

I have a 4 bit output number as output. How can it be seen on seven segment display as hexadecimal number? I'm new and mentioning verilog. case example: ...
0
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2answers
77 views

usb interface for fpga & Nios

I need some advice: i want to connect an altera FPGA to a computer by USB interface. i want to avoid placing an microcontroller in my board.. i want to set a nios II to "talk" to the computer i only ...
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51 views

SystemVerilog interface blocks and Altera Quartus Design Partitions

It appears that Quartus (including the latest v15.0) does not look at modports when determining the direction of the ports in SystemVerilog interface blocks. The fitter complaints that the design ...
0
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1answer
136 views

Help with resolving warning “inferring latch(es) for signal or variable ”..“, which holds its previous value in one or more paths through the process”

Below is the code for my branch unit implementation. This unit calculates the jump destination address and writes it into the PC register. There are a few different types of jumps, etc, standard ...
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1answer
162 views

Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?

Xilinx offers an Integrated Logic Analyzer (ILA) / called ChipScope. Altera's Quartus II comes with SignalTap - an equivalent solution. As an advance user\$^1\$, I'm using ChipScope as pre-compiled ...
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44 views

Altera Megafunction generics

I am using the Altera Megafunction LPM_ROM in one of my designs using the block diagram editor in Quartus. I want the ROM to have a configurable initialization file. For example for my component X ...
0
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1answer
140 views

Quartus II - Can I include other files into a *.qsf file?

An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...). Is is possible ...
3
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1answer
203 views

CDC Synchonisation primitives for an Altera FPGA

I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC). There are multiple resources (amongst others) which discuss various architectures for CDC and ...
0
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1answer
41 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
2
votes
1answer
89 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
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2answers
63 views

How are FPGA's configured when operating independently?

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
0
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1answer
70 views

Does the altera ROM megafunction have a startup delay?

I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...
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1answer
86 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
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2answers
513 views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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2answers
418 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
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1answer
152 views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
0
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0answers
62 views

Resistance or impedance offered by GPIO pins and SMA external clock pin in cyclone 2

I tried connecting a square wave from a signal generator as an external clock through the SMA pin. But I need to know the impedance offered by the SMA pin. What is it and how o find it? Besides the ...
0
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3answers
397 views

sine wave in FPGA

I am supposed to generate a sine wave in cyclone 2 altera? I get that I have to store the values in LUT or some memory. I think cyclone 2 uses a 4 input LUT. I am not sure how I should go on with the ...
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3answers
229 views

PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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1answer
115 views

Altera Clock + PLL

I am using an Altera devkit from terasic, DE0-CV. I am also new to the FPGA business. How to connect the onboard clock to the FPGA and use it with my design? As the clock is a 50 MHz one, surely I ...
4
votes
1answer
242 views

Altera's DRAM Controller with UniPHY

I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem). I have managed to generate the IP, but I don't understand which ...
2
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1answer
129 views

Using the ROM megafunction in VHDL code

I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd. My code: ...
0
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1answer
25 views

Node assigned to IOBANK

I'm working with an Altera FPGA. In the Pin Planner there is a choice in the combo box for a 1-bit inout node to be connected to an "IOBANK_n" (under "Location" row). I was expecting only "PIN_nn" are ...
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3answers
827 views

How to define a clock in Quartus II?

I have this piece of code here: ...
0
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2answers
293 views

FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
2
votes
1answer
213 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
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2answers
411 views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
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1answer
80 views

Why build errors when connecting timers in Quartus ii?

I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g. ...
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1answer
307 views

Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output

I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim. All the instantiated IP ...
0
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1answer
211 views

Can DE2-115 handle more than 3.3V on its GPIO

In my current project I want to connect some logic to Altera DE2-115 using 40-pin exapnsion header (JP5). Unfortunately, I can't ...
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1answer
2k views

How to install Altera USB master driver for Windows 8 (64 bit)?

I am trying to connect Altera Stratix 4 board with my PC in which Quartus 11.0 is per-installed. But my PC is not detecting USB JTAG connection from the board. What I am guessing is that, this ...
0
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2answers
282 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...