A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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25 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
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57 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
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2answers
45 views

How are FPGA's configured when operating independently?

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
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1answer
40 views

Does the altera ROM megafunction have a startup delay?

I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...
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55 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
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105 views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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48 views

OR1K on DE0-Nano

I seem to be having difficulty finding much information on implementing the OpenRisc architecture onto the DE0-nano with support for linux. I found one particular article on the official site from an ...
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21 views

How to compile .qsys file in modelsim?

My project contains both .qsys and .vhd files. I want to simulate my project using modelsim before programing to FPGA. For ModelSim to simulate first all files should be compiled. From what I know ...
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65 views

Having FPGA to output sound on “line out” pin using verilog

I am trying to write a verilog code for FPGA which will output sound from the embedded "line out" pin. I use Quartus II and Altera DE1. I am new to hardware programming, therefore it just takes too ...
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79 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
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50 views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
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37 views

Resistance or impedance offered by GPIO pins and SMA external clock pin in cyclone 2

I tried connecting a square wave from a signal generator as an external clock through the SMA pin. But I need to know the impedance offered by the SMA pin. What is it and how o find it? Besides the ...
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3answers
142 views

sine wave in FPGA

I am supposed to generate a sine wave in cyclone 2 altera? I get that I have to store the values in LUT or some memory. I think cyclone 2 uses a 4 input LUT. I am not sure how I should go on with the ...
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3answers
125 views

PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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67 views

How the change the frequency of a clock in Quartus II?

I have a clock in VHDL: ... process(clock) begin if rising_edge(clock) then ... When I check the timequest analyzer, it sets this clock to a default 1 GHz ...
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1answer
51 views

Altera Clock + PLL

I am using an Altera devkit from terasic, DE0-CV. I am also new to the FPGA business. How to connect the onboard clock to the FPGA and use it with my design? As the clock is a 50 MHz one, surely I ...
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29 views

Altera's DRAM Controller with UniPHY

I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem). I have managed to generate the IP, but I don't understand which ...
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1answer
55 views

Using the ROM megafunction in VHDL code

I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd. My code: ...
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1answer
23 views

Node assigned to IOBANK

I'm working with an Altera FPGA. In the Pin Planner there is a choice in the combo box for a 1-bit inout node to be connected to an "IOBANK_n" (under "Location" row). I was expecting only "PIN_nn" are ...
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126 views

How to define a clock in Quartus II?

I have this piece of code here: ...
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2answers
101 views

FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
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1answer
108 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
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76 views

How to output audio using an altera DE0 FPGA?

I am working on a project that involves realtime image processing using altera DE0 fpga board. Due to the nature of the project I am also really interested in including audio output. However according ...
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189 views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
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40 views

Is source code compatible between DE2 and DE2-115?

I have 2 FPGAs: Altera DE2 and DE2-115. I was reading that source code is compatible between different computers and different cores. I have written a C program for use with the Micrium ucos rtos with ...
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43 views

Why build errors when connecting timers in Quartus ii?

I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g. ...
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1answer
124 views

Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output

I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim. All the instantiated IP ...
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1answer
102 views

Can DE2-115 handle more than 3.3V on its GPIO

In my current project I want to connect some logic to Altera DE2-115 using 40-pin exapnsion header (JP5). Unfortunately, I can't ...
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1answer
616 views

How to install Altera USB master driver for Windows 8 (64 bit)?

I am trying to connect Altera Stratix 4 board with my PC in which Quartus 11.0 is per-installed. But my PC is not detecting USB JTAG connection from the board. What I am guessing is that, this ...
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1answer
128 views

Interfacing DDS with FPGA

I'm trying to use an FPGA (Altera Deo-Nano) to send data to a DDS (AD9910) using the parallel ports of the DDS. I am using the GPIO headers of the FPGA. I have only connected the parallel input pins ...
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2answers
98 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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1answer
70 views

reuse Cyclone IV fpga Pasive serial configuration pin for SPI

Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ? This are the dual purpose pin options: if i set "use as Regular I/O" , i ...
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1answer
121 views

Is it technically feasible to design a microchip that won't fail foreign characters? [closed]

I used to work as web developer and did the same part of the project for several decades: Making sure that our Scandinavian characters åäöÅÄÖ... will work. It was feasible and it did work, basically ...
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1answer
30 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...
2
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1answer
146 views

How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector. If it is on, show Y = SW[15:8], if it is off, ...
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1answer
98 views

Extracting a sub array from an array of switches with Verilog?

I am working with a Cyclone board. A basic code to assign every switch to the red leds is: ...
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2answers
320 views

Altera DE1-SoC Diagram

In this link is a description of the Altera DE1-SoC kit, and the bottom of the page shows the diagram of the SoC-FPGA chip. It shows some peripherals are connected to the FPGA and other are connected ...
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1answer
64 views

ALU once compiled giving errors of missing source signal?

This is ALU, not sure whether if it is all properly connected but all blocks are the correct ones. This has 3 4 bit latch registers, 5 2:1 ultiplexers, 4 4 bit adders. Can anyone help me? The problems ...
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1answer
83 views

Using a Counter to Determine next MSB position in polynomial division

I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right When ...
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35 views

Video system processing using FPGA. Options [duplicate]

I have to design a PCB where a FPGA, ASIC or SOC will be used and the system has to be able to record the video from a camera and display the live video in a display HD. The camera has a resolution ...
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2answers
142 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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2answers
788 views

Verilog FIR filter using FPGA

I am implementing an FIR filter in Verilog, using the DE2 board. For some reason the output out of the speakers is full of static, although it does appear to filter out some frequencies. Here is the ...
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4answers
424 views

Altera DE2 interfacing with analog sensor

Can Altera GPIO pins read the analog output of a light sensor? The light sensor output is analog and I want the Altera to turn an LED on whenever the signal of the sensor is greater than some specific ...
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229 views

Can Altera GPIO pins read the input voltage?

I have ALtera DE2-115, and I have a light sensor module, the output of the light sensor is a voltage, how can I use the Altera GPIO pins to read the coming voltage? Thanks
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1answer
47 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
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98 views

PING Ultrasonic sensor output

I'm new to the world of Digital Systems :D I want to know whether the output of the Ultrasonic range finder sensor is analog or digital, so I can connect it to Altera DE2 GPIO directly or I need an ...
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85 views

Altera DE2 compatible sensors

I'm a beginner in the world of digital systems, I want to connect an ultrasonic range finder sensor to my Altera DE2 Board, and this sensor is Arduino and pic microcontroller compatible , can I ...
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1answer
435 views

Solid color display on VGA not working

I'm trying to get VGA working on my Altera DE0 board using Verilog, but haven't had much luck. It has the same pins as a normal VGA interface except red, green, and blue are all 4 bits each. Here is ...
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1answer
68 views

Modeling FPGA logic element responses

I'm working on modeling a circuit implemented on an FPGA, and the fundamental question I keep running into is this: what is a logic element? I need to be able to model the temporal response of the ...
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2answers
135 views

Quartus FPGA migration issues

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used). I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA ...