A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

learn more… | top users | synonyms

0
votes
2answers
23 views

Altera Cyclone IV FPGA and jtag debugging

G'day All, Is there a method comparable to jtag debugging on a microcontroller (ATMEGA32) for the Cyclone IV family of FPGA? I am trying to debug my Verilog code so ideally I just want to be able to ...
0
votes
1answer
26 views

Altera Quartus. Technology Map Viewer looks different from expected

Recently, I've installed Altera Quartus 15.1 and now follow the "getting started" instructions, you can read it here. At the step: to see the resulting circuit go to Tools →Netlist Viewers →Technology ...
0
votes
0answers
23 views

How to assign pins of Altera Cyclone II to 7 segment?

I am quite new to FPGA and I want to design a 1-digit counter on a 7-segment on an Altera development board. What I have done so far was to schematically design a bcd to 7-segment decoder in Quartus ...
1
vote
1answer
45 views

What is configuration image zero and one?

Currently, I am working in Broadwell-DE based module design. In this circuit, There is an FPGA (p/n :10M02SCU169C8G ) Please see the configuration user guide added. ( ref page 14) ...
0
votes
0answers
17 views

Using TCL (or other Script) file in Quartus to automate circuit creation

I have various simple modules (Verilog) written and included in my Quartus project file. Lets say each such module receives a 8 bit input, increments the value and outputs the new value. Depending ...
0
votes
0answers
18 views

Flashing NIOS II with SPI at boot

I have a Altera FPGA, which is configured (programmed/flashed) at startup by SPI from a processor runing embedded linux. If I put a NIOS processor in the fpga, is it possible to flash the NIOS ...
0
votes
2answers
75 views

What the FPGA dev board to choose: Xilinx or Altera? [closed]

I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
0
votes
0answers
16 views

Creating a terminal windows on PC to control Nios-II in FPGA to send commands to SPI slave

To ease testing of slave devices e.g memory devices, ADCs e.t.c is it possible to create an application where one has a terminal window open on PC from which one can write specific 8 or 16 bit words ...
1
vote
1answer
26 views

Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
0
votes
0answers
58 views

Memory Interface with a Multiplexed Address/Data Bus

I want to implement a memory interface in VHDL between an FPGA and a processor. The address/data bus is a 16-bit multiplexed bus with an ALE, write protect and BusWait. According to the NVIDIA Tegra 3 ...
0
votes
2answers
69 views

Simple LED FPGA Circuit

I am new to digital design, and have recently purchased a Bemicro MAX10 FPGA development board to help get my feet wet. I am trying to learn VHDL, and have downloaded a few PDFs to get me started. The ...
0
votes
0answers
18 views

How to view Nios 2 assembly code?

I use the Altera DE2 FPGA that can run my C program. If I want to view the generated assembly, how can I do it? It's usually some flag for gcc and I use Nios 2 IDE ...
6
votes
2answers
212 views

Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...
-1
votes
1answer
59 views

Clock port and any other port of a register should not be driven by the same signal source

I get this Warning from Altera Design Assistant for the below: Clock port and any other port of a register should not be driven by the same signal source Critical Warning (308012): Node ...
0
votes
1answer
46 views

Altera Quartus Design Assistant Critical Warnings

I get a number of Critical Warnings with respect to lpm_ff and lpm_counter: Below are few: Rule A102: Register output should not drive its own control signal directly or through combinational ...
4
votes
2answers
117 views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...
0
votes
2answers
77 views

Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...
1
vote
1answer
83 views

Illegal bus range or name for logic function for instance “instMyAdder” of type 4 Bit Adder

I am using QuartusII for designing a Four bit ripple carry adder. I keep getting this error: ...
1
vote
1answer
60 views

Design of carry chain on Cyclone IV

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "cin" goes high, signal starts to ...
0
votes
0answers
25 views

SDC Command for set_clock_latency for a specific clock target

Could anybody please share the SDC Command for setting clock latency for a "specific target clock". I am unable to find the correct SDC Command. -6.109(Setup Slack) ; ...
3
votes
1answer
226 views

Use ancient Altera MAX II board in modern environment

Years ago (in 2004) my university got an Altera MAX-II devboard, but nobody used it. Now it's me who must teach students FPGA programming, but I still cannot get the board programmed. I faced the ...
1
vote
1answer
87 views

Verilog SPI module functioning in unpredicted ways

I am currently trying to implement a simple SPI Master module in Verilog using Quartus Prime Lite V15.1.0 Build 185 for compilation and Simulation Waveform Editor as my simulation tool. The module has ...
-1
votes
2answers
119 views

How to make an .sof upload to an Altera Max10 stick [duplicate]

I have a Max10 dev board with a 10m08 chip on it. I made a simple counter to blink the LED's. My counters have asynchronous resets, and my asynchronous reset has a circuit to keep it low for two clock ...
5
votes
1answer
166 views

Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are ...
0
votes
1answer
44 views

Cyclone V LVTTL GPIO Termination

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO. The cyclone V datasheet show that no external termination is required as shown ...
0
votes
2answers
210 views

How can I set a delay in Verilog using a clock?

I'm trying to write an always block that will open a valve and then keep it open for a few seconds and then close it if needed. The valve opens when the input is 1 and it closes when it's zero. How ...
-2
votes
1answer
103 views

how to set pin in verilog (atera)

I am beginner in Altera DE2-115. I am asked to make a project using Verilog language. My idea was connect an infrared sensor and if it is cut with something, a buzzer starts. The infra has 3 ...
-1
votes
2answers
331 views

verilog error left-hand side of assignment must have a variable data type

I have a verilog as module I get the error Error (10137): Verilog HDL Procedural Assignment error object "result" on ...
0
votes
1answer
169 views

Active serial configuration flash (EPCS & EPCQ) vs normal SPI flash

Is there a difference between the serial configuration devices from Altera and any other SPI flash memories? I see Terasic uses S25FL256S in their development board instead of EPCQ256, so I wondered ...
0
votes
1answer
412 views

Loading and displaying on VGA monitor a Background image in DE2-115's SDRAM

I would like to load a background image which I currently have saved as a .bmp into the DE2-115's SDRAM. I would then like to display this background image on a VGA-monitor (640x480). I will then be ...
-4
votes
1answer
327 views

How can I generate a 1 Hz clock from 50 MHz clock coming from an Altera board? [duplicate]

I have an Altera DE2 board that outputs a 50 MHz clock and I'm trying to write a verilog module that can bring it down to 1 Hz. How can I do this?
0
votes
0answers
84 views

NIOS II Flash Programmer

I am trying to program and configure the HW (time_limited.sof file) using the Quartus II Programmer (v11.1) and to generate and flash the SW (.ELF) using the Flash Programmer. Unfortunately I am ...
0
votes
3answers
210 views

Implementing an ADC Interface to connect to a FPGA

I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to implement it in VHDL. I already have an ADC Interface for a 10 bit ADC (MAX 1030) and a ...
2
votes
1answer
66 views

Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and ...
2
votes
1answer
131 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
-2
votes
1answer
69 views

Altera FPGA Pinout help [closed]

I recently bought an Altera FPGA Cyclone II board off of ebay, it says BAIXUN on the LCD display. It didnt come with any documentation. I'm trying to program the FPGA board but I have no idea what pin ...
0
votes
1answer
344 views

hexadecimal seven segment display verilog

I have a 4 bit output number as output. How can it be seen on seven segment display as hexadecimal number? I'm new and mentioning verilog. case example: ...
0
votes
2answers
101 views

usb interface for fpga & Nios

I need some advice: i want to connect an altera FPGA to a computer by USB interface. i want to avoid placing an microcontroller in my board.. i want to set a nios II to "talk" to the computer i only ...
0
votes
0answers
75 views

SystemVerilog interface blocks and Altera Quartus Design Partitions

It appears that Quartus (including the latest v15.0) does not look at modports when determining the direction of the ports in SystemVerilog interface blocks. The fitter complaints that the design ...
0
votes
1answer
209 views

Help with resolving warning “inferring latch(es) for signal or variable ”..“, which holds its previous value in one or more paths through the process”

Below is the code for my branch unit implementation. This unit calculates the jump destination address and writes it into the PC register. There are a few different types of jumps, etc, standard ...
1
vote
1answer
233 views

Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?

Xilinx offers an Integrated Logic Analyzer (ILA) / called ChipScope. Altera's Quartus II comes with SignalTap - an equivalent solution. As an advance user\$^1\$, I'm using ChipScope as pre-compiled ...
0
votes
0answers
55 views

Altera Megafunction generics

I am using the Altera Megafunction LPM_ROM in one of my designs using the block diagram editor in Quartus. I want the ROM to have a configurable initialization file. For example for my component X ...
0
votes
1answer
223 views

Quartus II - Can I include other files into a *.qsf file?

An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...). Is is possible ...
3
votes
1answer
300 views

CDC Synchonisation primitives for an Altera FPGA

I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC). There are multiple resources (amongst others) which discuss various architectures for CDC and ...
0
votes
1answer
57 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
2
votes
1answer
98 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
1
vote
2answers
82 views

How are FPGA's configured when operating independently?

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
0
votes
1answer
84 views

Does the altera ROM megafunction have a startup delay?

I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...
0
votes
1answer
116 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
0
votes
2answers
899 views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...