A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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Altera Quartus not creating symbol files

I'm looking to create a schematic block from a vhdl file in Altera'a Quartus software. I've been using File->Create/Update->Create Symbol Files for Current file The file compiles okay and I get the ...
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20 views

Help in Alterra DE0-Nano Clock

I am having trouble using the On-board 50MHz Clock of my DE0-Nano. I have this code: ...
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30 views

Effective Capacitance of an FPGA board

I am currently designing a processor on an Altera DE0 Nano and found out that the power consumption of my design may be computed by this equation: P = C * V^2 * (a * f) where P is the power ...
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39 views

Altera FPGA Configuration using Flash

During my current PCB design using Altera FPGA, I happened to come across knowledge that Altera EPCS devices are to be used for FPGA configuration. After further research, I realized the same job can ...
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3answers
113 views

Why does Altera DE2-115 board GPIO expansion header contain 5V & 3.3V power but the IO standard has no 5V?

The altera DE2-115 board user manual section 4.8 page 47 describes the GPIO expansion header. It is clear that it has 3.3V and 5V power supply. However, it later says that "The voltage level of the I/...
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33 views

CPLD: How to buffer data with short delay?

I have the following case: I have 2 logic(1/0) input signals (parallel and at 5MHz) into the CPLD. I want to capture the 2 paralell input signals at the same time and convert them into a serial output ...
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11 views

Altera DE2 - LCD (CFAH1602B-TMC-JP) Initialization Sequence

I have a Terrasic DE2 and am trying to initialize the LCD and then turn on the backlight for confirmation. I've modeled the sequence all the way up to the final point described in the datasheet (link ...
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90 views

Make DE0 Nano board to be Bootable and use SDRAM to store hardware and software

I have been stuck with this problem for MONTHS, please help me. I am currently working on a Nios II based design using the DE0-Nano board and the on board 32Mb sdram. My system is as follows: ...
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51 views

Nios II system generated by Qsys looks awful (All pin are at one side). Can we make it look better?

I have tried Quartus 16.0 and 14.1. Both of them generate Nios II system that looks very awful as shown in the figure below. Is there any way to make it look better like the previous version as ...
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58 views

Quartus partial compile or recompile

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. ...
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35 views

Simulating RAM in modelsim - cannot find library

I have a design in Quartus that includes an (on chip) RAM module that was created using the altera mega wizard. The wizard warns me that to simulate i need to include the ...
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34 views

Best utillization of M9K memory in max10

I've got a max10 with a nios processor built in my memory utillization on the part is: 414,198 / 562,176 ( 74 % ) but I've used up every M9K block on the FPGA. Here is a table for the utillization ...
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36 views

Altera Cyclone II JTAG after AS Programming

I've been playing with FPGA(Cyclone II EP2C5T144C8) with Quartus II 13.0 WebEdition 64bit and Altera USB Blaster. At first, I was using JTAG mode for programming FPGA into RAM. When I wanted to ...
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1answer
30 views

Bus to wire in quartus

I sometimes run into a problem with altera's Quartus that I would like a better solution to. Sometimes I use the graphical interface for design and I have a bus that I would like to pull off just one ...
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31 views

Altera Quartus - structural architecture

I am relatively new to VHDL and I am supposed to use structural architecture and Altera Quartus on my assignments. But, I have noticed that the Unisim library is not compatible with Altera Quartus, so ...
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40 views

Altera Cyclone IV FPGA and jtag debugging

G'day All, Is there a method comparable to jtag debugging on a microcontroller (ATMEGA32) for the Cyclone IV family of FPGA? I am trying to debug my Verilog code so ideally I just want to be able to ...
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33 views

Altera Quartus. Technology Map Viewer looks different from expected

Recently, I've installed Altera Quartus 15.1 and now follow the "getting started" instructions, you can read it here. At the step: to see the resulting circuit go to Tools →Netlist Viewers →Technology ...
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34 views

How to assign pins of Altera Cyclone II to 7 segment?

I am quite new to FPGA and I want to design a 1-digit counter on a 7-segment on an Altera development board. What I have done so far was to schematically design a bcd to 7-segment decoder in Quartus ...
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49 views

What is configuration image zero and one?

Currently, I am working in Broadwell-DE based module design. In this circuit, There is an FPGA (p/n :10M02SCU169C8G ) Please see the configuration user guide added. ( ref page 14) https://www.altera....
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28 views

Using TCL (or other Script) file in Quartus to automate circuit creation

I have various simple modules (Verilog) written and included in my Quartus project file. Lets say each such module receives a 8 bit input, increments the value and outputs the new value. Depending ...
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29 views

Flashing NIOS II with SPI at boot

I have a Altera FPGA, which is configured (programmed/flashed) at startup by SPI from a processor runing embedded linux. If I put a NIOS processor in the fpga, is it possible to flash the NIOS ...
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124 views

What the FPGA dev board to choose: Xilinx or Altera? [closed]

I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
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30 views

Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
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79 views

Memory Interface with a Multiplexed Address/Data Bus

I want to implement a memory interface in VHDL between an FPGA and a processor. The address/data bus is a 16-bit multiplexed bus with an ALE, write protect and BusWait. According to the NVIDIA Tegra 3 ...
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77 views

Simple LED FPGA Circuit

I am new to digital design, and have recently purchased a Bemicro MAX10 FPGA development board to help get my feet wet. I am trying to learn VHDL, and have downloaded a few PDFs to get me started. The ...
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291 views

Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...
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60 views

Clock port and any other port of a register should not be driven by the same signal source

I get this Warning from Altera Design Assistant for the below: Clock port and any other port of a register should not be driven by the same signal source Critical Warning (308012): Node "App_Logic:...
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50 views

Altera Quartus Design Assistant Critical Warnings

I get a number of Critical Warnings with respect to lpm_ff and lpm_counter: Below are few: Rule A102: Register output should not drive its own control signal directly or through combinational ...
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2answers
181 views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...
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89 views

Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...
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116 views

Illegal bus range or name for logic function for instance “instMyAdder” of type 4 Bit Adder

I am using QuartusII for designing a Four bit ripple carry adder. I keep getting this error: ...
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71 views

Design of carry chain on Cyclone IV

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "cin" goes high, signal starts to ...
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235 views

Use ancient Altera MAX II board in modern environment

Years ago (in 2004) my university got an Altera MAX-II devboard, but nobody used it. Now it's me who must teach students FPGA programming, but I still cannot get the board programmed. I faced the ...
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120 views

Verilog SPI module functioning in unpredicted ways

I am currently trying to implement a simple SPI Master module in Verilog using Quartus Prime Lite V15.1.0 Build 185 for compilation and Simulation Waveform Editor as my simulation tool. The module has ...
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2answers
180 views

How to make an .sof upload to an Altera Max10 stick [duplicate]

I have a Max10 dev board with a 10m08 chip on it. I made a simple counter to blink the LED's. My counters have asynchronous resets, and my asynchronous reset has a circuit to keep it low for two clock ...
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236 views

Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are ...
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58 views

Cyclone V LVTTL GPIO Termination

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO. The cyclone V datasheet show that no external termination is required as shown ...
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297 views

How can I set a delay in Verilog using a clock?

I'm trying to write an always block that will open a valve and then keep it open for a few seconds and then close it if needed. The valve opens when the input is 1 and it closes when it's zero. How ...
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1answer
128 views

how to set pin in verilog (atera)

I am beginner in Altera DE2-115. I am asked to make a project using Verilog language. My idea was connect an infrared sensor and if it is cut with something, a buzzer starts. The infra has 3 ...
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2answers
446 views

verilog error left-hand side of assignment must have a variable data type

I have a verilog as module I get the error Error (10137): Verilog HDL Procedural Assignment error object "result" on ...
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1answer
226 views

Active serial configuration flash (EPCS & EPCQ) vs normal SPI flash

Is there a difference between the serial configuration devices from Altera and any other SPI flash memories? I see Terasic uses S25FL256S in their development board instead of EPCQ256, so I wondered ...
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530 views

Loading and displaying on VGA monitor a Background image in DE2-115's SDRAM

I would like to load a background image which I currently have saved as a .bmp into the DE2-115's SDRAM. I would then like to display this background image on a VGA-monitor (640x480). I will then be ...
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1answer
432 views

How can I generate a 1 Hz clock from 50 MHz clock coming from an Altera board? [duplicate]

I have an Altera DE2 board that outputs a 50 MHz clock and I'm trying to write a verilog module that can bring it down to 1 Hz. How can I do this?
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3answers
270 views

Implementing an ADC Interface to connect to a FPGA

I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to implement it in VHDL. I already have an ADC Interface for a 10 bit ADC (MAX 1030) and a ...
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1answer
85 views

Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and ...
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1answer
141 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
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1answer
72 views

Altera FPGA Pinout help [closed]

I recently bought an Altera FPGA Cyclone II board off of ebay, it says BAIXUN on the LCD display. It didnt come with any documentation. I'm trying to program the FPGA board but I have no idea what pin ...
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369 views

hexadecimal seven segment display verilog

I have a 4 bit output number as output. How can it be seen on seven segment display as hexadecimal number? I'm new and mentioning verilog. case example: ...
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2answers
127 views

usb interface for fpga & Nios

I need some advice: i want to connect an altera FPGA to a computer by USB interface. i want to avoid placing an microcontroller in my board.. i want to set a nios II to "talk" to the computer i only ...
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1answer
263 views

Help with resolving warning “inferring latch(es) for signal or variable ”..“, which holds its previous value in one or more paths through the process”

Below is the code for my branch unit implementation. This unit calculates the jump destination address and writes it into the PC register. There are a few different types of jumps, etc, standard ...