A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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Using a Counter to Determine next MSB position in polynomial division

I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right When ...
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30 views

Video system processing using FPGA. Options [duplicate]

I have to design a PCB where a FPGA, ASIC or SOC will be used and the system has to be able to record the video from a camera and display the live video in a display HD. The camera has a resolution ...
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2answers
75 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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1answer
85 views

Verilog FIR filter using FPGA

I am implementing an FIR filter in Verilog, using the DE2 board. For some reason the output out of the speakers is full of static, although it does appear to filter out some frequencies. Here is the ...
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4answers
76 views

Altera DE2 interfacing with analog sensor

Can Altera GPIO pins read the analog output of a light sensor? The light sensor output is analog and I want the Altera to turn an LED on whenever the signal of the sensor is greater than some specific ...
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80 views

Can Altera GPIO pins read the input voltage?

I have ALtera DE2-115, and I have a light sensor module, the output of the light sensor is a voltage, how can I use the Altera GPIO pins to read the coming voltage? Thanks
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29 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
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56 views

PING Ultrasonic sensor output

I'm new to the world of Digital Systems :D I want to know whether the output of the Ultrasonic range finder sensor is analog or digital, so I can connect it to Altera DE2 GPIO directly or I need an ...
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44 views

Altera DE2 compatible sensors

I'm a beginner in the world of digital systems, I want to connect an ultrasonic range finder sensor to my Altera DE2 Board, and this sensor is Arduino and pic microcontroller compatible , can I ...
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126 views

Solid color display on VGA not working

I'm trying to get VGA working on my Altera DE0 board using Verilog, but haven't had much luck. It has the same pins as a normal VGA interface except red, green, and blue are all 4 bits each. Here is ...
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61 views

Modeling FPGA logic element responses

I'm working on modeling a circuit implemented on an FPGA, and the fundamental question I keep running into is this: what is a logic element? I need to be able to model the temporal response of the ...
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62 views

Quartus FPGA migration issues

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used). I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA ...
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41 views

Trouble getting push button working in Nios II

To give you an idea of what I'm trying to accomplish, the 18 LEDs on the board are to scroll right to left, then back to the right, and keep looping as such. Where the push button comes into play is ...
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229 views

50 MHz FPGA (Cyclone IV @ DE0-Nano) and 60 MHz input from FT2232H

I want to read data from FT2232H used in an FT245 style synchronous FIFO mode (http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf p.27) with DE0-Nano FPGA board: ...
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47 views

How to get OpenCL kernel simulation performance by Altera OpenCL SDK or Quartus II?

I am using OpenCL to program FPGA by Altera OpenCL SDK. However, I don't have an Altera FPGA board now. Thus currently I just want to do emulation or simulation to get performance like number of ...
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204 views

Bidirectional FPGA implementations (parallel ADC)

New FPGA convert here. I am trying to interface with a parallel ADC as part of a data acquisition project. The pins on the ADC are used for both input and output (not simultaneously). Therefore, I ...
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75 views

Trying not to be subjective, but is there an affordable development board for CPLD design? [closed]

Yes, I've Googled and I realize this could be considered "subjective" and not "fact based". But, this is the only EE community I know of that isn't centered around a brand (i.e., biased). I'm ...
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1answer
160 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
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184 views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
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153 views

How do I reset an FPGA development board to its factory settings?

I have programmed an Altera board in configuration mode so that it runs my program when booted up. Now I want to revert it back to factory configuration. How do I do that?
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2answers
76 views

Verilog: is connection without wires possible?

I am sorry to ask this question, which I believe is very basic, but I cannot find an answer. The following example clearly works. But I would like to omit the declaration of the wires ay and by. ...
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1answer
54 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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78 views

Simple FPGA serial communication not working

FPGA board (manual) USB-to-RS232 cable (controller) synthesis reports I created a simple schematic which shorts the TXD and RXD pins according to the manual. However, when I use RealTerm to send ...
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67 views

How do I make a real product after building an MP3 player with Altera DE1?

I need to know what the next stage is after programming and testing a MP3 player and such on altera DE1 board. In undergraduate we had a course called microcomputers during which we had to program ...
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116 views

What are retimers?

I am working with a low latency 10G MAC IP core for a Stratix V FPGA. One of the parameters is "High performance mode". The documentation states When enabled, high performance mode enables all ...
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790 views

What is a ripple clock?

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1 Volume 1: Design and Synthesis which states (p. 8): Ripple counters use cascaded registers, in which ...
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50 views

Quartus II hangs when trying to create new project [closed]

I have Quartus II installed under Ubuntu 13.10. It starts up fine, but when I click "finish" on the "Create New Project" wizard, it loads infinitely, stuck at 0%, then stops responding. I have tried ...
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89 views

Access to Quartus II beta

My FPGA card (a BittWare card, datasheet available here) comes with example designs which require Quartus II 14 (beta). I cannot find where the beta versions of Quartus II can be downloaded from the ...
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60 views

Learning FPGA Design (Books, Resources, VHDL/Verilog) [closed]

I used to use FPGA's back in college and I really enjoyed it. Years have passed though and I haven't had much time to play with it since then. I have realized I have forgotten some stuff (quite a bit ...
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1answer
62 views

What are the jitter characteristics of PLLs internal to Stratix V FPGAs?

I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying ...
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354 views

Shematics of the BeMicro CV eval board from Arrow

Where can I find the complete schematics of the board? Arrow sells an ultra low cost FPGA platform with a Cyclone V device on it for around 30$. Ok, for that price it has the bear minimum: 2 buttons, ...
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68 views

How do I minimize the size of a 3-input parallel adder?

Currently this alu uses 24 logic elements, most likely from the adders. I'm wondering if there is any tool in Altera/Quartus I can use to minimize this? For my design, multiplier and RAM modules are ...
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121 views

How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
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231 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
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138 views

Any good suggestions for Basys2 optional oscillator 50 MHz or 100 MHz? [closed]

I want to get the optional stable oscillator for the Basys-2 but don't know which would be the best choice for 50 MHz and 100 MHz? Has anyone bought and used any? If so, what is the part number?
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1answer
64 views

How to find MAX V CPLD pinout

Can someone please explain how to find the pin-out of a 5M80Z CPLD device. The documentation on this page shows the names of the pins but does not indicate the pin numbers. I have not encountered ...
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142 views

Internal fmax of FPGA program

When I compile my project in QUARTUS, it provides me with information about "internal fmax" ...
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1answer
140 views

Designing a peripheral for soft core CPU

I've been implementing a hardware module in VHDL for part of my university dissertation and I want to implement it as part of a NIOS II core in my cyclone 2 FPGA. This uses the Avalon interface, what ...
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1answer
372 views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...
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4answers
330 views

Custom FPGA PCB with external programming circuit

My team has verified our logic design on a development board and we are ready to move to a final prototype. Due to the nature of the device, the FPGA board must contain minimal components and be ...
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1answer
127 views

Quartus II - SignalTap II Getting the Period of Sampled Data

I am working on a VHDL project where I am trying to make an LCD controller. I have been trying to get the period of my scaled clocks using Signal Tap, however the time bar does not show the time ...
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1answer
110 views

Memory logic array blocks VS M20K

I am looking at the Stratix V overview Table 1. In it, they distinguish two types of memories: M20K memory blocks Memory logic array blocks What are the ...
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491 views

How to implement FIR filter for Altera DE2?

I understand that a DSP is preferred rather than FPGA for an FIR filter, but my task is to implement both fixed-point and floating-point software filters (in C) for the Altera DE2. I barely know what ...
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205 views

Why no JTAG connection?

This used to work before I installed Quartus v10 to ensure backward-compatibility. Now I get no hardware found in Quartus both v13 and v10. The USB-Blaster used to show up, then I installed Quartus ...
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1answer
742 views

What are ALMs, LEs and ALUTs?

Does ALM mean "Adaptive logic module"? www.altera.com/literature/ds/ds_nios2_perf.pdf‎ Jul 1, 2013 - One ALUT is equivalent to about 1.25 LEs. Does LE mean logic element and ALUT means ...
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4answers
916 views

Why FPGA's have latches when they are almost never used?

This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both". If use of latches in FPGA's is limited to rarest or rare ...
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626 views

How to wire a system for Nios 2 in Qsys?

I've managed to reduce the number of errors but I still have some: ...
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173 views

VHDL variable behaving strangely

I have the following snippet of VHDL code which is misbehaving and I don't know why: ...
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241 views

How to assign clock/reset to sram in Quartus?

I'm building a system in Quartus according to this question How to upgrade a Quartus II project from SOPC to QSys? Now a part of the problem is how to assign clock/reset pins to my sram. In Quartus ...
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697 views

Quartus II: Where are the worst-case paths?

In the Quartus II settings (under TimeQuest timing analyser), I have checked the Report worst-case paths during compilation checkbox. However, I do not see any ...