A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
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1answer
40 views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
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1answer
72 views

How do I reset an FPGA development board to its factory settings?

I have programmed an Altera board in configuration mode so that it runs my program when booted up. Now I want to revert it back to factory configuration. How do I do that?
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60 views

Verilog: is connection without wires possible?

I am sorry to ask this question, which I believe is very basic, but I cannot find an answer. The following example clearly works. But I would like to omit the declaration of the wires ay and by. ...
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1answer
30 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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2answers
57 views

Simple FPGA serial communication not working

FPGA board (manual) USB-to-RS232 cable (controller) synthesis reports I created a simple schematic which shorts the TXD and RXD pins according to the manual. However, when I use RealTerm to send ...
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51 views

How do I make a real product after building an MP3 player with Altera DE1?

I need to know what the next stage is after programming and testing a MP3 player and such on altera DE1 board. In undergraduate we had a course called microcomputers during which we had to program ...
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1answer
112 views

What are retimers?

I am working with a low latency 10G MAC IP core for a Stratix V FPGA. One of the parameters is "High performance mode". The documentation states When enabled, high performance mode enables all ...
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4answers
582 views

What is a ripple clock?

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1 Volume 1: Design and Synthesis which states (p. 8): Ripple counters use cascaded registers, in which ...
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28 views

Quartus II hangs when trying to create new project [closed]

I have Quartus II installed under Ubuntu 13.10. It starts up fine, but when I click "finish" on the "Create New Project" wizard, it loads infinitely, stuck at 0%, then stops responding. I have tried ...
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2answers
75 views

Access to Quartus II beta

My FPGA card (a BittWare card, datasheet available here) comes with example designs which require Quartus II 14 (beta). I cannot find where the beta versions of Quartus II can be downloaded from the ...
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54 views

Learning FPGA Design (Books, Resources, VHDL/Verilog) [closed]

I used to use FPGA's back in college and I really enjoyed it. Years have passed though and I haven't had much time to play with it since then. I have realized I have forgotten some stuff (quite a bit ...
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1answer
51 views

What are the jitter characteristics of PLLs internal to Stratix V FPGAs?

I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying ...
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215 views

Shematics of the BeMicro CV eval board from Arrow

Where can I find the complete schematics of the board? Arrow sells an ultra low cost FPGA platform with a Cyclone V device on it for around 30$. Ok, for that price it has the bear minimum: 2 buttons, ...
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58 views

How do I minimize the size of a 3-input parallel adder?

Currently this alu uses 24 logic elements, most likely from the adders. I'm wondering if there is any tool in Altera/Quartus I can use to minimize this? For my design, multiplier and RAM modules are ...
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2answers
100 views

How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
4
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1answer
158 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
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1answer
100 views

Any good suggestions for Basys2 optional oscillator 50 MHz or 100 MHz? [closed]

I want to get the optional stable oscillator for the Basys-2 but don't know which would be the best choice for 50 MHz and 100 MHz? Has anyone bought and used any? If so, what is the part number?
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1answer
47 views

How to find MAX V CPLD pinout

Can someone please explain how to find the pin-out of a 5M80Z CPLD device. The documentation on this page shows the names of the pins but does not indicate the pin numbers. I have not encountered ...
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1answer
100 views

Internal fmax of FPGA program

When I compile my project in QUARTUS, it provides me with information about "internal fmax" ...
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1answer
116 views

Designing a peripheral for soft core CPU

I've been implementing a hardware module in VHDL for part of my university dissertation and I want to implement it as part of a NIOS II core in my cyclone 2 FPGA. This uses the Avalon interface, what ...
2
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1answer
272 views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...
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4answers
247 views

Custom FPGA PCB with external programming circuit

My team has verified our logic design on a development board and we are ready to move to a final prototype. Due to the nature of the device, the FPGA board must contain minimal components and be ...
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1answer
87 views

Quartus II - SignalTap II Getting the Period of Sampled Data

I am working on a VHDL project where I am trying to make an LCD controller. I have been trying to get the period of my scaled clocks using Signal Tap, however the time bar does not show the time ...
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1answer
80 views

Memory logic array blocks VS M20K

I am looking at the Stratix V overview Table 1. In it, they distinguish two types of memories: M20K memory blocks Memory logic array blocks What are the ...
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383 views

How to implement FIR filter for Altera DE2?

I understand that a DSP is preferred rather than FPGA for an FIR filter, but my task is to implement both fixed-point and floating-point software filters (in C) for the Altera DE2. I barely know what ...
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138 views

Why no JTAG connection?

This used to work before I installed Quartus v10 to ensure backward-compatibility. Now I get no hardware found in Quartus both v13 and v10. The USB-Blaster used to show up, then I installed Quartus ...
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1answer
456 views

What are ALMs, LEs and ALUTs?

Does ALM mean "Adaptive logic module"? www.altera.com/literature/ds/ds_nios2_perf.pdf‎ Jul 1, 2013 - One ALUT is equivalent to about 1.25 LEs. Does LE mean logic element and ALUT means ...
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4answers
639 views

Why FPGA's have latches when they are almost never used?

This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both". If use of latches in FPGA's is limited to rarest or rare ...
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1answer
464 views

How to wire a system for Nios 2 in Qsys?

I've managed to reduce the number of errors but I still have some: ...
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3answers
163 views

VHDL variable behaving strangely

I have the following snippet of VHDL code which is misbehaving and I don't know why: ...
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1answer
210 views

How to assign clock/reset to sram in Quartus?

I'm building a system in Quartus according to this question How to upgrade a Quartus II project from SOPC to QSys? Now a part of the problem is how to assign clock/reset pins to my sram. In Quartus ...
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1answer
481 views

Quartus II: Where are the worst-case paths?

In the Quartus II settings (under TimeQuest timing analyser), I have checked the Report worst-case paths during compilation checkbox. However, I do not see any ...
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1answer
941 views

How to upgrade a Quartus II project from SOPC to QSys?

I don't understand my errors in QSys, can you help me? I'm trying to go through this exercise: http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf In Qsys when I connect the components I ...
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1answer
609 views

Can't synthesize my VHDL in Qsys

I'm trying to make a module with VHDL for my DE2 where the easy thing ("Hello World") is nearly impossible. The bakground is that I'm trying to run Hello World: ...
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1answer
85 views

How to route a node from one block to another block in Altera Quartus II [closed]

I am new to designing in and coding with with Altera Quartus II version 13 Web edition FPGA software. I am trying to split my design across serval blocks in order to make it more manageable. How do I ...
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0answers
254 views

Altera ModelSim simulating PLL

In my design, I make use of the ATLPLL Library/IP which is to convert the clock frequency accordingly for my design. I am Using De0-Nano board for my project which has cyclone IV FPGA. The ATLPLL ...
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1answer
117 views

Enabling uClinux to run on Altera DE2-115?

I'm trying to learn Qsys and Quartus II to define a system that can run linux according to this document: http://uuoc.org/uClinux_nios2_custom_hardware.pdf But I'm running into problem as the ...
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2answers
521 views

FPGA encoder counter running away randomly

I am programming an Altera FPGA using Quartus II v9.0 to count encoder pulses and output that count to an external LabVIEW program (see diagram below). I was able to debug one issue with my code ...
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4answers
2k views

Generating pulse train of varying frequency on an FPGA

I am working on generating a pulse train to control a motor that accepts a pulse train as an input. Each pulse corresponds to a pre-set movement increment; I can set one pulse equal to 1/1000 degree ...
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1answer
247 views

Quadrature counter on FPGA is running away

I am attempting to count pulses from a quadrature encoder in an Altera FPGA. I believe I have my counter set up correctly (circuit diagram below, following this tutorial), but when I turn my encoder ...
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1answer
113 views

Altera Quartus - How do I simulate a different Entity

I tested the first entity in my project successfully. Now, when I try to create a Vector Waveform File for my second entity, it only lets me add the pins of my first entity. I did set my new entity ...
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2answers
230 views

Understanding timers

I'm studying timers for use in scheduling and embedded systems but I don't understand the detail, does the time count upwards or downwards? Is the timer like a hardware timer like the ones we learnt ...
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2answers
319 views

FIFO wrfull asserted when FIFO is not full

I have an issue with Altera FIFOs. It seems that the full signal wrfull gets asserted even when the FIFO is not full. My FIFOs are of size 8. The SignalTap traces ...
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2answers
533 views

PCIe fails on “polling compliance” state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that ...
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1answer
118 views

Adjustable clock in HDL

I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag - there is no need to recompile the code). ...
2
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1answer
782 views

Is De0-Nano an alternative to Arduino/RaspberryPi?

Arduino and Raspberry Pi are touted as ideal programming boards for beginners and hobbyists. Could De0-Nano fit in that role, too? What does Arduino or RaspberryPi have that De0-Nano does not?
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1answer
219 views

OpenCL for Altera FPGAs

Recently I have been quite interested in OpenCL of the Khronos Group, and already gained some experiences with the language. I'm excited to know that OpenCL now works with Altera FPGA. ...
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107 views

What to change when migrating designs from Altera DE2 to DE2-115?

I'm migrating a working design from Altera DE2 to Altera DE2-115 and I'm running into problems. First everything works with DE2 just like mentioned in the exercises doing what is instructed. Now I ...
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2answers
1k views

Can we run Quartus II on Ubuntu?

I can compile digital components and download them to the boards DE2 and DE2-115 I got. I do it from Windows 7 but I want to enable this on ubuntu while the files from Altera are for Red Hat Linux. ...