ALU is the acronym for arithmetic and logic unit. This circuit performs arithmetic and logic operations in a processor.

learn more… | top users | synonyms

0
votes
1answer
34 views

Verilog 8 Bit ALU

Here's what I have so far but I'm stuck with what to do for the f values for the last two and whether the if statement syntax is correct. Any tips? ...
-1
votes
1answer
39 views

Eight bit ALU with Overflow in Verilog

I have the above assignment and here's what I have so far in verilog: ...
1
vote
4answers
71 views

Does an ALU always do add and sub, but only returns one of the results?

Pretty simple question. Does an ALU internally always do multiple operations like add, sub, div, mul, ... and you simply have to specify which result you want to return? I was told that it does that, ...
1
vote
1answer
47 views

Is the ALU control unit enough to execute all the instructions in a MIPS processor?

The ALU control unit dictates the operation to be done by the ALU. It's truth table though describes only 7 operations, which are enlisted in the truth table below. How the processor handles the rest ...
0
votes
1answer
99 views

How does this reverse NOT gate work?

I created a 74LS181 circuit in Logisim based on TI's datasheet. Notice how the NOT gate for the B0 input has a dot before the triangle: Here's a screenshot of my circuit: Notice that my ...
0
votes
2answers
63 views

Can a multiplier be used to multiply larger numbers? [closed]

Can you do 8 bit multiplication easily with a 4 bit multiplier. Efficiently.
1
vote
2answers
78 views

Design an ALU that only adds

I need some help designing a simple ALU that only can add (4-bit) numbers. For the design I can only use 4-bit full adders and 4-bit edge-triggered flip-flops. I am stuck as I do not even know where ...
1
vote
1answer
75 views

How can z80 uses a 4-bit ALU and return results in a single clock cycle?

According to Ken Sheriff's blog post Z80 ALU is 4-bits wide. If we take a look at page 8 and 9 of Z80 User Guide we will find the following information: Clock states T3 and T4 of a fetch cycle are ...
1
vote
2answers
78 views

How do I multiplex 6 x 4 bit ALU outputs?

I have an ALU that performs 6 functions, each function provides a 4 bit result. I want to multiplex these outputs so they can be selected with an op-code (selector bits of the mux). The only problem ...
1
vote
2answers
95 views

AND gate with a single input in a diagram

consider the following diagram: http://ee-classes.usc.edu/ee459/library/datasheets/DM74LS181.pdf ( page 3 ) The first AND gate at the top left of the schematic has only one input! What does this ...
1
vote
3answers
144 views

How to link ALU to registers, RAM and Clock?

I've designed a basic 4-Bit ALU which computes A+B, A-B, B-A, and a few logic operations. I'm using a mux to determine which output appears at the multiplexer output. This is a basic start to a CPU as ...
0
votes
1answer
85 views

How do ALU flags communicate with the rest of the computer?

How are ALU flags connected to various parts of a computer? I've just finished building an 8 bit computer in Logisim that can add subtract and compare... and am wondering how I can make it multiply ...
2
votes
2answers
211 views

Why does my ALU design delay outputting the results for two clock cycles since input of valid data?

Hello EE StackExchange! I have been trying to design a simple 8-bit CPU for several months now. However, I am experiencing a problem: The ALU outputs the result of the operation two clock cycles ...
0
votes
3answers
674 views

How do I make a 4-bit comparator?

I'm making an ALU (Arithmetic and Logic Unit), I've made a 1-bit ALU with ease, but 1-bit (1b) is impractical, who would need only 1b? I've made that adder/subtractor and I need the comparator ...
3
votes
3answers
232 views

How was the Zero Flag implemented on Z80 ALU?

Z80 was a popular 8-bit processor with a 4-bit ALU. Implementing a zero flag for a register should be straight forward, it would be a logical NOR of all the bits ...
0
votes
1answer
71 views

Carry look ahead adder with 2-input gates?

I would like to make a 8 bit adder, with carry look ahead, but i only have 2-input logic gates. All I've heard about use some at least 4-input gates. Or do I need to use a totally different method, ...
1
vote
3answers
55 views

Is there any difference between using a decoder for the alu op code vs using a multiplexer?

I am a programming student studying electrical engineering fundamentals on the side. I have come across two different methods for getting the result of an operation onto the bus. A decoder accepts ...
1
vote
2answers
97 views

Choosing ALU functions

I am currently taking the Nand2Tetris course online, where I am in the process of building a virtual computer all from nand gates. I have learned what an ALU is, how it works, and build a simple ...
0
votes
1answer
475 views

Equality 4 bit with 4 bit by IC 74181 (ALU)

Pin 14 in IC 74181 when 2 numbers (4bit) equal this pin must be high. This pin is open collector. I connect this pin to Vcc & Res but not high or red. I've created this circuit in Protheus. ...
2
votes
7answers
1k views

Why are 11, 111, 1111, … equivalent to -1 in two's complement? [duplicate]

According to two's complement, the binary numbers 111 and 11111111 are equivalent to -1. Why or how are the binary numbers 11, 111, 1111, 1111 1111, etc. equivalent to -1 in two's complement? Can ...
4
votes
3answers
291 views

Why All 1's used as a second input in decrement operation of ALU?

Suppose the first four data inputs are X (X0, X1, X2, X3) and the second four data inputs are Y (Y0, Y1, Y2, Y3) in a 4-bit ALU. Why "All 1's" are used as an input for Y in the decrement operation of ...
-1
votes
1answer
78 views

Can a microprocessor ( specifically the ALU) be considered as an FPGA that is re-programmed by the Instruction Decoder

So, I have been reading about FPGAs. As I understand, they work by providing logic blocks for the programmer to link together to solve a particular task. Many such tasks may run in parallel; so an ...
-1
votes
1answer
152 views

Wallace tree multiplication rules

I was looking at this wallace tree diagram for an 8x8 multiplier: and I'm confused about why the pairs of two (and the one pair of 3) are not added together in the initial reduction layer. My ...
0
votes
1answer
42 views

Learning about multipliers, confused about cycles in relation to Wallace tree

At this link: http://en.wikibooks.org/wiki/Microprocessor_Design/Multiply_and_Divide_Blocks It says that a wallace tree can be used to perform multiplication in a single cycle. I'm assuming then ...
0
votes
1answer
160 views

Implementing Integer Division in hardware

I am trying to figure out how to create an efficient way to divide 5 bit numbers in hardware (using registers, Shift Registers, Comparators, Muxes, basic logic gates, bit shifters, bit extenders, and ...
2
votes
3answers
135 views

Curious how does ALU addressing work like in Assembly code?

When writing assembly code, say R1 = R2 + R3, it is pretty easy to understand the addressing procedure because all registers are close to the ALU. But I find it hard to see how does the ALU go to the ...
0
votes
2answers
143 views

How does Decimal Mode in an ALU work?

Trying to wrap my head around the basic of how to do decimal addition in an ALU. Here is what I have so far. I am primarily looking at the MOS 6502 CPU architecture. It has two modes in which you ...
2
votes
2answers
402 views

How do you do operations on large numbers using a small fixed-width ALU?

I am wanting to design a simple calculator like what you would find in the dollar store. Something like this: This little guy can display a number 8 digits long, meaning 99999999 is the largest ...
0
votes
1answer
151 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
-4
votes
2answers
464 views

I need help with verilog code, I am in trouble?

I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
1
vote
1answer
73 views

How do you reduce an 8 output ALU to a 4 or 3 output ALU?

I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...
-2
votes
1answer
164 views

Would it be practical to build a chip that can do this math?

I was theorizing a new kind of 64-bit number for use in data storage, but then started wondering if it could become practical if created in hardware. (I believe it would be too slow if only software ...
1
vote
1answer
159 views

How is the zero flag set in terms of hardware? [duplicate]

I'm angling this as a general question on the assumption that it doesn't differ significantly with architecture - at least at the level I'm asking. I'm curious how - in terms of hardware, not the ...
4
votes
1answer
17k views

How to shift left/right a STD_LOGIC_VECTOR value within a WHEN statement?

I'm attempting to create a parametrizable ALU which handles N-Bit signed data. However the methods I know of shifting left/right, either won't work because the values are defined as STD_LOGIC_VECTOR: ...
1
vote
1answer
141 views

CISC, microcode execution flow

Say we have 16 bit processor and such CISC instruction: 0001 0010 0100 1000 As far as I understood from the answer on related question In the process of decoding, this CISC instruction will be ...
0
votes
1answer
470 views

Active high and active low in IC

I am using an alu SN74ls181 . I am unable to figure out how active high and active low are decided . Is it during the manufacturing or some circuit parameters decide if the circuit is active high or ...
5
votes
1answer
569 views

Creating an ALU slice with 8 operations

Hey, I'm trying to implement a 4bit ALU based on this 8bit alu design. The ALU has 8 different operations, given by an input of X Y Z The 8 operations are (edit: the last one is just A not, made ...
3
votes
1answer
241 views

Are there gate-level ways to produce the min or max of two binary values?

Some basics of digital logic are the half adder and full adder. We know how to produce the sum of two binary values at the level of and/or/not gates, in a straightforward way presented in many ...
3
votes
3answers
561 views

Design ALU with 2 Select lines, 2 Inputs ( n bits )

I want to design ALU with 2 select lines , 2 inputs ( n bits ) that do the following: this is a homework and I want to know what to do, writ to me the steps for design it. the first thing I thought ...
2
votes
2answers
296 views

Trouble on understanding ALU 2-bit design

I'm new to this site and I'm pretty "noobish" to electrical engineering coming from a software engineering background I was hoping someone could help me understand this design a bit. I've highlighted ...
2
votes
2answers
765 views

Is the registry file made from SRAM?

I study computer engineering and I read Hennessy's book about Computer Organization where it's described how the microprocessor does pipelining and that the microproceossor has on-chip cache, as much ...
0
votes
1answer
748 views

What's the difference between delayed branch and branch prediction?

I'm studying how delayed branch works and I'm trying to distinguish delayed branch from branch prediction. What is the difference? Is delayed branch a means to facilitate a control hazard?
0
votes
1answer
256 views

What to change when migrating designs from Altera DE2 to DE2-115?

I'm migrating a working design from Altera DE2 to Altera DE2-115 and I'm running into problems. First everything works with DE2 just like mentioned in the exercises doing what is instructed. Now I ...
-2
votes
1answer
83 views

Getting my head around ALUs

What is a good place to start understanding about ALU's? Lots of sites seem very over the top and complex, can anyone recommend a good place to start? Thanks in advance, James
2
votes
1answer
701 views

4 Bit ALU addition

What are the values of the Z, V, C and N bits in the status register after the operation 1000 + 1111 for a 4-bit ALU?
3
votes
1answer
339 views

Parallel multiplication hardware

This picture is taken from Computer Organization and Design, Fourth Edition, David A. Patterson, John L. Hennessy. Sorry for the low resolution. I cannot get my head around it. I can see why the ...
0
votes
1answer
205 views

Why is carry on for an adder that is simply on? [closed]

I've understood that the behaviour is correct when I make a simple adder: But why does carry on light up just because I switch on the + operation for my 4-bit system? ...
-1
votes
1answer
128 views

Running the linux kernel and ubuntu on a custom processor [closed]

This is hardly a theoretical question as many have done this, albeit there's very little information on the underlying processes. I'm developing a custom MIPS-based processor on which I would like ...
2
votes
3answers
806 views

Confused as to how implement ALU using structured VHDL

I am new to VHDL, working on assignment for my Computer architecture class: implement 32 bit ALU using VHDL, that performs only certain operations: and, ...
8
votes
3answers
2k views

Designing a simple ALU

I need to design an ALU with two 8-bit inputs A and B and control inputs x, y, and z that supports the following operations: ...