Cache is a type of memory used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory. The cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations.

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Is cache memory unnecessary in microcontrollers?

Do we use cache memory in microcontrollers, if not, why not? If yes, what is its application in embedded systems or it is enough just to have RAM?
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391 views

How do you calculate Byte Offset?

I am confused by the concept of byte offset. In my textbook the examples always show the word aligned byte offset as being two bits but doesn't really explain how they arrive at that value. It says ...
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4answers
212 views

direct mapping cache question

I have been doing the question below in what I thought was the correct way. After doing some more reading I am now slightly confused and would appreciate some clarification. Previously I was just ...
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1answer
58 views

CPU ports and cache controllers

I have seen CPUs conforming to Harvard architecture with dedicated ports for program memory and data memory. I have also seen that instruction and data caches (read-through caches) are connected to ...
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1answer
102 views

Is there a wire (a bus), albeit a very short one, between the CPU and its level-1 cache?

I was wondering what is the specific connection mechanism between the CPU and its level-1 cache so that in practice level-1 cache access time is reduced to match the CPU clock frequency? Do level-1 ...
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1answer
393 views

how to calculate CPI?

The miss rate in the instruction and data cache is 3% .A processor has a base CPI of 1.5 when all references hit the cache and a clock rate of 4 GHz. The time to access main memory is 50 ns ...
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80 views

find cache hit rate for direct mapped cache memory

I have this practice exam problem which I am having trouble with. I have gone over many slides but haven't been able to really get it. The question is I currently have an 8 block main memory with ...
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3answers
114 views

Increasing cache line size when cache and RAM don't work asynchrounsly

I want to improve a processor design. It has a simple directly mapped cache, and I want to improve the hit rate. I've been working on increasing the cache line size from one data word to four, but ...
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1answer
100 views

Improving a processor design in VHDL

For a project at my university we have to improve the design of a processor (more specifically, the Plasma CPU. The design is generated based on a description written in VHDL. We have to identify ...
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1answer
60 views

What are the meanings of the fields of this cache memory?

I have a cache memory simulator with this cache memory shown. The cache size is 64 bytes and the block size is 8 bytes. What is the decomposition into fields? If block size is 8 bytes, then ...
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2answers
48 views

What are the bits for this cache?

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. The physical address is 50 bits, numbered from 0 to 49 (with 0 being the least significant ...
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1answer
33 views

Which are the spec bits in this cache?

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. The physical address is 50 bits, numbered from 0 to 49 (with 0 being the least significant ...
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2answers
522 views

How does CPU read data from the RAM?

In a general purpose computer(like normal pc), how does the CPU read the RAM, assuming that it first reads from the ...
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346 views

How much energy does cache memory consume in a modern processor? [closed]

What fraction (on average or range) of total processor energy consumption does the cache subsystem consume in modern processors (say post 2009)?
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1answer
87 views

How do I get the index of these word addresses? [closed]

We are given 32 bit memory address references. For example: 180, 43,2. We are asked to find the index "given a direct-mapped cache with two-word blocks and a total size of 8 blocks". Mind you have ...
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2answers
814 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
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1answer
2k views

Calculate Paging System

I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it. A paging system has the following parameters: 2^32 bytes of physical memory; page size of ...
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1answer
461 views

Determining physical address for logical address

I have a simple segmentation system with the following segment table: ...
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0answers
91 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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1answer
289 views

How to calculate cache size?

A cache with a line size of L 32-bit words, S number of sets, W ways, and addresses are made up of A bits. Assume that the cache is word addressed, i.e., the low two bits of the address are ...
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1answer
175 views

Direct cache vs. associative cache

Trying to solve this problem where direct cache would outperform associative: Propose you have a cache with a line size of L 32-bit words, S number of sets, W ways, and addresses are made up of A ...
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1answer
361 views

Calculating Cpi with Miss Rate

In my assignment I have the following question: The processor has a clock rate of 1 GHZ. The miss rate in the instruction cache is 1.5%. The miss rate in the data cache is 4%. 30% of the instruction ...
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3answers
30 views

Spatial Locality in Cache - Which addresses are loaded?

I don't understand quite well the concept of spatial locality in cache. I understand that when there is a miss in the cache, not only the specific address we write is loaded into the cache, but also ...
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1answer
2k views

Three way set associative cache with LRU replacement

So I am going through a homework exercise, and I am not understanding the solution to the problem. We are given a sequence of memory references and we are to use a three-way set associative cache with ...
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1answer
75 views

Measuring power consumption of cache memories?

Is there any practical method to only measure the power consumption of combined cache memory. I am intereted in measuring the power conumption overhead when replacing blocks, and or filling the cache ...
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1answer
1k views

Precharging circuits in SRAM

I got to know 4 circuits used for Precharging in SRAM. I have few questions regarding circuits explanation: Diagram (a): Q1: It mentions it as diode-connected NMOS pair. Why? Q2: This burns more ...
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Why is L1 cache faster than L2 cache?

I'm trying to understand why certain CPU cache memories are faster than others. When comparing cache memory to something like main memory, there are differences in memory type (SRAM vs DRAM), and ...
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2answers
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CPU Cache implementation in VHDL

I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL. I know the required theory for carrying out this ...
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1answer
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Why do we need the MOESI/MESIF protocols?

As I understand, those two protocols add an extra state to identify which cache should respond to a miss request from another cache for a particular cache-line. But, in the MESI protocol, only one ...
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Direct Mapped Cache [duplicate]

A computer using a direct-mapped cache has \$2^{24}\$ words of main memory and a cache of 256 blocks. Each cache block contains 64 words. How many blocks of main memory are there? What is the format ...
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1answer
824 views

Virtual Memory, Cache, and TLB's

I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question. I'm trying to study for an exam ...
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3answers
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Is there a correspondence between cache size and access latency?

Is there is a correspondence between cache sizes and access latency? All other things being equal, does a larger cache operate slower? If so, why? How much slower?
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1answer
3k views

How many bits are used for the tag, block, and offset fields for the representation of a memory address?

A small byte-addressable embedded computer system, with a word length of 32 bits, has a main memory consisting of 4 KBytes. It also has a small data cache capable of holding eight 32-bit words, ...
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1answer
430 views

What is asked by this question re cache memory?

I've a difficulty understanding what is asked by this questions: Can you explain in more detail? AFAIK the associativity determines the number of sets and the size of the set determines the number ...
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1answer
233 views

unable to understand write policy in Cache memory

I am studying write policies in cache memory ( for first time ). I am able to understand the 'write-through' but i am not able to understand 'write back' and the problems associated with it . Please ...
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1answer
90 views

Why does small cache memory take less time to index

I was going though these slides (page 3) which are adapted from Computer Architecture: A Quantitative Approach, 4th Edition by Patterson and Hennessey. The topic is about Advanced Cache ...
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1answer
86 views

How to calculate the address fields for a cache?

I've a homework question about 32-bit cache memories: For a cache memory that has size 16kB (16384 byte) and blocksize 2 words, state the names and the sizes of each field of the address that ...
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1answer
80 views

How to know which element replaces which for a cache?

If I assume that the first element of the matrix that is fetched to the D-cache is a[0][0], for associativity 4, please tell me which element in which matrix that ...
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1answer
63 views

How to explain the results from different block sizes?

I vary the D-cache block size for a program. I test different block sizes for the D-cache, block sizes from 1 to 8. Size = 128 words, and blocks in sets (associativity) = 1. ...
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2answers
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Why is the hit rate so bad until the cache has a certain size?

For a certain cache, these are the measurements: Test of different sizes of cache memory, from 16 to 1024 words, Block size = 2 words and assosiativity = 1. Access time: 20 cycles. ...
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1answer
71 views

Is associativity number for caches per row?

If a cache memory has associativity 4, then it means than the memory has "4 blocks per set" but how do I visualize it? It "4 blocks per set" the same as "4 blocks per row" so that a cache memory with ...
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1answer
139 views

How to best understand cache associativity?

AFAIK this definition is the most clear and physical: Associativity number = Number of comparators. Is it correct? Could you make a more precise / better definition? The wikipedia illustration is ...
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Number of bits for tag, index, and block in a direct-mapped cache

Suppose you have a 64-byte cache on a system with 16-bit memory addresses. If the cache is direct-mapped and it has 10 bytes of tag overhead in total, how many bits are used for the tag, index, and ...
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1answer
228 views

Processor - L1 Data cache interface

Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer: I'm ...
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1answer
518 views

How to calculate access time for a cache simulation?

We're simulating a MIPS cache with a program called MipsIT. We've reached a point where we should set access time for the memory. But I don't understand how to calculate this setting. It says in ...
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1answer
79 views

Please explain the details of cache circuit addressing

My cache can have 32 address bits with 2 bits for index and 3 bits for byte-offset. Associativity 2, block size 8. Of course, the the bits for index says which row of the cache the data is. But ...
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1answer
687 views

How to calculate index and tag fields lengths for a cpu cache?

I study computer engeering notes for a cache memory and I try to understand what determines the length of the index and the tag fields. The first examples is for 64 bits and the second example is for ...
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2answers
727 views

Verilog asynchronous reads of regs - and design question

I'm trying to understand what the following bit of behavioral code, what kind of hardware it turns into: ...
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2answers
1k views

What determines the number of bits for the address field in a cache memory?

I understand a cache memory is constructed for a basic block like this Valid bit | Address bits | Data/Instruction But what determines the length of the address bits? I understand that for a 32-bit ...
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2answers
662 views

Difference between 2-way and 4-way caches?

I don't fully understand this picture: If the data and instruction caches are separated, doesn't that mean that this CPU is not von Neumann model but Harvard model? And what does it mean that one ...