The cache tag has no wiki summary.
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1answer
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How to calculate the address fields for a cache?
I've a homework question about 32-bit cache memories:
For a cache memory that has size 16kB (16384 byte) and blocksize 2
words, state the names and the sizes of each field of the address that
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0
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1answer
43 views
How to know which element replaces which for a cache?
If I assume that the first element of the matrix that is fetched to the D-cache is a[0][0], for associativity 4, please tell me which element in which matrix that ...
0
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1answer
34 views
How to explain the results from different block sizes?
I vary the D-cache block size for a program. I test different block sizes for the D-cache, block sizes from 1 to 8. Size = 128 words, and blocks in sets (associativity) = 1.
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2answers
93 views
Why is the hit rate so bad until the cache has a certain size?
For a certain cache, these are the measurements:
Test of different sizes of cache memory, from 16 to 1024 words, Block size = 2 words and assosiativity = 1. Access time: 20 cycles.
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0
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1answer
47 views
Is associativity number for caches per row?
If a cache memory has associativity 4, then it means than the memory has "4 blocks per set" but how do I visualize it? It "4 blocks per set" the same as "4 blocks per row" so that a cache memory with ...
3
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1answer
52 views
How to best understand cache associativity?
AFAIK this definition is the most clear and physical:
Associativity number = Number of comparators.
Is it correct? Could you make a more precise / better definition?
The wikipedia illustration is ...
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2answers
218 views
Number of bits for tag, index, and block in a direct-mapped cache
Suppose you have a 64-byte cache on a system with 16-bit memory addresses. If the cache is direct-mapped and it has 10 bytes of tag overhead in total, how many bits are used for the tag, index, and ...
1
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1answer
76 views
Processor - L1 Data cache interface
Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer:
I'm ...
0
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1answer
119 views
How to calculate access time for a cache simulation?
We're simulating a MIPS cache with a program called MipsIT. We've reached a point where we should set access time for the memory.
But I don't understand how to calculate this setting. It says in ...
1
vote
1answer
47 views
Please explain the details of cache circuit addressing
My cache can have 32 address bits with 2 bits for index and 3 bits for byte-offset.
Associativity 2, block size 8.
Of course, the the bits for index says which row of the cache the data is.
But ...
2
votes
1answer
182 views
How to calculate index and tag fields lengths for a cpu cache?
I study computer engeering notes for a cache memory and I try to understand what determines the length of the index and the tag fields. The first examples is for 64 bits and the second example is for ...
2
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2answers
142 views
Verilog asynchronous reads of regs - and design question
I'm trying to understand what the following bit of behavioral code, what kind of hardware it turns into:
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0
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2answers
112 views
What determines the number of bits for the address field in a cache memory?
I understand a cache memory is constructed for a basic block like this
Valid bit | Address bits | Data/Instruction
But what determines the length of the address bits? I understand that for a 32-bit ...
3
votes
2answers
122 views
Difference between 2-way and 4-way caches?
I don't fully understand this picture:
If the data and instruction caches are separated, doesn't that mean that this CPU is not von Neumann model but Harvard model?
And what does it mean that one ...
1
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3answers
148 views
Physical address vs virtual address
Physical address is hardware address of physical memory and virtual address is the one the processor will be seeing, it has it has a tag and offset. I understand this. Can any one describe it with an ...
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2answers
57 views
Data processing vs instruction processing in processor [closed]
What a processor does with instructions and with data using examples.
Why does it need data if it is processing an instruction?
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3answers
112 views
Cache write/read times?
I would like to devise certain rules of thumb to help solve certain computer design/architecture challenges. Hence, in memory, which operations typically take longer to execute: loads or stores?? I ...
1
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2answers
117 views
Sorting of data from instructions ( ARM I-cache and D-cache )
Some ARM cores like the ARM9 family of cores have a Harvard Architecture, at least at the cache level. That is they access two seperate caches, an I-cache for instructions and a D-cache for data ( ...
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5answers
196 views
stack cache instead of registers
Is there a processor that do arithmetic operations on a stack and not on registers? To keep performance, of course, that processor should cache top block of a stack in the same type of memory that is ...
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2answers
88 views
How does the Processor unit identify if the decoded instructions when it wants the next instruction?
I have read that to avoid cache misses, a lot of instructions are fetched together and decoded and kept in the cache, as it is mostly the case the instructions near the REQUESTED INSTRUCTION will be ...
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2answers
162 views
A Strange Computer : Cache based computer [closed]
In the Operating System class I heard from Professor that in some institute, researchers are working on cache based computer ( means the computer that don't have RAM and have a big cache ( probably 1 ...
3
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1answer
219 views
Cache. MESI protocol for multilevel cache in Intel processors
Now I'm trying to simulate the performance of Intel CORE 2 Duo processor (but I'll be very pleased with information about any other multi-core Intel processor) and it's work with the computer memory. ...
3
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2answers
162 views
Fully Associative cache offset bits
When dealing with a fully associative cache, why is it necessary to use an offset (or word), if the entire cache is being searched anyway what will the offset do for you?
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2answers
373 views
Are page table walks cached?
On a microprocessor with hardware TLB management (say an Intel x86-64) if a TLB miss occurs and the processor is walking the page table, are these (off-chip) memory accesses going through the cache ...
4
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2answers
71 views
Controller Resets after Enabling Cache
I am using a MCF5253 controller which is based on Coldfire Architecture.
It has 8KB of Instruction Cache.
Everything was working fine till I enabled it's Instruction Cache.
Now what's happening is ...
2
votes
3answers
681 views
I know why DRAM is slower to write than to read, but why is the L1 & L2 cache RAM slower to write?
DRAM is slower to write than read because it takes time to either charge or discharge a DRAM memory cell. But what about the SRAM in my processor's L1 and L2 caches? It's slower to write as well but ...
