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23 views

Measuring power consumption of cache memories?

Is there any practical method to only measure the power consumption of combined cache memory. I am intereted in measuring the power conumption overhead when replacing blocks, and or filling the cache ...
1
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1answer
66 views

Precharging circuits in SRAM

I got to know 4 circuits used for Precharging in SRAM. I have few questions regarding circuits explanation: Diagram (a): Q1: It mentions it as diode-connected NMOS pair. Why? Q2: This burns more ...
4
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3answers
244 views

Why is L1 cache faster than L2 cache?

I'm trying to understand why certain CPU cache memories are faster than others. When comparing cache memory to something like main memory, there are differences in memory type (SRAM vs DRAM), and ...
0
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2answers
312 views

CPU Cache implementation in VHDL

I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL. I know the required theory for carrying out this ...
1
vote
1answer
227 views

Why do we need the MOESI/MESIF protocols?

As I understand, those two protocols add an extra state to identify which cache should respond to a miss request from another cache for a particular cache-line. But, in the MESI protocol, only one ...
0
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0answers
23 views

Direct-Mapped Cache [duplicate]

I am a bit confused about the tables with direct mapped cache. I've attached picture of the problem, I know some stuff but, I don't know how to determine the size of the tag, offset and set. Can ...
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2answers
130 views

Direct Mapped Cache [duplicate]

A computer using a direct-mapped cache has \$2^{24}\$ words of main memory and a cache of 256 blocks. Each cache block contains 64 words. How many blocks of main memory are there? What is the format ...
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0answers
94 views

Virtual Memory, Cache, and TLB's

I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question. I'm trying to study for an exam ...
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0answers
97 views

Doubts in two level cache system

A computer system has an L1 cache, an L2 cache, and a main memory unity connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times ...
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3answers
358 views

Is there a correspondence between cache size and access latency?

Is there is a correspondence between cache sizes and access latency? All other things being equal, does a larger cache operate slower? If so, why? How much slower?
0
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1answer
528 views

How many bits are used for the tag, block, and offset fields for the representation of a memory address?

A small byte-addressable embedded computer system, with a word length of 32 bits, has a main memory consisting of 4 KBytes. It also has a small data cache capable of holding eight 32-bit words, ...
0
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1answer
126 views

What is asked by this question re cache memory?

I've a difficulty understanding what is asked by this questions: Can you explain in more detail? AFAIK the associativity determines the number of sets and the size of the set determines the number ...
1
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1answer
77 views

unable to understand write policy in Cache memory

I am studying write policies in cache memory ( for first time ). I am able to understand the 'write-through' but i am not able to understand 'write back' and the problems associated with it . Please ...
0
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1answer
77 views

Why does small cache memory take less time to index

I was going though these slides (page 3) which are adapted from Computer Architecture: A Quantitative Approach, 4th Edition by Patterson and Hennessey. The topic is about Advanced Cache ...
0
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1answer
52 views

How to calculate the address fields for a cache?

I've a homework question about 32-bit cache memories: For a cache memory that has size 16kB (16384 byte) and blocksize 2 words, state the names and the sizes of each field of the address that ...
0
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1answer
58 views

How to know which element replaces which for a cache?

If I assume that the first element of the matrix that is fetched to the D-cache is a[0][0], for associativity 4, please tell me which element in which matrix that ...
0
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1answer
45 views

How to explain the results from different block sizes?

I vary the D-cache block size for a program. I test different block sizes for the D-cache, block sizes from 1 to 8. Size = 128 words, and blocks in sets (associativity) = 1. ...
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2answers
111 views

Why is the hit rate so bad until the cache has a certain size?

For a certain cache, these are the measurements: Test of different sizes of cache memory, from 16 to 1024 words, Block size = 2 words and assosiativity = 1. Access time: 20 cycles. ...
0
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1answer
54 views

Is associativity number for caches per row?

If a cache memory has associativity 4, then it means than the memory has "4 blocks per set" but how do I visualize it? It "4 blocks per set" the same as "4 blocks per row" so that a cache memory with ...
4
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1answer
79 views

How to best understand cache associativity?

AFAIK this definition is the most clear and physical: Associativity number = Number of comparators. Is it correct? Could you make a more precise / better definition? The wikipedia illustration is ...
0
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2answers
3k views

Number of bits for tag, index, and block in a direct-mapped cache

Suppose you have a 64-byte cache on a system with 16-bit memory addresses. If the cache is direct-mapped and it has 10 bytes of tag overhead in total, how many bits are used for the tag, index, and ...
2
votes
1answer
128 views

Processor - L1 Data cache interface

Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer: I'm ...
0
votes
1answer
211 views

How to calculate access time for a cache simulation?

We're simulating a MIPS cache with a program called MipsIT. We've reached a point where we should set access time for the memory. But I don't understand how to calculate this setting. It says in ...
1
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1answer
60 views

Please explain the details of cache circuit addressing

My cache can have 32 address bits with 2 bits for index and 3 bits for byte-offset. Associativity 2, block size 8. Of course, the the bits for index says which row of the cache the data is. But ...
2
votes
1answer
359 views

How to calculate index and tag fields lengths for a cpu cache?

I study computer engeering notes for a cache memory and I try to understand what determines the length of the index and the tag fields. The first examples is for 64 bits and the second example is for ...
2
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2answers
355 views

Verilog asynchronous reads of regs - and design question

I'm trying to understand what the following bit of behavioral code, what kind of hardware it turns into: ...
0
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2answers
334 views

What determines the number of bits for the address field in a cache memory?

I understand a cache memory is constructed for a basic block like this Valid bit | Address bits | Data/Instruction But what determines the length of the address bits? I understand that for a 32-bit ...
4
votes
2answers
239 views

Difference between 2-way and 4-way caches?

I don't fully understand this picture: If the data and instruction caches are separated, doesn't that mean that this CPU is not von Neumann model but Harvard model? And what does it mean that one ...
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3answers
202 views

Physical address vs virtual address

Physical address is hardware address of physical memory and virtual address is the one the processor will be seeing, it has it has a tag and offset. I understand this. Can any one describe it with an ...
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2answers
72 views

Data processing vs instruction processing in processor [closed]

What a processor does with instructions and with data using examples. Why does it need data if it is processing an instruction?
1
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3answers
162 views

Cache write/read times?

I would like to devise certain rules of thumb to help solve certain computer design/architecture challenges. Hence, in memory, which operations typically take longer to execute: loads or stores?? I ...
3
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2answers
245 views

Sorting of data from instructions ( ARM I-cache and D-cache )

Some ARM cores like the ARM9 family of cores have a Harvard Architecture, at least at the cache level. That is they access two seperate caches, an I-cache for instructions and a D-cache for data ( ...
6
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5answers
355 views

stack cache instead of registers

Is there a processor that do arithmetic operations on a stack and not on registers? To keep performance, of course, that processor should cache top block of a stack in the same type of memory that is ...
0
votes
2answers
160 views

How does the Processor unit identify if the decoded instructions when it wants the next instruction?

I have read that to avoid cache misses, a lot of instructions are fetched together and decoded and kept in the cache, as it is mostly the case the instructions near the REQUESTED INSTRUCTION will be ...
0
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2answers
181 views

A Strange Computer : Cache based computer [closed]

In the Operating System class I heard from Professor that in some institute, researchers are working on cache based computer ( means the computer that don't have RAM and have a big cache ( probably 1 ...
3
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1answer
418 views

Cache. MESI protocol for multilevel cache in Intel processors

Now I'm trying to simulate the performance of Intel CORE 2 Duo processor (but I'll be very pleased with information about any other multi-core Intel processor) and it's work with the computer memory. ...
3
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2answers
196 views

Fully Associative cache offset bits

When dealing with a fully associative cache, why is it necessary to use an offset (or word), if the entire cache is being searched anyway what will the offset do for you?
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2answers
678 views

Are page table walks cached?

On a microprocessor with hardware TLB management (say an Intel x86-64) if a TLB miss occurs and the processor is walking the page table, are these (off-chip) memory accesses going through the cache ...
4
votes
2answers
77 views

Controller Resets after Enabling Cache

I am using a MCF5253 controller which is based on Coldfire Architecture. It has 8KB of Instruction Cache. Everything was working fine till I enabled it's Instruction Cache. Now what's happening is ...
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3answers
1k views

I know why DRAM is slower to write than to read, but why is the L1 & L2 cache RAM slower to write?

DRAM is slower to write than read because it takes time to either charge or discharge a DRAM memory cell. But what about the SRAM in my processor's L1 and L2 caches? It's slower to write as well but ...