A digital signal that goes high and low at a specific frequency.

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54 views

STM32F4 clock 60Mhz

I want to set my STM32F446 controller his clockfrequency to 60MHz. I thought I could do it, but without results. I am using an STM32F446 -nucleo board. I used STM32CubeMX to generate my code. After ...
0
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0answers
60 views

STM32 if-statement timing

I'm working on a porject where I need to communicate with an USB PHY chip. I am using a STM32 microcontoller. (stm32f446ret6, ...
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1answer
39 views

Digital Clock - set time x hours ahead?

I have a digital clock made from an electronic kit - it has 3 buttons (1 to set the time, 1 to set alarm, 1 to cancel the alarm). I want to be able to set it so every time it is connected to power ...
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1answer
63 views

Need Help In Creating and Debugging a 8Mhz CLK Circuit

I want to create a CLK generator circuit that will work at 8Mhz. I'm following this design (from http://www.electronics-tutorials.ws/oscillator/crystal.html): My crystal is 8Mhz HC49/US, with 20pF ...
3
votes
1answer
58 views

Why is my VHDL clock signal so far off from what I thought it would be?

I'm new to FPGA and VHDL. The following code was supposed to be 5MHz but I'm getting 4.167MHz on my scope. The FPGA board I ...
2
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1answer
36 views

In which physical unit is 'clock drift' measured?

I would like to model a clock signal with an drift parameter in my digital simulation. The current implementation handles: frequency / period phase -360.0 .. 360.0 degree duty cycle 0.0 .. 1.0 ...
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1answer
63 views

Clock and data vs rx and tx communication

I'm working on a project in which I have to make two pic10f200 microcontrollers communicate via serial communication lines. I know that with Arduino you interconnect the two board's rx and tx lines, ...
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0answers
46 views

Cycles lost on clock domain crossing

I have a MAC (VHDL) connected to the PHY through RGMII (so the clock for this communication is 125 MHz). The MAC outputs every byte at a rate of 200 MHz, so there is some clock domain crossing here. ...
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1answer
60 views

frequency divider by 42 with 50% duty cycle

I want to design a clock divider by 42 from flip flops. Is there a way to do that while still gets 50% duty cycle?
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2answers
61 views

GPS 1 PPS Aligment Clock Signal Generator

i want to do GPS 1 pps aligment clock signal generator. Clock signal should be at 24.576 Mhz and voltage level Vmax= 3.3 V and Vmin=0 V DC. How can i do that? It is very important to align between GPS ...
0
votes
4answers
71 views

How to generate edge-triggered pulse

First, a bit of background: I am just a hobbyist with electronics and have very little formal education in the area. I understand most terminology, but generally require a schematic for me to be able ...
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3answers
188 views

Understanding Test Parameters on Datasheet (CL pF)

On Page 7 of the datasheet for M74HC590 It uses a CL (pF) At the bottom of Page 8 is the test circuit which shows where the CL(pF) goes, in regards to a circuit diagram, but I don't understand that ...
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0answers
50 views

Nixie Tube Clock Kit Issues

I recently purchased the Lena kit from Nixiekits.eu http://nixiekits.eu/Laura+Lars.htm The manual: http://nixiekits.eu/Downloads/USB_Nixie_Clocks_Aufbauanleitung.pdf After putting it together ...
4
votes
2answers
315 views

How to generate high frequency clock with high stability from a microcontroller?

I am using TivaC launchpad TM4C123G microcontroller, to generate a clock of 40 MHZ but I tested it on the oscilloscope and it doesn't look like a square wave it's more like a sinusoidal here is a ...
0
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0answers
34 views

I get error in vivado when I try to use source clock of generated one

I want to have two clocks in my project. One that sends output to a VGA and runs at 25 Mhz and another which runs my mandelbrot set calculation at a higher frequency. Here is the code I have. ...
0
votes
1answer
86 views

Output 48MHz system clock on a GPIO pin other than MCO pin on STM32F030

I want to output the max 48MHz clock signal of STM32F030 to drive another subcircuit. The problem is the chip STM32F030F4P6 (TSSOP-20 package) I prefer to use a GPIO because the MCU doesn't have the ...
4
votes
2answers
711 views

Can I produce a square wave(basically a clock) from a USB port on my Laptop? If yes how?

Can I produce a square wave(basically a clock) from a USB port on my Laptop? If yes how ? Briefly explaining, I am using ad9834 in a project and this chip needs a clock of any frequency ranging ...
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0answers
96 views

Find maximum clock frequency at which a given counter can be operated

What should be the maximum frequency at which the given counter can be operated: Each AND gate, JK flip flop takes 10ns, as propagation delay. My solution: To calculate that we need to know the ...
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2answers
76 views

10 USB Hub ICs from 1 Crystal Oscillator?

I am designing a PCB with 10 individual USB hub ICs onboard. They all require a clock input and I am wondering if it is possible to drive all the clocks from a single crystal oscillator? The hub IC ...
0
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1answer
61 views

Strange ADC sampling frequency / clock frequency on STM32F401 board

I use a timer to trigger ADC sampling on STM32F401, and the interrupt service routine of ADC will toggle a GPIO pin so that I can measure the ADC sampling frequency using an oscilloscope (which should ...
0
votes
1answer
47 views

How to set SD card clock frequency between 100 kHz - 400 kHz

I am interfacing a 32 GB microSD card with PIC32MX795F512L. I am following the examples provided in Lucio de Jasio's book. As the author has described that to set a 250 kHz, they are ...
3
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0answers
33 views

Does sequential clock gating useful? [closed]

I know there is clock gating method that xor-ing the input and output of FF, and use that signal as clock enable. (figure 1, i'll call it xor-ing from now) I'm now studying sequential clock gating. I ...
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3answers
91 views

How to delay a “not gate oscillator” to make it run at a desired frequency?

I want to blink an led(0.75 seconds on and 0.75 seconds off) repeatedly. I was thinking of using an idea from a book called "But How Do It Know" by J. Clark Scott. A part of the book tries to explain ...
3
votes
1answer
72 views

Xilinx clocking wizard - How to connect clkfb_in and clkfb_out

I created a VHDL design which needs a 50 MHz clock input. The Spartan-6 I'm working on gives me a 100 MHz clock signal, so I used the Xilinx Clocking Wizard to get a 50 MHz clock. When I choose "No ...
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2answers
106 views

if else statements

I am trying to understand how if else statements and clock work. My application accepts chars as input (), and for each char the application should go into the if else statement. Here the code: ...
2
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1answer
21 views

LPC1110 confusion about default system clock and uart baud rate

I'm trying to get acquainted with ARMs on example of LPC1110 device. And there is some confusion about selecting baud rate for UART. I suppose it is running at ...
6
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0answers
791 views

Why is there a need of external clock even though MCUs can provide timing? [duplicate]

Why is there a need sometimes for an external crystal, even though the MCU have an internal oscillator? To give you an example, the Atmega328P used in Arduino Uno has an internal 8Mhz internal ...
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1answer
105 views

Verilog: Slow Clock Geneator Module (1Hz from 50Mhz)

I wrote clock generator module, i dont know if it is true but the problem is in my reg module. The error is: ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is ...
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2answers
32 views

PCIe Data clocked refclk question

When only one clock is used in PCIe and let's assume the clock is connected to device A. How does device B transfer data to device A. Device B does not have a clock source.
0
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1answer
68 views

FT2232H with non-standard crystal

I'm making an interface board using FT2232H in sync mode with a small FPGA, and thought how everything could be much easier if I can just use FT2232H as my clock source. Unfortunately I need different ...
0
votes
1answer
37 views

Verilog: Using a counter module to switch outputs

So I'm pretty new to Verilog and am working on a 3 bit multiplier project that outputs the decimal solution of the multiplier to the 7 segment display on my fpga board. I'm having a problem with ...
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3answers
482 views

How does one get the common PC frequencies (33.33 MHz, 48.000 MHz) from 14.318 MHz?

I see that a lot ICs for PC use a single 14.318 MHz crystal oscillator (which is an NTSC standard frequency, so very widely available in terms of parts) to generate the clocks for PCI, USB, etc. ...
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0answers
51 views

Can't Get HSE to work with STM32L4-Discovery!

We are running the STM32CubeL4 demo firmware on the STM32L4-Discovery board: We are trying to leverage the demo "IddMeasurement" module to assess power consumption with an external 8 MHz 3.3V square ...
2
votes
2answers
332 views

How to overcome clock stretching on I2C

I have the clock stretching issue on my I2C line, attached is the below snapshot of it.. I have Kinetis K64 board communicating to MAX7304 port expander at 400Khz. Should I get the driver have the ...
0
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0answers
38 views

Built in clock for HC-05 bluetooth chip

I want to add bluetooth to a game controller. The controller has 3 connections I'm unsure about: Data clock, Data latch, and Serial data. From my understanding ...
0
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2answers
118 views

STM32F303RET's core is always halted after programming

I have an STM32F303RET MCU with Eclipse, Cross ARM GCC and HAL library environment. I am using an STM32F4Discovery board as SWD programmer. My problem is when I download the hex file to the MCU I got ...
3
votes
2answers
107 views

Error in this Countdown module? (Verilog)

My professor looked at this code for a good 10 minutes, but could not find the problem. So, I'm hoping a fresh pair of eyes will see something both of us missed. As always, I'll be grateful for any ...
2
votes
1answer
38 views

Reconize JK Flip-Flop operating edge: rising or falling?

This is a JK Flip-Flop image. Using this image is there a way to know if the output changes on raising or falling clock? In other words, is input data transferred to the outputs on the HIGH-to-LOW ...
2
votes
1answer
43 views

Absolute max voltage of Differential Signal

I am using IDT 85104 Buffer IC for clock distribution in my design. I need to give the clock output of this Buffer to a device @ 156.25 MHz. I have 2 doubts :- 1. In the parameter table of 85104, it ...
2
votes
1answer
50 views

Why is it difficult to develop wide-bandwidth analog-to-digital converters?

How is bandwidth of analog-to-digital converters constrained? In particular, why would sample-and-hold subcircuitry not be able to perform high-speed switching?
3
votes
2answers
51 views

Problem with connecting clock divider generated by CORE Generator to I2S design for Spartan 6

I'm trying to connect clock divider generated by CORE Generator to I2S receiver and I2S transmitter on Spartan 6. The PLL_BASE is connected via ODDR2 module, as adviced. Both receiver and transmitter ...
1
vote
1answer
60 views

JK flip-flop: What is the difference between clear and J=0, K=1, rising clock?

I'm trying to create a Program Counter using some JK flip-flops. I have two different way to do that: Use some 74LS73 (dual ...
1
vote
1answer
64 views

Need to implement a phase locked frequency converter from 32768Hz to 36000Hz. How would I go about it?

I am building a timecode-related application and need to generate a square-wave clock pulse of 36000 which is integer-dividable down to 24,25 and 30. My source clock is 32768Hz which does not divide ...
0
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0answers
29 views

Crystal Clock Oscillators - Output Load

I want to understand why on certain datasheets the output load of active crystal clock oscillators is given in pF (picofarads). For example take the datasheet of the XO53 clocksource. Here the ...
1
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0answers
68 views

Nordic Nrf51822. Where to get the clock source for external SPI Slave

I need to connect an external SPI device . Cannot figure out where do get the Clock source for Nrf51822. The datasheet says: "The GPIOs used for each SPI interface line can be chosen from any GPIO on ...
0
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1answer
68 views

Inverting a very fast clock signal

How can I generate a inverted signal of a 20MHz Clock signal synchronous to the original signal? (At least, very close to the original) With a typical HEX INVERTER the propagation delay is already ...
2
votes
0answers
36 views

Why create clk and clk NOT with 2 inverters instead of 1? [duplicate]

I see many circuits use this topology Why dont we use just only one inverter like this: Thanks very much!
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2answers
212 views

Divide by integer in VHDL

I need to divide an integer by an integer in one clock cycle. how should I do this? I have a function for it I found on the internet but it always returns one. ...
2
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2answers
243 views

Can I use a button in place of a clock crystal?

So basically, I'm wanting to finally get into electronics. A little while ago I bought a few MCP3008 chips and analog pressure sensors. I've been wanting to build an compressed air system with it. ...
19
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5answers
6k views

How do electronic devices keep track of time without power?

There's laptops, PCs, microcontrollers and a lot of other things that can be plugged out and plugged in without a battery. But how does the system clock still keep track of time without anything to ...