A digital signal that goes high and low at a specific frequency.

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2answers
53 views

Calculate jitter of oscillator from PPM

I found oscillators with from 10ppm up to 50ppm and more, but how I can calulate maximum jitter of this oscillators? With an online calculator I've found with 40Mhz and 50ppm this value: 2.500e-12s ...
0
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0answers
30 views

Strange outputs in Zedboard (sometimes)

I made a block in Vivado HLS to normalize some 512x512 pixel maps. These maps are read from the SD card into memory (and they are read correctly,I've confirmed) and then they are passed to my Vivado ...
0
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1answer
26 views

Change PL clock

I'm designing my project in Vivado and I had a WNS (Worst negative Slack) of -2.67 ns (my PL clock was 200Mhz). I had some problems when running my design since the results where good sometimes and ...
0
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2answers
65 views

How to trigger at both edges in VHDL?

In Verilog if we use always@(clock) we can trigger a module at both rising edge and falling edge. Is there any method to do the same in VHDL.
2
votes
2answers
112 views

Timer PIC16 not working.. is it my code?

I'm new here as an OP, but I have been visiting this site for years. This time, just looking at other problems hasn't helped me. Hence, I sign up and just ask! I'm creating a countdown timer with 30 ...
2
votes
1answer
105 views

Debounce Functional Clock on AM335

What is the purpose of Debounce Functional clock on AM335x processor? In the technical reference they say: "The de-bounce clock is used for the de-bouncing cells". What cells? I am little confused ...
1
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1answer
30 views

Shift registers, understanding parallel-in serial-out

I have the 74hc597 parallel-in serial-out (PISO) shift register. The datasheet can be found here. I have a general idea about how serial-in shift registers (SIPO) work, but I'm having trouble ...
17
votes
8answers
3k views

Why do Microcontrollers need a Clock

Why do instructions need to be processed at set time intervals (i.e. with the use of a clock)? Can't they be executed sequentially - immediately after the previous instruction has completed? An ...
1
vote
1answer
45 views

How do devices with different external clock communicate between each other on a motherboard?

I don't have any pratical knowledge about eletronic circuit. Actually I am a high level software programer and I've just begin to learning about computer hardware and eletronics. Basically, I ...
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0answers
26 views

Design timing Summary - Xilinx

(Working with a Zedboard) I made a design in Vivado HLS, selecting a period of 200Mhz. In the synthesis report I can see that the estimated clock is 5.24ns with an uncertainty of 0.63. I decided to ...
1
vote
2answers
32 views

Current sinking capability of HV507PG

I am new to this forum, heard you guys are great and helpful. I have been designing a nixie clock recently for my girlfriend's birthday. The tubes run at 170v and have a current rating of 2.5mA. I ...
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votes
1answer
80 views

NOP- clock cycles [closed]

In general, how we calculate number of clock cycles in one NOP.?? I need to implement delays in my code. Just wanted to implement delays using nop. Please advice.
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1answer
27 views

Verilog mux using a clock

I'm trying to get a simple piece of logic working: on the positive edge of the clock the output should always be 1, on the negative edge, the output should be the value of a provided input. I've ...
1
vote
3answers
160 views

Divide-by-3 with square output?

I'm thinking of making an 8MHz about-square clock starting from a 24MHz about-square clock. All signals are CMOS with 3.3V(±10%) power. What are my options? I'd like it low-power, cheap and easy to ...
0
votes
2answers
38 views

Eye diagram measurement of a CLK using an Oscilliscope

I'm still a junior engineer and wondering how to perform eye diagram measurement of a CLK using an Oscilliscope? My second question: Is the eye diagrams just using to measure CLKs, or one may also ...
0
votes
4answers
124 views

Generate an 40MHz Clock on an FPGA with 100Mhz clock

I'm trying to generate an 40MHz clock on an 100Mhz FPGA kind of strugle with the Verilog CODE, I rediredted the Clock to a pin to check the 100Mhz: ...
0
votes
1answer
35 views

What does Limit at Min to Max values in datasheet means?

I have doubt while implementing I/O SPI interface for the ADF4158 PLL Synthesizer. I planned to use a simple I/O model to send bytes (using only 3 bits for 3 lines) using RS232 at 115200 BPS. I didn't ...
1
vote
2answers
57 views

Why does the clock stay at high?

I'm very new and I'm trying to do an I2C trace of ADXL345 with Ch1 to SCL and Ch2 to SDA, but the traces look like these: Is the clock not supposed to oscillate continuously? Is it normal for it ...
0
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0answers
49 views

8-point FFT on FPGA using verilog

I have implemented 4-point FFT using xilinx software, for 8-point FFT, we have twiddle factors (1+0j) (0.707-0.707j) (0-1j) (-0.707-0.707j). when i give twiddle factor as 0.707 and simulate it in ...
0
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0answers
31 views

Variable frequency oscillator

How can I design a Variable frequency oscillator, in the range of 2-40 MHz? It must output a square or pulse wave (0-5V) and the frequency adjustable by a potentiometer. I tried this with a 555, ...
3
votes
1answer
77 views

Poor clock output from Spartan6 FPGA

I am using the LX9 Microboard from AVNET with the Spartan 6 PFPGA. I implement SPI to read from an ADC (ADS7822). I was getting wrong sampled values. When I ched the signals with an oscilloscope, it ...
2
votes
1answer
185 views

what happens to SPI clock in loop-back

I want to use SPI module in loop-back mode. so I wire MOSI to MISO. but how about the clock??. is it wired somewhere?? and how the clock works loop-back mode
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vote
2answers
73 views

Output clock of the LPC1768?

I am using NXP's LPC1768 development board and I came across the User Manual for this part and page 67/849 section 4.10 descusses the External Clock Output. I couldn't figure out which pin out of the ...
1
vote
2answers
32 views

SR Latch/Racing?

Following truth table resulted from the circuit below. SR(NOR) latch is used. I have tried several times to trace through the circuit to see how truth table values are produced but its not working. ...
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0answers
57 views

How does increasing core voltage increase the performance of the processor

Platform: Mobile Based on ARM Cortex A7 MP Core Observation: In a legacy code the author tries to increase the default voltage during boot time ...
0
votes
1answer
73 views

Clock distribution for low-jitter audio DAC

I am building a 10-channel audio DAC using 10 ES9018 converters and an ultra low phase noise clock (Pulsar) with femtosecond jitter. What would be the best way to distribute the clock's signal to the ...
0
votes
1answer
61 views

Clock doesn't seem to tick

I have been working on a program for class which acts as a stopwatch, but I've been having troubles where it doesn't work. (Only one digit, the first that would be shown on the four digit display is ...
-1
votes
1answer
43 views

Altera Clock + PLL

I am using an Altera devkit from terasic, DE0-CV. I am also new to the FPGA business. How to connect the onboard clock to the FPGA and use it with my design? As the clock is a 50 MHz one, surely I ...
1
vote
1answer
94 views

PIC 16F887 and the mysterious System Clock Select bit (SCS)

I'm using a PIC 16F887 and I'd like to use the internal oscillator HFINTOSC. To accomplish this, I set the IRCF 2:0 bits to 110 (4Mhz prescaler) and the FOSC 2:0 config bits to INTOSC. Now I should ...
1
vote
2answers
53 views

How to multiply base system clock using .xdc constraints in Vivado

This question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock ...
1
vote
1answer
50 views

It is better to have a negative clock skew?

Is it better to have a negative clock skew? Why? If we compare it with a positive clock skew, which is better?
1
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1answer
66 views

How to use an H-clock tree in a pipelined adder

This is for a lab at my university. Normally I don't have a problem with these things, but this one is poorly written and the professor hasn't discussed the H-clock tree, which is where I'm getting ...
3
votes
1answer
186 views

What parts could be labeled XT and be near a Clock of a microcontroller

An ice cube maker stopped working with the symptom that the temperature cycles are getting shorter and shorter. I suspect that the microcontrollers clock is not working properly. I desoldered a part ...
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0answers
50 views

VHDL - does sequential component need to know whether input comes from clock?

If I have some component that represents a sequential circuit (or sub-circuit), e.g. an SR-latch within a D flip-flop, do I need to know which inputs are clock-based? Often sequential components seem ...
0
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0answers
34 views

Clock distribution among multiple cores in an arm based SOC

I have a general doubt of how clock is distributed among cores in ARM based SOC, for example take an ARM Cortex A7 MPCore based SOC the soc i was looking at is based on above core and is a quad core ...
0
votes
3answers
62 views

How to get equal number of clock cycles before ISR on an AVR

While writing a time critical piece of code for an Attiny13, I figured I could use the rising edge of an input as a trigger to read in some self clocking data. However, the number of clock cycles ...
0
votes
1answer
32 views

cmos output buffer currents

In a cmos driver what controls the amount of current it can source or sink? Is it the combined RDS on of the internal FETs? When you try to pull a line low I guess there's voltage stored in the ...
1
vote
1answer
85 views

Can I use an AND gate before a clock input?

Can I use an AND gate with a clock input? For example, in the picture below, I have a positive-edge D flip-flop. I'm using an AND gate with the Select_chip input and the Clock input but I'm not sure ...
0
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0answers
62 views

Using two 4-bit registers, AND and OR gates and inverters, what would be a one bit slice of the logic diagram that implements all of the following?

C0: R2 <- 0 (clear R2 synchronously with the clock) C1: R2 <- R2' (complement R2) C2: R2 <- R1 (transfer R1 to R2) The control variables C0, C1, C2, ...
0
votes
2answers
79 views

1/6 Clock Frequency Divider

How would I design a circuit made of rising edge triggered flip flops and inverters to make its output 1/6 of the clock frequency. Cheers
0
votes
0answers
28 views

How to use external clock on STM32F205VC?

I'm using VisualGDB for stm32F205VC programming. I have an external clock on my board connected to OSC_IN and OSC_OUT that I have to use. How to switch to it?
0
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0answers
37 views

How the clock runs on modern processors? [duplicate]

I would like to understand how the clock in modern processors. It is delivered via hardware or via software? I understand how the clock works of a microcontroller with an external crystal or even ...
0
votes
2answers
123 views

Numerically Controlled Oscillator (NCO) Sample quantity

Ive been doing some research on NCOs and some initial information (or lack of information) is bugging me. Ive read a few articles on this topic: FPGA based NCO Blog on NCOs But i still don't ...
2
votes
1answer
44 views

Clock switching hangs when switching back to original source

I am currently working on a project where the clock needs switching between the Primary Oscillator with PLL (POSCPLL) to the FRC and back again. I have initialised the Clock as the PRIPLL by using ...
0
votes
0answers
35 views

Clipped sine input for HSE clock input on STM32F303?

I am using a STM32F303 and need a very high stability clock ie around 1ppm over temperature. One of the modules I am looking at outputs what is described as "clipped sine". Can this drive the ...
1
vote
3answers
81 views

Adjustable Clock Generator between 15.5 MHz and 17.4 MHz

I'm looking for an inexpensive component to generate frequencies between 15.5 MHz and 17.5 MHz. My intention is a medium-run product (a few hundred units). The issue is that I would like to change ...
4
votes
5answers
1k views

What components or circuitry exist that can provide extremely high speed, accurate clocks?

I've been curious for awhile now about doing some high speed projects, such as measuring time differences of radio wave reception, and was wondering if there exists components that provide clocks much ...
0
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1answer
46 views

JK flip-flop and sequence network

State diagram of the sequence network S looks like the following for a jk flip-flop: Is this the right truth table for it? ...
0
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0answers
31 views

How to choose clock frequency in Dynamic Logic?

I want to design a full adder using dynamic logic but I don't know how to choose the frequency of operation. I know the following about dynamic logic clock: The clock frequency is crucial for ...