A digital signal that goes high and low at a specific frequency.

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External low-power clock design review

I am designing an outdoor wireless sensor node using an ATtiny861a MCU that will be operating at 1.8Volts. I am basing my work off of a previous sensor node that used a LTC6930 silicon oscillator ...
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4answers
87 views

Generate an 40MHz Clock on an FPGA with 100Mhz clock

I'm trying to generate an 40MHz clock on an 100Mhz FPGA kind of strugle with the Verilog CODE, I rediredted the Clock to a pin to check the 100Mhz: ...
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1answer
29 views

What does Limit at Min to Max values in datasheet means?

I have doubt while implementing I/O SPI interface for the ADF4158 PLL Synthesizer. I planned to use a simple I/O model to send bytes (using only 3 bits for 3 lines) using RS232 at 115200 BPS. I didn't ...
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2answers
44 views

Why does the clock stay at high?

I'm very new and I'm trying to do an I2C trace of ADXL345 with Ch1 to SCL and Ch2 to SDA, but the traces look like these: Is the clock not supposed to oscillate continuously? Is it normal for it ...
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38 views

8-point FFT on FPGA using verilog

I have implemented 4-point FFT using xilinx software, for 8-point FFT, we have twiddle factors (1+0j) (0.707-0.707j) (0-1j) (-0.707-0.707j). when i give twiddle factor as 0.707 and simulate it in ...
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28 views

Variable frequency oscillator

How can I design a Variable frequency oscillator, in the range of 2-40 MHz? It must output a square or pulse wave (0-5V) and the frequency adjustable by a potentiometer. I tried this with a 555, ...
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1answer
68 views

Poor clock output from Spartan6 FPGA

I am using the LX9 Microboard from AVNET with the Spartan 6 PFPGA. I implement SPI to read from an ADC (ADS7822). I was getting wrong sampled values. When I ched the signals with an oscilloscope, it ...
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1answer
173 views

what happens to SPI clock in loop-back

I want to use SPI module in loop-back mode. so I wire MOSI to MISO. but how about the clock??. is it wired somewhere?? and how the clock works loop-back mode
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2answers
54 views

Output clock of the LPC1768?

I am using NXP's LPC1768 development board and I came across the User Manual for this part and page 67/849 section 4.10 descusses the External Clock Output. I couldn't figure out which pin out of the ...
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2answers
27 views

SR Latch/Racing?

Following truth table resulted from the circuit below. SR(NOR) latch is used. I have tried several times to trace through the circuit to see how truth table values are produced but its not working. ...
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43 views

How does increasing core voltage increase the performance of the processor

Platform: Mobile Based on ARM Cortex A7 MP Core Observation: In a legacy code the author tries to increase the default voltage during boot time ...
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1answer
51 views

Clock distribution for low-jitter audio DAC

I am building a 10-channel audio DAC using 10 ES9018 converters and an ultra low phase noise clock (Pulsar) with femtosecond jitter. What would be the best way to distribute the clock's signal to the ...
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1answer
57 views

Clock doesn't seem to tick

I have been working on a program for class which acts as a stopwatch, but I've been having troubles where it doesn't work. (Only one digit, the first that would be shown on the four digit display is ...
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1answer
38 views

Altera Clock + PLL

I am using an Altera devkit from terasic, DE0-CV. I am also new to the FPGA business. How to connect the onboard clock to the FPGA and use it with my design? As the clock is a 50 MHz one, surely I ...
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1answer
66 views

PIC 16F887 and the mysterious System Clock Select bit (SCS)

I'm using a PIC 16F887 and I'd like to use the internal oscillator HFINTOSC. To accomplish this, I set the IRCF 2:0 bits to 110 (4Mhz prescaler) and the FOSC 2:0 config bits to INTOSC. Now I should ...
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2answers
37 views

How to multiply base system clock using .xdc constraints in Vivado

This question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock ...
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1answer
49 views

It is better to have a negative clock skew?

Is it better to have a negative clock skew? Why? If we compare it with a positive clock skew, which is better?
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1answer
47 views

How to use an H-clock tree in a pipelined adder

This is for a lab at my university. Normally I don't have a problem with these things, but this one is poorly written and the professor hasn't discussed the H-clock tree, which is where I'm getting ...
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1answer
183 views

What parts could be labeled XT and be near a Clock of a microcontroller

An ice cube maker stopped working with the symptom that the temperature cycles are getting shorter and shorter. I suspect that the microcontrollers clock is not working properly. I desoldered a part ...
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44 views

VHDL - does sequential component need to know whether input comes from clock?

If I have some component that represents a sequential circuit (or sub-circuit), e.g. an SR-latch within a D flip-flop, do I need to know which inputs are clock-based? Often sequential components seem ...
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0answers
25 views

Clock distribution among multiple cores in an arm based SOC

I have a general doubt of how clock is distributed among cores in ARM based SOC, for example take an ARM Cortex A7 MPCore based SOC the soc i was looking at is based on above core and is a quad core ...
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3answers
62 views

How to get equal number of clock cycles before ISR on an AVR

While writing a time critical piece of code for an Attiny13, I figured I could use the rising edge of an input as a trigger to read in some self clocking data. However, the number of clock cycles ...
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1answer
27 views

cmos output buffer currents

In a cmos driver what controls the amount of current it can source or sink? Is it the combined RDS on of the internal FETs? When you try to pull a line low I guess there's voltage stored in the ...
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1answer
75 views

Can I use an AND gate before a clock input?

Can I use an AND gate with a clock input? For example, in the picture below, I have a positive-edge D flip-flop. I'm using an AND gate with the Select_chip input and the Clock input but I'm not sure ...
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38 views

Using two 4-bit registers, AND and OR gates and inverters, what would be a one bit slice of the logic diagram that implements all of the following?

C0: R2 <- 0 (clear R2 synchronously with the clock) C1: R2 <- R2' (complement R2) C2: R2 <- R1 (transfer R1 to R2) The control variables C0, C1, C2, ...
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69 views

1/6 Clock Frequency Divider

How would I design a circuit made of rising edge triggered flip flops and inverters to make its output 1/6 of the clock frequency. Cheers
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28 views

How to use external clock on STM32F205VC?

I'm using VisualGDB for stm32F205VC programming. I have an external clock on my board connected to OSC_IN and OSC_OUT that I have to use. How to switch to it?
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37 views

How the clock runs on modern processors? [duplicate]

I would like to understand how the clock in modern processors. It is delivered via hardware or via software? I understand how the clock works of a microcontroller with an external crystal or even ...
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2answers
105 views

Numerically Controlled Oscillator (NCO) Sample quantity

Ive been doing some research on NCOs and some initial information (or lack of information) is bugging me. Ive read a few articles on this topic: FPGA based NCO Blog on NCOs But i still don't ...
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1answer
34 views

Clock switching hangs when switching back to original source

MIGRATED TO EE.SE http://electronics.stackexchange.com/q/159634/69868 I am currently working on a project where the clock needs switching between the Primary Oscillator with PLL (POSCPLL) to the FRC ...
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29 views

Clipped sine input for HSE clock input on STM32F303?

I am using a STM32F303 and need a very high stability clock ie around 1ppm over temperature. One of the modules I am looking at outputs what is described as "clipped sine". Can this drive the ...
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3answers
76 views

Adjustable Clock Generator between 15.5 MHz and 17.4 MHz

I'm looking for an inexpensive component to generate frequencies between 15.5 MHz and 17.5 MHz. My intention is a medium-run product (a few hundred units). The issue is that I would like to change ...
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5answers
1k views

What components or circuitry exist that can provide extremely high speed, accurate clocks?

I've been curious for awhile now about doing some high speed projects, such as measuring time differences of radio wave reception, and was wondering if there exists components that provide clocks much ...
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1answer
44 views

JK flip-flop and sequence network

State diagram of the sequence network S looks like the following for a jk flip-flop: Is this the right truth table for it? ...
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0answers
27 views

How to choose clock frequency in Dynamic Logic?

I want to design a full adder using dynamic logic but I don't know how to choose the frequency of operation. I know the following about dynamic logic clock: The clock frequency is crucial for ...
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2answers
309 views

How to check frequency of MSP430 clock?

I'm working on a project in which an MSP430 is used to provide the timing for some stuff where accurate timing is important (it can be off by 10%, but not by 2x). This is driven by the timer A0 ...
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1answer
43 views

External clocking of MSP430 with variable duty cycle clock

I'm going to clock an MSP430FR5969 using a PCF2127 RTC. The PCF2127 can output 32.768kHz at a duty cycle between 40%-60% and 16.384kHz, 8.192kHz, etc at exactly 50%. I will use the MSP's DCO system to ...
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65 views

ENC28J60 on a XMega along with USB

I'm trying to port the TuxGraphics webserver example to the ATxmega128A3U for the ENC28J60 This is my first time using the xmega so I need help making sure all my SPI registers are set correctly and ...
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2answers
90 views

XMega Get Clock Speed

I'm doing some debugging on my project and I need to check if I'm setting my external crystal correctly. I have the ability to print out to a serial monitor via usb, is it possible to retrieve the ...
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68 views

Mueller Muller CDR

For a clock data recovery in a reciever a phase detector is used. In my case I want to understand how the Mueller Muller CDR works. And also what its advantages and disadvantages are. The ...
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1answer
902 views

Clock divider circuit with flip D flip flop

I am using D flip flops in my clock divider circuit. I have started with one FF and moving up with the number of divisions I want to have in my clock. This is how I want my D ffs to work. Now I ...
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1answer
55 views

AMBA Bus Architecture and its clocks

I Have Few Doubts on AMBA Bus Architecture and its clocks I am working on Propriety SOC with non-detailed docs , the SOC is based on ARM9 Architecture which has peripherals connected to it through ...
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1answer
139 views

ATmega162 fuses to select external clock 12Mhz?

Could anyone tell me how I could change the fuse bit, so that my ATmega162 uses 12 MHz external crystal. Once, I made the changes in the AVR fuses wrong the AVR went dead. That is why I need ...
2
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1answer
104 views

How can two separate devices send clock data to a shift register IC?

I'm using a microcontroller to clock a byte into a 74HC595 shift register and latch it. It then sends a signal to the other device which send 8 clock pulses when it is ready to receive the byte. So ...
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1answer
35 views

clock drivers low current consumption

I am trying to drive a 30 pF load cap (1 pF times 30 or 2pF times 15 or so on) from a ring oscillator generated clock. The frequency I want is 250 Mhz. What is the best approach to keep the input ...
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2answers
68 views

Why prescaler doesn't give 50% duty cycle pulse

I am new to embedded electronics. While reading the datasheet of ATmega328P, I saw this when timers and their timing diagrams were given... I wonder why clk/8 is not of 50% duty cycle...Please help ...
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1answer
200 views

Help for Changing the ATMega328's clock source to External Clock

I want to change the fuse bits of the ATMega328 to operate with external clock (function/signal generator) instead of the crystal. The clock speed will be 8MHz. I have been trying for months and all ...
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2answers
118 views

Acquiring an accurate clock input for my computer

Building a timegrapher is quite straightforward, it is nothing more than a piezo transducer connected through to an amplifier. However, in order to actually utilize the results, one need an accurate ...
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1answer
35 views

150 MHz LVPECL Clock

I am using a SAS expander IC. In the datasheet, it is given to use a 150 MHz LVPECL clock with specifications as attached in the snapshot. Can somebody please explain how to use common mode & ...