I recently completed a PCI-E Gen 1.0 line card design. The line card consisted of 4 Spartan 6 FPGAs sharing one PCIE reference clock. Early on in the design there was a decision to solely use the PCIE ...
I am working with an FPGA that does 10Gb ethernet. As I understand, at the PHY level the clock frequency is 322.265625 MHz for a 32 bit wide bus, but at the MAC level, the clock frequency is 156.25 ...
This is regarding a design choice involving LAN8720, specific to clocking schemes. We are interfacing an ARM cortex M4 (with inbuilt MAC) to the 8720 PHY via RMII in the REFCLKO configuration. In the ...
I'm trying to evaluate the quality of an 8b/10b encoded data stream (Gigabit Ethernet, 1.25 gigabits/sec). Without doing clock recovery from the data stream, I want to measure jitter (et al) with a ...