"Complementary Metal-Oxide Semiconductor" is a circuit topology which uses a combination of PMOS and NMOS transistors to create logic gates. Most current digital logic is implemented as CMOS.

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What sets the source voltage in this simple CMOS circuit if the current source is 0A?

In the circuit below, what sets the voltage at the source of the NMOS if the current source is set to 0A? simulate this circuit – Schematic created using CircuitLab If I run the circuit ...
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Using OA Layout Designs on Tanner L-Edit

I am facing difficulty opening OA designs in the L-edit of Tanner. I have a design kit that has folders for the L-edit for NMOS and PMOS designs that I am trying to open.The instructions in the user ...
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4answers
807 views

Can a NOT gate be used to achieve 180 degree phase shift?

I have seen from various sources which say that a NOT gate cannot be used to achieve an 180-degree phase shift. Is this claim true? Edit: The question is definitely sounding unclear because that is ...
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970 views

Why is a capacitor used to protect CMOS chips? [duplicate]

I am studying digital electronics. A book says that "use a 0.1 μF capacitor between Vcc and ground for each IC". What does this mean? Why can a capacitor protect CMOS chips? Does it mean that a ...
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45 views

RF/voltage clamp/limiter [closed]

I'm looking for a circuit that is called "RF clamp", "RF limiter", "voltage clamp" or "voltage limiter". The example of such circuit is a transistor Q on this picture: However, what I need is a ...
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48 views

How to get a CMOS transistor SPICE model?

So far in order to simulate CMOS circuits I relied on a library that I had to randomly download from Internet such as this one: http://ecee.colorado.edu/~ecen4827/spice/ltspice/5827_035.lib Inside ...
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1answer
20 views

What is AO222 based design in concept of design of CMOS cell library?

I am reading a paper "Static Implementation of QDI Asynchronous Primitives" by P. Maurine, J.B. Rigaud, F. Bouesse, G. Sicard, and M. Renaudin. They designed a cell library using AO222 gate, What is ...
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16 views

How to accomplish parameterized subcircuits in LTSpice?

I am trying to play around with beta ratio effect of CMOS inverter. To do so I need to have parameterized subcircuit so I can adjust the ratio of PMOS beta over NMOS beta and achieve HI-skewed or LO-...
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1answer
47 views

CMOS Gates, I can't understand when we use those negation bubbles

I began to study CMOS gates, that are in my teacher's book, and I have 2 questions, because there is no explanation. If we use NAND or NOR , it means we have F = ~(A*B) and F = ~(A+B) and is normal ...
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54 views

Dual edge triggered D flip flip CMOS implementation. Less than 20 transistor

I need to implement a dual edge triggered D flip flop (DET) in a CMOS IC using 0.35u technology. The best design which I could fine is this one http://ieeexplore.ieee.org/xpl/login.jsp?tp=&...
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1answer
32 views

Should I use NMOS or PMOS in CMOS demultiplexer circuit?

I am trying to design a simple 1:2 demultiplexer. I have two question here. First, is the following design right?: (simulation shows that it is working) in_D is the input data line, in_S is the ...
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33 views

LTSpice error message: Multiple instances of “M:XX:XX:XX:1”

This is driving me nuts. I am trying to simulate some fundamental digital gates in transistor level using LTSpice. Each component is defined in a separate sub-circuit. Sometimes when I put a sub-...
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2answers
78 views

Why is there a resistor in a cmos X-OR gate?

While reading up on logic gates i came across this image on Wikipedia: According to the article, the resistor on the supply voltage for the inverter is necessary to ensure that no current is leaked ...
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1answer
93 views

Raspberry 3.3 V to 5 V level conversion at 5MHz

I have a Raspberry Pi 2 to handle my cards. I need to convert 3.3 V GPIO of Raspberry to 5 V for my cards. Actually I use CD4050 (Non-Inverting Buffer) to convert 3.3 V to 5 V. I have mesaured ...
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3answers
76 views

How do you design a CMOS buffer with exact same delay of a CMOS inverter?

Everyone knows that a CMOS inverter is simply a PMOS connected to an NMOS. There are situations in asynchronous design that we need to compensate for the inverter propagation delay in a parallel ...
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1answer
51 views

What is the difference between sCMOS and CMOS?

I am interested in microscopy applications, and am looking at both sCMOS and CMOS sensors as options. Why are sCMOS sensors so expensive compared to CMOS sensors? What are the benefits, and are they ...
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1answer
37 views

Startup circuit 0 current mode

I was designing the start up circuit for one of my circuits as shown in the figure below . I was able to understand how a start up works clearly but I stil havent figured out how exactly the 0 current ...
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2answers
23 views

Which CMOS SPICE model should I choose?

I need to simulate digital circuits which have custom gates. For now I am not concerned about the specific CMOS technology, the transistor Length and Width, etc. I only need to glue NMOS and PMOS ...
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1answer
61 views

What To Do With Unused TTL and CMOS Outputs

Just about everything I've read on the Web, including on this site, say that unused TTL and CMOS outputs should be left floating. However, this TI article, Designing with Logic, states "Unused ...
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1answer
99 views

How to increase fanout of CMOS buffer

I'm new to online forum. I want to interface 74HC541(Buffer) to 74HC574(D-f/f). The thing is 100's of D-f/f parallel interface as shown in figure(Fig.1). Input and load capacitance limits it to 10 to ...
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3answers
230 views

What is a weak transistor?

In implementation section of C-element at Wikipedia website: https://en.wikipedia.org/wiki/C-element there is a diagram that points to a weak transistor. What is a weak transistor? Below is the ...
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63 views

Transistor level design of flip flops - Is the complementary clock necessary?

Below is one of many different ways to design a Master Slave D Flip Flop. simulate this circuit – Schematic created using CircuitLab Of course a lot of details are glossed over, ...
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PMOS carrying more current than NMOS?

I dont know what is happening here. Both PMOS and NMOS have W=100*270nm L=180nm Vgs=1.8v vds=1.8v while NMOS is carrying only 14.19mA current, How can PMOS carry 15.97mA for the same size and ...
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41 views

CMOS 4000 series postfix meaning: BCL, BCP, BD

I am simulating a digital circuit and I need to use a CMOS inverter 4009. There are three of them with different postfixes: 4009BCL 4009BCP 4009BD What are the differences between BCL and BCP and ...
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54 views

Level shifting in HV CMOS processes

I'm working on a project for which custom ICs are being designed by another person on the project. The process being used is a mixed voltage CMOS process which uses a \$1.8\mathrm{V}/5\mathrm{V}\$ ...
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42 views

How are the circuits and design considerations for opamps and comparators different, at an integrated transistor level?

I've designed various transconductance and operational amplifiers in CMOS technologies in the past. I've also worked with clocked latching comparators. However, I've yet to design an asynchronous ...
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2answers
60 views

How to size CMOS transistors

I am new to CMOS technology and I am trying to learn about CMOS logic gates. I have a problem with transistors sizing. As far as I could understand the main idea is to obtain equal rise and fall times....
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1answer
46 views

Design of the two stage amplifier with p-type input

I have to design the two stage amplifier with p-type input (p-type diff pair), the schematic bellow: However, mostly tutorials discuss the same architecture but with n-type input. My main ...
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45 views

Minimum delay path and sizing of CMOS gates

I've been wracking my brain for the past 3 hours trying to figure this one out, and all the examples I've seen just slap an answer on there like it's supposed to be obvious, which I can't for the ...
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1answer
48 views

CMOS on breadboard - Which P & N type MOSFETs to get started?

I would like to implement my own CMOS logic on a breadboard. I have already designed a simple PCB with basic logical functionality but now I'm stuck on the choice of N & P Type transistors (...
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42 views

CMOS logic gate output

What happens to Voh and Ioh when the number of loads connected to the output of this logic gate increases? My interpretation is: the increase in number of loads decreases the equivalent impedance, ...
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44 views

How do I use the CD4026 IC with a multiplexed 7-segment display?

I have 2 pcs. of 3 digit multiplexed 7-seg display (ELT-511SURWA) and 6 pcs of CD3026. I am building a frequency counter (CD4060 + crystal as timebase). I have considered using 6x UDN2983 + CD4017 + ...
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37 views

How to get the same output signal but with an increased capacitive load?

I'm designing a CMOS circuit of a VCO and it works perfectly fine when tested independently. Now when I cascade an other block like a divider to it, the output isn't the same as before. Rather its ...
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2answers
75 views

MOSFET as a VCCS or an variable resistance

I am a bit confused. In saturation region, sometimes, an MOSFET is called voltage-controlled current source and sometimes it is called variable resistor where its resistance is controlled by the gate-...
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1answer
45 views

Solid State Relay from CMOS pin

I want to operate the LCC110 solid state relay from a 5V CMOS output pin on the PGA2505. I can see that I will likely need 8mA to drive the relay. However, I don't see on the PGA2505 datasheet if it ...
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1answer
59 views

DIL IC for simple non-volatile memory [closed]

Can anyone suggest a DIL IC where I can store a couple bits of memory without having to use a complicated interface like serial, I2C, and etc. I want to be able to store at least 2 bits of memory to ...
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1answer
27 views

M48Z02 (16Kbit ZEROPOWER SRAM) is TTL compatible?

I've some problem using together TLL and CMOS integrated. I'm developing a project and only now I discovered that the two standards can create troubles together. So I decided to use only TTL chips. ...
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2answers
44 views

Bredboard compatible FAST TTL [duplicate]

I have been looking for 16-bit ICs for a project i`m working on. The project is to build a 16-bit computer from scratch, therefor i decided i nedded cgips that could handle high clock-frequensies. ...
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1answer
67 views

Input resistance of differential LNA

This is a wideband differential LNA. I am trying to calculate the input resistance of this circuit but the result is not anything similar to the result shown in the picture below. Could you explain ...
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2answers
665 views

CMOS and gate implementation

As far as I am aware, this is an incorrect implementation of an AND gate, as when out is logic high, the two N-type FET transistors will go to an open state, leaving it floating. I am doubting my ...
5
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1answer
177 views

CMOS transistors for educational purposes

I am currently teaching my daughters Digital Electronics, ages 9 and 12. In doing so, I wanted to introduce them to CMOS logic, since I feel that a hands-on approach is always better than just doing ...
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1answer
33 views

How diffusion constant vary with temperature in Semiconductors?

Diffusion constant = Mobility*Thermal Voltage *Where,Thermal voltage = T/11600* From above equation it is clear that Diffusion constant should ...
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1answer
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What is Minority Carrier Storage Time?

I know that Minority Carrier Life-Time is the time difference Between generation of minority carrier & their Recombination. I am bit Confused Between Minority Carrier Storage Time & Minority ...
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1answer
154 views

Push pull CMOS output stage overcoming the distortion problem

I implemented the simple push pull source follower and I understand that it has this distortion problem. That is between -|VTP| ≤ Vin ≤ VTN there is no output because the output terminal floats since ...
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1answer
28 views

Why diffusions in CMOS CAD tool (Magic) is continuous

I am using Magic to draw some transistors and create digital logic gates. While I was studying the theory about MOSFET I've always seen images like the one below. In this picture, one can see that ...
2
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4answers
132 views

Digital Circuit to Check for Majority

I have 31 digital inputs (each is high or low) and want one digital output which is high only if at least 16 inputs are high. How can I implement this "majority" function (which is also the most ...
3
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3answers
323 views

What is the maximum allowable load capacitance for 74HC04?

Does anybody know the maximum allowable load capacitance for 74HC04? In the datasheet, nothing is mentioned in the "Limiting values" section. Some of the dynamic characteristics are given for a load ...
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1answer
85 views

NMOS/PMOS logic vs. CMOS logic

With PMOS and NMOS, one can deduce that it is off, if Vgs < Vt (NMOS) || Vsg < Vt (PMOS) id = 0. Now my question rests on the dependency of these conditions. I know proving condition 1 ...
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77 views

Cross coupled-gm boosting stage

From this paper, a wideband differential LNA is proposed with structure below: The first stage is called "cross coupled- gm boosting stage". I am wondering if there is a mistake here. As seen from ...
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1answer
35 views

Beta Multiplier - Not Getting Correct Reference Current

Solved: The body of M2 needs to be connected to ground and not to source. I am reading a textbook on CMOS technology and I am having trouble simulating a beta multiplier in NGSPICE. The reference ...