CMOS stands for Complementary MOS, most digital logic is made in CMOS.

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Cabling simple sensors 5-20 ft from a uC - tips and gotchas; UTP vs STP cables

The situation: using a simple microcontroller (eg: 5V Arduino Pro Micro) which needs to read a few sensors located about 5 to 20 feet away via cables. (This is a garage/storage area controller). The ...
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29 views

How does this voltage detector IC work in a circuit? What does open drain vs. CMOS output mean?

I'm evaluating the Rohm BD48/BD49 series voltage detector. I'm having trouble understanding the data sheet. I want to generate a high signal when the input voltage is above a desired threshold (3.0 ...
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75 views

CMOS OR gate using 4 Transistors

Can an OR gate be implemented using 4 CMOS transistors? The circuit would have two n-type transistors in parallel in the pull-up network, and two p-type transistors in series for the pull-down ...
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39 views

cmos inverter in voltage regulation

How does a CMOS Inverter drives the gate of MOSFET for voltage regulation? I have attached the image for clarification. I just want someone to explain me why two cmos inverters are connected to the ...
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71 views

Determine the Number of Transistors Needed to Build CMOS circuit

I would like to determine the number of transistors that will be used in the CMOS circuit below. Is there a specific formula for it?
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106 views

CD4050 Voltage leaks, what can I be doing wrong?

As often as I see the CD4050 used as a logic level converter, I'm surprised that I haven't heard much about how it seems to leak voltage from the inputs into Vdd. I hope this isn't a case where the ...
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39 views

Electret Mic Capsule to Piezoelectric Disk

I'm working on a project that involves creating units/cells that "listen" and "talk" to each other. The principle being the circuitry I've tried is to use an Electret MIC Capsule to pick up sound, ...
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68 views

How to construct CMOS equivalent of an XNOR gate using AND, OR, NOT gates?

I am new to digital logic and I am confused hot to construct CMOS equivalent for XNOR gate using AND, OR, and NOT gates. I found XNOR circuit implemented with gates. And what I did is I plugged CMOS ...
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28 views

Comparison of 180nm and 65nm CMOS technology in consideration of delay, power and energy consumption

how would each of them typically compare with respect to delay, power and energy consumption? (Used in digital circuits)
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75 views

Replacing resistors with active load in active filter

I am building a low pass filter IC in 0.25 micron CMOS. My design requires 14 Mega-Ohm resistors. I want to replace them with an active load in order to save space. If possible I would like to use a ...
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42 views

Choosing R when designing CMOS Amplifier

I am trying to design a two stage amp like the one pictured above. I want the overall small-signal gain, |Av| = vo / vid = 240 V/V = (47.6 dB). I know in theory how to achieve this but am having ...
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70 views

Is there relation between logic chip names and their internal structure

I know that for instance an ATMega328 is a 8 bit MCU with 32k of program space, the same can be said for most other MCUs and some other ICs with a direct relation between the name and internal specs. ...
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71 views

Transistor count in NAND or NOR implementation of boolean algebra?

I have a complex output function in boolean algebra ( Where '~' means NOT): F=~( (a c ~d) + (a ~c ~d) + (~a c) + (~ a c d) + (a c ! d b) ) I know this can be simplified down to: F = (~a ~c) + (a d) ...
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26 views

How to open recent schmatic on Tanner Eda Tools v13.0

This is my first time working with Tanner Eda Tools. I designed the circuit and then I saved the T-spice and S-edit and exported the PDFs successfully. My first problem is that I couldn't open my ...
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1answer
40 views

Howto convert “0=floating / 1=Vcc” to CMOS compatible “0=ground / 1=Vcc” signal

I'm playing around with CMOS logic using CD#### dip packages. As far I understand input pins should never be left floating, always connect them to Vcc or ground. Unfortunately my digital source ...
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52 views

Applying euler path to CMOS schematic with inverter

I've discovered that tracing the Euler path of a CMOS schematic can aid in creating compact stick diagrams. I have an issue, though. Of all the lectures I've read on the net, the pull-up and ...
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232 views

Simplifying CMOS schematic to reduce number of transistors

I know the basics in creating a schematic in CMOS, wherein in a(n inverted) boolean expression, if there is a: NOR - NMOS should be in parallel, PMOS in series; NAND - NMOS in series, PMOS in ...
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44 views

Why TTL logic gates are faster when compared to CMOS logic gates? [duplicate]

In TTL families resistors are used and number of stages between input and output terminals is comparatively high. Still operation speed of TTL is better than CMOS. Why?
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240 views

Understanding the Texas Instruments CD4075 datasheet table

I downloaded the CD4075 IC datasheet and I'm having trouble understanding the lines labelled "Output High (Source) Current" in the table below. The table shows current values relative to temperature ...
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57 views

adjust clock frequency using Timing Error Avoidance Technique

I am following the next example as is depicted on the diagram, in order to adjust the clock frequency of a multiplier to its maximum. The System works as follows: The flip-flop at the input to the ...
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1answer
58 views

Improving my impulse counter circuit

I just started studying electrical engineering this semester, and I'm currently working on following impulse counter: The circuit is basically a power supply regulated to 5V, a pendulum acting as ...
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1answer
57 views

falling delay inverters VLSI CMOS

How do I obtain the falling delay driving by signal A: Data: ...
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27 views

CMOS transmission gate transients

I have a question on transients in transmission gates. I've seen in a couple textbooks that the basic model is an RC circuit with a switch controlled by the control signal, and that the equivalent ...
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Do logic families use different type of transistors?

Do the logic families such as TTL and CMOS represent only different logical structure? Or do they also use different type of transistors? Latest microprocessor chips with millions of components use ...
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Precise differences between DRAM and CMOS processes

There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture: Why do microcontrollers have so little RAM? How do they integrate logic into a DRAM ...
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114 views

An Explanation of CMOS Logic

While trying to understand CMOS Logic on Wikipedia for class, I came upon this paragraph which I can't quite wrap my head around on the duality of CMOS: "An important characteristic of a CMOS ...
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78 views

Switch Vcc to Ground with a control bit

I have a device that is 1 ohm and it consumes 3Amp. I want to run my device in both ways and I have only one voltage supply. I want to switch ground to Vcc and vice versa with a control bit from mcu. ...
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56 views

CMOS vs LVDS oscillator

I am trying to select a 160MHz clock oscillator for my FPGA. The least expensive I found was either LVDS or LVPECL type for this frequency. I used a CMOS type before, so the output of the oscillator ...
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44 views

Online resource for lithography/micro fabrication [closed]

I am looking for good compiled resources on microfabrication (photolithography, ion etch, etc) for making integrated circuits. Some background: I do some work in a cleanroom user facility making ...
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66 views

Simulation to find worst-case delay path

Assume there is a combinational logic function implemented by a CMOS logic inside (1 Pull Up network and 1 Pull Down network). From the intuition of RC Tree elmore delay analysis, we know that input ...
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70 views

Question about CMOS Inverter Oscillator

Using CMOS inverter with crystal and cpacitors, we can make a oscillator. And i find many docs mention the method 'negative resistance'. But, they are not all the same. The method from TI's doc: Use ...
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266 views

How can PMOS eliminate body effect but NMOS doesn't?

I have a question on the body effect of MOS transistor. In particular, how does the body effect in PMOS be eliminated (by connecting bulk to source together) while this similar technique doesn't do ...
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107 views

NMOS transistor: how does its structure relate to two interconnecting diode?

There is a popular idea that structure of NMOS transistor could be viewed as the inter-connecting diode across their PN junction. Therefore, when operating NMOS, you always want to keep the Source and ...
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CMOS gate logic switching time based on input vectors

My question is regarding CMOS logic gates switching time based on input. Say I have a NAND gate and my input vectors are: 00 | 1 01 | 1 11 | 0 10 | 1 So, the ...
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CMOS inverter with feedback

In some circuits such as crystal oscillators, there is a CMOS inverter with a feedback resistor, they all simply say the resistor bias the 'amplifier' and force it to operate in the linear region, ...
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Preference of MOS resistor as load in MOS inverter [closed]

Whys is a MOS resistor preferred over diffused resistor as load in design of a MOS inverter?
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72 views

NMOS: what exactly forms the inversion layer

I have a a question on forming of the inversion layer in NMOS. More specifically, please refer to the following figures The negative ions (in-mobile) are due to the the accumulation of the positive ...
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116 views

NMOS: why VGS instead of VG?

I am having lots of trouble trying to understand how the mosfet is triggered. The text I read assumes the source of the NMOS connect to ground, while a positive voltage is applied at the gate. ...
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Derivation of depletion layer in depletion mode in MOS Structure

First off, please understand my background. I am doing a course in Digital Integrated Circuits and following the book CMOS Digital Integrated Circuits and Design by Kang (3rd Edition). I barely have ...
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58 views

NOT consistent Euler Paths in logic diagram. What now?

i'm working with non-series-parallel arrangements, something like this: as you can see, the euler paths in pull-up and pull-down are differents. for example, in pull-up we have "abcde" and in ...
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86 views

More advice desired on my Model Railroad Building light controller circuit

Building is built in O Scale (1/48) and has 40 rooms that are lighted independently (masked out from each other with walls) Rooms are lighted with White LEDs. The rooms will light one at a time (but ...
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83 views

Floating a digital output pin of an IC

I'm using a FXLS8471Q accelerometer for a project using the SPI interface. The chip uses the same pins for SPI and I2C. To detect which interface the user desires, the chip samples the SA0 pin on ...
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167 views

Circuit for model railroad building lighting control

The building has 10 separate rooms. Want the circuit to turn on LEDS to light each room sequentially. Another words you turn the circuit on, a 555 timer pulses and turns on room one. About 5 seconds ...
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1answer
99 views

LTSpice Level 2 Simulation CMOS follower

I'm trying to make a level 2 simulation of a voltage buffer made by a CMOS circuit: For this, I have been told to use level 2 CNM25 technology Spice models for the transistors, and I have been ...
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219 views

Circuit to switch about 5W of 12V using CMOS logic inputs using N-channel MOSFET?

I want to switch some 12V landscape light LEDs, totaling about 5 watts, using MOSFETs. I thought I had some logic level N-Channel MOSFETs lying around, but apparently not. What I have is several ...
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94 views

Is a DVD sensor a photodiode or an array of them?

Is a DVD sensor just a photodiode or an array of them? I need to know if it is a CMOS with an array of them or just a single sensor.
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89 views

Voltage transfer characteristics of a C-mos inverter

How to determine the voltage transfer characteristics of a c-mos inverter during the region when both the p-mos and the n-mos transistors are in the saturation region.I know that both the transistors ...
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31 views

Using n-mos and p-mos transistors as pass transistors! [duplicate]

The n-mos passes a good '0' and the p-mos passes a good '1'.What is the logic behind this?Can anyone suggest a proper book to study Vlsi design?
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Should I use CMOS vs. TTL?

Now, I know that this question has been asked so many times that it seems like I'm trolling, but I must point out that I couldn't find the right answer to this question anywhere. So yeah, CMOS and ...
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54 views

Capacitive load at the output for analysis of CMOS cells

This question is very rudimentary one. Please point me to the link if this question has been already asked. In general, when working with simulations and and analyzing the standard cells designed ...