"Complementary Metal-Oxide Semiconductor" is a circuit topology which uses a combination of PMOS and NMOS transistors to create logic gates. Most current digital logic is implemented as CMOS.

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How to size CMOS transistors

I am new to CMOS technology and I am trying to learn about CMOS logic gates. I have a problem with transistors sizing. As far as I could understand the main idea is to obtain equal rise and fall ...
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30 views

Design of the two stage amplifier with p-type input

I have to design the two stage amplifier with p-type input (p-type diff pair), the schematic bellow: However, mostly tutorials discuss the same architecture but with n-type input. My main ...
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36 views

Minimum delay path and sizing of CMOS gates

I've been wracking my brain for the past 3 hours trying to figure this one out, and all the examples I've seen just slap an answer on there like it's supposed to be obvious, which I can't for the ...
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33 views

CMOS on breadboard - Which P & N type MOSFETs to get started?

I would like to implement my own CMOS logic on a breadboard. I have already designed a simple PCB with basic logical functionality but now I'm stuck on the choice of N & P Type transistors ...
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40 views

CMOS logic gate output

What happens to Voh and Ioh when the number of loads connected to the output of this logic gate increases? My interpretation is: the increase in number of loads decreases the equivalent impedance, ...
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24 views

How do I use the CD4026 IC with a multiplexed 7-segment display?

I have 2 pcs. of 3 digit multiplexed 7-seg display (ELT-511SURWA) and 6 pcs of CD3026. I am building a frequency counter (CD4060 + crystal as timebase). I have considered using 6x UDN2983 + CD4017 + ...
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1answer
36 views

How to get the same output signal but with an increased capacitive load?

I'm designing a CMOS circuit of a VCO and it works perfectly fine when tested independently. Now when I cascade an other block like a divider to it, the output isn't the same as before. Rather its ...
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29 views

Inside A Coulomb Counter

I am trying to continuously measure the state-of-charge of a 3.5V nominal Lithium Ion battery. [My first question: Is this possible without using discrete method?] My approach is to place a sense ...
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2answers
60 views

MOSFET as a VCCS or an variable resistance

I am a bit confused. In saturation region, sometimes, an MOSFET is called voltage-controlled current source and sometimes it is called variable resistor where its resistance is controlled by the ...
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1answer
41 views

Solid State Relay from CMOS pin

I want to operate the LCC110 solid state relay from a 5V CMOS output pin on the PGA2505. I can see that I will likely need 8mA to drive the relay. However, I don't see on the PGA2505 datasheet if it ...
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1answer
49 views

DIL IC for simple non-volatile memory [closed]

Can anyone suggest a DIL IC where I can store a couple bits of memory without having to use a complicated interface like serial, I2C, and etc. I want to be able to store at least 2 bits of memory to ...
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26 views

M48Z02 (16Kbit ZEROPOWER SRAM) is TTL compatible?

I've some problem using together TLL and CMOS integrated. I'm developing a project and only now I discovered that the two standards can create troubles together. So I decided to use only TTL chips. ...
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Bredboard compatible FAST TTL [duplicate]

I have been looking for 16-bit ICs for a project i`m working on. The project is to build a 16-bit computer from scratch, therefor i decided i nedded cgips that could handle high clock-frequensies. ...
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62 views

Input resistance of differential LNA

This is a wideband differential LNA. I am trying to calculate the input resistance of this circuit but the result is not anything similar to the result shown in the picture below. Could you explain ...
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2answers
426 views

CMOS and gate implementation

As far as I am aware, this is an incorrect implementation of an AND gate, as when out is logic high, the two N-type FET transistors will go to an open state, leaving it floating. I am doubting my ...
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1answer
159 views

CMOS transistors for educational purposes

I am currently teaching my daughters Digital Electronics, ages 9 and 12. In doing so, I wanted to introduce them to CMOS logic, since I feel that a hands-on approach is always better than just doing ...
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1answer
27 views

How diffusion constant vary with temperature in Semiconductors?

Diffusion constant = Mobility*Thermal Voltage *Where,Thermal voltage = T/11600* From above equation it is clear that Diffusion constant should ...
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1answer
31 views

What is Minority Carrier Storage Time?

I know that Minority Carrier Life-Time is the time difference Between generation of minority carrier & their Recombination. I am bit Confused Between Minority Carrier Storage Time & Minority ...
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1answer
103 views

Push pull CMOS output stage overcoming the distortion problem

I implemented the simple push pull source follower and I understand that it has this distortion problem. That is between -|VTP| ≤ Vin ≤ VTN there is no output because the output terminal floats since ...
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1answer
22 views

Why diffusions in CMOS CAD tool (Magic) is continuous

I am using Magic to draw some transistors and create digital logic gates. While I was studying the theory about MOSFET I've always seen images like the one below. In this picture, one can see that ...
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4answers
124 views

Digital Circuit to Check for Majority

I have 31 digital inputs (each is high or low) and want one digital output which is high only if at least 16 inputs are high. How can I implement this "majority" function (which is also the most ...
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3answers
313 views

What is the maximum allowable load capacitance for 74HC04?

Does anybody know the maximum allowable load capacitance for 74HC04? In the datasheet, nothing is mentioned in the "Limiting values" section. Some of the dynamic characteristics are given for a load ...
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1answer
65 views

NMOS/PMOS logic vs. CMOS logic

With PMOS and NMOS, one can deduce that it is off, if Vgs < Vt (NMOS) || Vsg < Vt (PMOS) id = 0. Now my question rests on the dependency of these conditions. I know proving condition 1 ...
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66 views

Cross coupled-gm boosting stage

From this paper, a wideband differential LNA is proposed with structure below: The first stage is called "cross coupled- gm boosting stage". I am wondering if there is a mistake here. As seen from ...
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31 views

Beta Multiplier - Not Getting Correct Reference Current

Solved: The body of M2 needs to be connected to ground and not to source. I am reading a textbook on CMOS technology and I am having trouble simulating a beta multiplier in NGSPICE. The reference ...
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1answer
78 views

Threshold voltage of a pseudo nmos inverter

How can I find the Vm of a pseudo nmos inverter? Since I dont know the Vds of neither of my transistors I cant determine in which region they are. The circuit and some parameters are in that link. ...
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38 views

Negative Charge Pump- How to analyze this?

I am using CMOS 4069 inverter and wired up this circuit. I want to generate a \$-V_{dd}\$ negative pulse and \$2V_{dd}\$ positive pulse. The circuit above is for the negative voltage. However, I get ...
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512 views

Using CMOS Schmitt trigger inverters in quartz crystal oscillator circuit

In all sources I've seen about quartz crystal oscillators using CMOS inverters there's a note like this: But why Schmitt inverter is needed? Won't classic 74HC04 work?
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72 views

Basic gain cell

Guys i was going through basic gain cell topic in my textbook. I came accross this circuit. Pls explain how vo is not equal to VDD. I mean how can they be different? There is no resistance that ...
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1answer
57 views

Biasing using constant current source

guys i was going through this diagram in my book when these lines came along(i am a student): Here RG(usually in M-ohm range) establishes a dc ground at the gate and presents a large resistance to ...
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3answers
169 views

Ultra low power 555 timer circuit

I am trying to design a circuit involving an LMC555 CMOS timer operating as a monostable multivibrator. Essentially, I want a momentary switch to turn on a set of LEDs for ~20 seconds and then turn ...
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1answer
53 views

DMOS construction

I am learning for my exam , and i am not sure if this DMOS construction si correct. Did i make any mistake or is it as it should be?
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55 views

Does CMOS J/K trigger need pull-up resistor

I want to use J/K trigger and I was told that usually IC outputs need pull-up resistor, but if I understand it correctly the following J/K trigger is based on CMOS: TI J/K trigger And it seems to me ...
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252 views

Why can't CMOS simply be made of n-type enhancement mode MOSFETs and n-type depletion mode MOSFETs?

According to my textbook, a CMOS must use both PMOS and NMOS transistors because a CMOS needs transistors that follow the positive logic system and transistors that don't follow the positive logic ...
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389 views

Assistance with CMOS simulation

It's been a very long time since I took intro level EE courses. I'm working on a hobby project and as a refresher I figured I would simulate a CMOS inverter. For the life of me I can't figure out why ...
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66 views

native mos: how to turn off

I am studying about native mos and want to use it for my oscillator. However, I can't seem to find any document describing how it works and how to use it. How to turn off native mos? I know that ...
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1answer
52 views

Different voltage characteristics of CMOS NAND gate for different connections

Recently, I've played with a simple 2-input 1-output NAND gate realised in CMOS technology as shown in Fig. 1. Fig. 1. CMOS NAND scheme. I took some measurements of volteges U(output) vs. ...
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1answer
80 views

What is the meaning of Bootstrapping Phenomenon in MOSFET,What are its Consequences & How to avoid it?

According to what i have read from book Bootstrapping occurs because of capacitance b/w Gate & drain of mosfet,Bootstrapping Phenomenon results into Glitches at the output.I have read from ...
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2answers
42 views

Why is Vtyp less than Vmin on a CMOS chip

Regarding the chip 74HC08 On the table describing Static Characteristics (Section 9). Why is the typical VIH lower than the minimum value. And vice versa for VIL
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1answer
64 views

CMOS Gate and Coupling Noise from Loose Wires

I am currently working on this small circuit which as you can see, has to level shift a 3.3v 1Hz PPS signal into a 5v pulse. Everything is marvelous when I measure the level shifted pulse with ...
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1answer
67 views

what is telescopic Mos load

i have a design project, which includes designing a single stage amplifier (cmos device) i have to use telescopic p mos load to design degenerated common source single stage amplifier. what exactly is ...
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CMOS op amp subtractor deviation

I constructed a single stage differential amp and used it to make a subtractor. The input amplitudes are 2 mV and 3 mV, however the output is about 1.4 mV. Can anyone tell me why?
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83 views

CMOS Fabrication Process - Ion Implantation

During the process of producing the source and drain of the MOSFET, people use a technique called ion implantation. So my question is why use ion not atom? Thanks very much!
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1answer
60 views

How to design Digital logic gate using TFET logic?

In my recent project, I need to design digital logic gates using TFET instead of CMOS logic. Can someone Suggest any simulator or procedure which support design using TFET logic?
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1answer
80 views

How to prevent internal MOSFET from being precgharged?

For MOSFET circuits: simulate this circuit – Schematic created using CircuitLab Say, how do we make sure that the gates M3, M4 are never pre-charged, so that they will always produce the ...
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1answer
177 views

Truth table to transistor diagram and Boolean experssion to transistor diagram

I'm having a little trouble, making transistor level diagrams based off truth tables and Boolean expressions. I was doing a problem to which I understand the first part, but I am unsure on how to do ...
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72 views

Routing audio signal with CMOS Analog Multiplexer

I am quite new to electronics but I'm planning to build a device for routing analog audio inputs (cinch) to one output. I want to select one input channel (using a raspberry pi) to forward to the ...
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1answer
469 views

Basic TIE HIGH and TIE LOW circuits in Digital VLSI Design

I am trying to understand how a basic TIE HIGH and TIE LOW circuit that are based on diode connected MOSFETs followed by a PMOS pullup or NMOS pull down for TIEHI/TIELO accordingly work ? How does ...
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51 views

When does the NMOS form the channel? VGS > VTH or VGB > VTH?

When does the NMOS form the channel? VGS > VTH or VGB > VTH? I see that textbook talks about VGS > VTH, channel formed, but the capacitor is formed between the gate and the body, so i think it ...
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335 views

CMOS: Why is an nMOS transistor a bad conductor of high logic, but a good conductor of low?

I can't find an answer that addresses this and makes sense to me. I know that V_t is subtracted from the 'output', but I don't understand why.