CMOS stands for Complementary MOS, most digital logic is made in CMOS.

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Create a CMOS circuit from a logic function F=~A+B

I tried to draw the a CMOS logic circuit, but I don't know whether is is right or not. The function is: \$ F = \overline{A} + B \$ $$ F = \overline{A} + B $$ $$ \overline{F} = ...
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Connecting unused logic gates

Logic gates like AND, OR, NOT etc. often come packed as arrays in ICs. Sometimes not all gates are used in a project. I would like to know how the remaining unused gates should be connected to ...
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35 views

Can the CMOS 4014b be used as a SIPO shift register?

I'm currently working on a school project that requires the use of an 8-bit shift register. I collected the components for the project on the last day of school rather hurriedly, and I picked the ...
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35 views

What will be this CMOS logic circuit's Truth Table?

I encountered with this MOSFET logic circuit and asked to find which logic gate it represent. simulate this circuit – Schematic created using CircuitLab How can I calculate it's logic ...
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CMOS Logic system

When I was practicing logic circuit design using PMOS and NMOS , It's said that we have to use all PMOS for Pull Up Network (PUN ) and NMOS for Pull Down Network (PDN). But we know that for input ...
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189 views

First chip with 1000 or more transistors?

I am wondering what was the first chip ever with over 1000 transistors? I already am aware of the following: The Intel 4004 was the first commercially available single-chip microprocessor and it ...
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34 views

Modern 3.3V CMOS Logic gates

I wonder what series of 3.3V CMOS logic gates are the standard in the year 2015. Decades ago, when I learned about digital logic the 7400 TTL series was just going out of favor for the CD4000 series. ...
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22 views

I want to make a cd4049 cmos inverter spice model

I know the cd4049 is just two FET's but I don't know how I can model those transistors to be at least near what one would expect from the behavior of the IC. Also, what parameters are absolutely ...
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33 views

best/worst rise/fall of 2 input cmos nand gate

The truth table of a 2 input cmos nand gate is- A B Y 0 0 1 0 1 1 1 0 1 1 1 0 As far as I know the first row is the best rise and the last row is the best(only) ...
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35 views

What determines the # of pins of a cmos Imaging sensor?

Why do some cmos Imaging sensors have 48 pins and others 36 and some 34...e.c.t? I'm new to these sensors and I don't really understand the connectivity differences.
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How many transistors in Y = ((A+B+C).D)' in CMOS?

There is an example for Y = ((A+B+C).D)' in here. How do I know how many transistors it has? For instance NAND and NOR in CMOS both have two transistors, but I don't really know how to count ...
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205 views

Why is CMOS fall time faster than rise time?

I've just started a computer architecture class, and the slides from a lecture says that the reason why fall time is faster than rise time is that the NMOS electrons have more mobility than PMOS which ...
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32 views

OmniVision CMOS sensor package name for camera modules?

I seen few camera modules by OV, that come on a flex cable like the one below (OV2640) How does this package called? I see on the OV website COB, CSP, uCSP,CLGA, but I suspect they're without the ...
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35 views

Video via STM32F746NG (ARM Cortex M7) VS SM320DM6446 (ARM9)?

I am interestedin getting a Video feed from a CMOS sensor module like the OV2640 or OV7670. I found that the STM32F746NG has a camera interface which is useful, but I also found out that the ...
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1answer
31 views

Using an analog demultiplexer as a digital demultiplexer

If I want to use an analog de/multiplexer as a digital demultiplexer, do I have to use pull-up / pull-down resistors? For example when driving a CMOS IC like the 4015 with the CMOS analog 4051, do I ...
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1answer
25 views

CD4017BE output pin question

I am designing a circuit which uses a CMOS decade counter to activate and deactivate pairs of transistors in turns.The problem is:will the IC be damaged if the current of one of the outputs(activated) ...
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94 views

CMOS explanation

Please, explain me the CMOS Inverter at the physical layer trying not to involve mathematical formulas. Just in terms of physics. Mostly I wonder how the same high voltage on the gates can cause the ...
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28 views

What kind of driver should I implement in buck convertors

I have a couple of questions. In the diagram below, when the current falls to 0 , the NMOS is supposed to turn off. Similarly when the voltage error increase the PMOS turns off. However in the diagram ...
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52 views

Power and Ground Clamp Diodes in CMOS IO Buffer

I have usually seen Power & Ground Clamp diodes in CMOS structure as per attached figure. They are protection diodes. But I have few doubts :- 1.can someone explain in what situations they are ...
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30 views

TTL Vs CMOS technology [duplicate]

why now a days most of the devices in market are CMOS technology instead TTL? Its depends on digital and analog design respectively? or because of CMOS has Lower dissipation and low input voltage when ...
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82 views

pmos transistor acting as pull down device

I have a simple question related to the pmos transistors. Why can't it be used to fully pull down a high voltage signal? Can somebody please help me to understand the electrical characteristics behind ...
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1answer
86 views

Extracting and Using Sensor in Camera Assembly of Nokia Lumia 1020

I am trying to use the awesome camera sensor in the Nokia Lumia 1020 for research purposes. Unfortunately, my screen is broken so the screen is completely black. I intend to disassemble the phone, ...
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81 views

Protecting complementary MOSFET switch

I have a complementary MOSFET switch that turns ON/OFF a DC voltage offset of 2.25 V that is provided to another circuit. The switch is controlled by a digital signal, Vctrl, from a PIC18. Simulation ...
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80 views

Substrate Connection when driving a Bi-Directional Switch

I am very confused about the way the below circuit functions. Below is an excerpt from a research paper which shows two NMOS transistors connected such that the body diodes face each other back to ...
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Significance of -1 slope in CMOS inverter transfer characteristics

In the CMOS inverter transfer characteristics what is the significance of slope of \$-1\$ at the points where \$V_{IH}\$ and \$V_{IL}\$ have been shown? And how is this the occurrence of the values, ...
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27 views

Cmos Sensor, Difference bettween column amplifier and pixel amplifier?

what is the difference between column amplifier and pixel amplifier (source follower)? how a column amplifier works is it by chosing the size of the capacitor? But i also would like to understand the ...
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CMOS voltage swing problem

I modelled an XOR gate using HSPICE (Transistor level).Input voltage signal is 4V and Vdd of the circuit is 5V (threshold voltage= 1v). While giving input voltage 4v I got Maximum output voltage swing ...
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48 views

How to reduce voltage of an SRAM cell in HSPICE?

I have a simple 6T SRAM cell and I would like to reduce its voltage VDD for a short period of time. I expect the cell node Q and QB to flip after pulling the voltage supply to zero or at least to ...
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43 views

HSPICE code to cut off supply voltage of a subcircuit

I am trying to cut off the supply voltage "Vcontrol" of a subblock "circuit" for a very short time using a pmos, a nmos transitor and a voltage source. The Hspice code is as follows: ...
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150 views

Use Arduino(5V) to switch a 3.3V

I have a HDMI switch that I want to control with an Arduino. It's working by pressing a button to change input signal. The button is NC(Normally Close). By pressing the button you break the 3.3V going ...
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35 views

Substrate design in MOS ICs

In CMOS technology, why does the substrate always have to be p doped? When we need a p-channel MOSFET, we generally create an n-well into it and create p source and drain regions. Why does the balance ...
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133 views

CMOS inverter delay

Please tell me whether my thoughts on the question below is correct or not. How does the delay of a CMOS inverter decrease when we increase the supply voltage? What I thought was if ...
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85 views

Question about logic gate optimization and CMOS implementations

I am struggling with a conceptual question surrounding logic gates and how they're efficiently implemented in CMOS circuits. For example, let's say I want to implement a NAND gate. If I didn't know ...
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59 views

MOSFET as a switch. Why does the voltage depend on the gate?

Let's say I have an NMOS, the gate is connected to 5 volts, Vth is 0.7 volts and I want to pass a voltage of 7 using the NMOS as a switch. Can you tell me what will be the voltage at the source? Will ...
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47 views

cmos output buffer currents

In a cmos driver what controls the amount of current it can source or sink? Is it the combined RDS on of the internal FETs? When you try to pull a line low I guess there's voltage stored in the ...
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39 views

Balancing Rise and fall times at input and output in CMOS Design

How do I make sure that my rise and fall times are balanced between input and output in a CMOS design?
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124 views

How do the access transistors in an SRAM cell work?

For example, in the picture above, how do M5 and M6 really work? how can they be turned on by simply asserting WL? wouldn't the transistors turn on or off based on the gate-source voltage? I don't ...
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What is this effect causing a flash on video when a model aircraft collides with the ground?

When recently flying a model airplane with friends, I was recording on a smartphone camera (I believe CMOS, 720p, 120fps), and saw, in one of the videos, a flash that was not visible to the naked eye, ...
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How does this regenerative latch push the circuit into saturation or 0 V

I am looking into this circuit which is a comparator latch. In the above diagram there are 2 gain stages. For the first 1 , a PMOS is used as a load and an NMOS for the second stage. If the ...
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22 views

CMOS: Getting time delay and power dissipation of a huge circuit (e.g. multiplier)

Our design project is to build a carry save multiplier in CMOS. We already have the spice netlist and layout. Problem is, we are also asked to get the timing delays such as the propagation delay ...
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Common drain CMOS single stage amplifier with current bias with positive and negative rail analysis

I was presented with a classical problem where i am asked to evaluate the output of this circuit when VIN = 0 and then 5 volts. The NMOS will be off as long as Vgs is less than Vtn. The NMOS will ...
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Is inverting the output of a CMOS network a bad practice?

I am an Electronics & Comm. Engg. 3rd yr. student and we are learning CMOS logic for the first time this semester under the subject VLSI design. While designing for the logic equation: \$Y= A + ...
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48 views

Operation of this CMOS Logic

I found this CMOS circuit in my textbook. It says that when input voltage is 0V, the output voltage is 0V, and IDN and IDP are both zero. I think that the output voltage is 0V due to some form of ...
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34 views

why resistance of n-channel transistor in series is less than p-channel transistor?

why series n-channel transistor resistance is less than the p-channel transistor? how n-channel transistor are faster than the p-channel transistor? why additive "on" resistance of series transistors ...
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90 views

TTL to CMOS Different Supply voltages

I am designing a circuit using a CD4011 Nand Gate 5 volt Vcc and a CD4555 using a 15 volt vcc. Will the Nand gate High output have enough voltage to drive the input of the CD4555 to a High Output? ...
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43 views

Combining CMOS and TTL logic

I have a bunch of 74LS383 (TTL octal transparent latch with three-state outputs) and MM74C83N (CMOS 4-bit binary full adder) that I would like to connect together. I need to connect the output of the ...
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131 views

Effective transconductance of a CMOS inverter

If we have a CMOS inverter operating in its' linear region, what would be the effective trans conductance of the inverter?
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Somewhat broken 74HC00 ic. What happened to it?

I built the following single stepping circuit using a new 74HC00. The inputs for the two unused gates were connected to GND and power decoupled with 0.1uF as close as I could. The circuit appeared ...
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Infrared filter on CMOS single package sensor

I am trying to recognize infrared-reflectors with a CMOS module. The ideal would be to use an IR filter to get rid of everything else and only have the trackers (reflectors) on the picture. I found ...
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67 views

Discharge of a load capacitor through a cascode

How will a cascode effect the discharge of the load capacitor? I would expect that the discharge trough the cascade is slower since the cascode has higher output impedance. simulate this ...