CMOS stands for Complementary MOS, most digital logic is made in CMOS.

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CMOS inverter delay

Please tell me whether my thoughts on the question below is correct or not. How does the delay of a CMOS inverter decrease when we increase the supply voltage? What I thought was if ...
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Question about logic gate optimization and CMOS implementations

I am struggling with a conceptual question surrounding logic gates and how they're efficiently implemented in CMOS circuits. For example, let's say I want to implement a NAND gate. If I didn't know ...
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Hackrf External Clock with LVCMOS‏

Hi 1)I recently buy TCXO(Vectron C2260A1 3.3v) for my hackrf but i'm not sure about CMOS and LVCMOS square waveforms.Can someone say is it compatible or incompatible with my hackrf's si5351c clock ...
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MOSFET as a switch. Why does the voltage depend on the gate?

Let's say I have an NMOS, the gate is connected to 5 volts, Vth is 0.7 volts and I want to pass a voltage of 7 using the NMOS as a switch. Can you tell me what will be the voltage at the source? Will ...
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cmos output buffer currents

In a cmos driver what controls the amount of current it can source or sink? Is it the combined RDS on of the internal FETs? When you try to pull a line low I guess there's voltage stored in the ...
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Balancing Rise and fall times at input and output in CMOS Design

How do I make sure that my rise and fall times are balanced between input and output in a CMOS design?
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How do the access transistors in an SRAM cell work?

For example, in the picture above, how do M5 and M6 really work? how can they be turned on by simply asserting WL? wouldn't the transistors turn on or off based on the gate-source voltage? I don't ...
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What is this effect causing a flash on video when a model aircraft collides with the ground?

When recently flying a model airplane with friends, I was recording on a smartphone camera (I believe CMOS, 720p, 120fps), and saw, in one of the videos, a flash that was not visible to the naked eye, ...
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How does this regenerative latch push the circuit into saturation or 0 V

I am looking into this circuit which is a comparator latch. In the above diagram there are 2 gain stages. For the first 1 , a PMOS is used as a load and an NMOS for the second stage. If the ...
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CMOS: Getting time delay and power dissipation of a huge circuit (e.g. multiplier)

Our design project is to build a carry save multiplier in CMOS. We already have the spice netlist and layout. Problem is, we are also asked to get the timing delays such as the propagation delay ...
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27 views

Common drain CMOS single stage amplifier with current bias with positive and negative rail analysis

I was presented with a classical problem where i am asked to evaluate the output of this circuit when VIN = 0 and then 5 volts. The NMOS will be off as long as Vgs is less than Vtn. The NMOS will ...
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Is inverting the output of a CMOS network a bad practice?

I am an Electronics & Comm. Engg. 3rd yr. student and we are learning CMOS logic for the first time this semester under the subject VLSI design. While designing for the logic equation: \$Y= A + ...
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Operation of this CMOS Logic

I found this CMOS circuit in my textbook. It says that when input voltage is 0V, the output voltage is 0V, and IDN and IDP are both zero. I think that the output voltage is 0V due to some form of ...
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28 views

why resistance of n-channel transistor in series is less than p-channel transistor?

why series n-channel transistor resistance is less than the p-channel transistor? how n-channel transistor are faster than the p-channel transistor? why additive "on" resistance of series transistors ...
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58 views

TTL to CMOS Different Supply voltages

I am designing a circuit using a CD4011 Nand Gate 5 volt Vcc and a CD4555 using a 15 volt vcc. Will the Nand gate High output have enough voltage to drive the input of the CD4555 to a High Output? ...
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Combining CMOS and TTL logic

I have a bunch of 74LS383 (TTL octal transparent latch with three-state outputs) and MM74C83N (CMOS 4-bit binary full adder) that I would like to connect together. I need to connect the output of the ...
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Effective transconductance of a CMOS inverter

If we have a CMOS inverter operating in its' linear region, what would be the effective trans conductance of the inverter?
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55 views

Somewhat broken 74HC00 ic. What happened to it?

I built the following single stepping circuit using a new 74HC00. The inputs for the two unused gates were connected to GND and power decoupled with 0.1uF as close as I could. The circuit appeared ...
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Infrared filter on CMOS single package sensor

I am trying to recognize infrared-reflectors with a CMOS module. The ideal would be to use an IR filter to get rid of everything else and only have the trackers (reflectors) on the picture. I found ...
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Discharge of a load capacitor through a cascode

How will a cascode effect the discharge of the load capacitor? I would expect that the discharge trough the cascade is slower since the cascode has higher output impedance. simulate this ...
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When and who invented and introduced MTCMOS?

This is more of a historical interest question. I was trying to figure out when multithreshold CMOS processes were introduced, which foundry was first, and perhaps who came up with the idea for what ...
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Create a CMOS circuit from a logic function [duplicate]

I have to create a CMOS circuit from the logic function: F= ~A + B (notA or B). I made the truth table but I'm stuck here trying to make the CMOS circuit. Any ideas anyone? Thanks! I know it's the ...
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How can I use a NPN transistors to convert from 3.3v to VCC (3.9-3.0v)

I'm wanting to drive a NeoPixel from a CMOS device. The power for the neopixel is a 4v LiPo battery and will fall from around 3.9v to 3v before it cuts off. I have a few PN2222 NPN transistors, I'm ...
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Implementing logic gates in CMOS

I'm trying to build the below function with CMOS my implementation correct? $$ F = ABC + (\overline{B+C})D $$ I am having trouble with the $$(\overline{B+C})$$ in all of the examples I've seen the ...
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Level-triggered mono-stable multi-vibrator running at 12+ volts.

I need a CMOS (preferably dual) level-triggered mono-stable multi-vibrator that runs at least 12V (better at 15~18VDC), perhaps in the CD4000 family. Everything I have found is edge-triggered only or ...
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CMOS technology, use a NMOS or PMOS as series switch?

A general question regarding switches in CMOS. Have a look at the schematic below (symplified current mirror) There is a input reference current, on/off switch, a PMOS mirror and the resulting ...
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walking ring sine wave generator

simulate this circuit – Schematic created using CircuitLab Here is the low pass I have used. I used the 347 op amp just because it was cheap from a local surplus house. I will get ...
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Simple switching between clocks using oscillator disable pins

I am working on a circuit where I need to use different clock sources. I am using two HCMOS oscillators. Both oscillators have an disable pin. When disabled, the clock output buffer is placed in ...
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Cabling simple sensors 5-20 ft from a uC - tips and gotchas; UTP vs STP cables

The situation: using a simple microcontroller (eg: 5V Arduino Pro Micro) which needs to read a few sensors located about 5 to 20 feet away via cables. (This is a garage/storage area controller). The ...
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76 views

How does this voltage detector IC work in a circuit? What does open drain vs. CMOS output mean?

I'm evaluating the Rohm BD48/BD49 series voltage detector. I'm having trouble understanding the data sheet. I want to generate a high signal when the input voltage is above a desired threshold (3.0 ...
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151 views

CMOS OR gate using 4 Transistors

Can an OR gate be implemented using 4 CMOS transistors? The circuit would have two n-type transistors in parallel in the pull-up network, and two p-type transistors in series for the pull-down ...
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cmos inverter in voltage regulation

How does a CMOS Inverter drives the gate of MOSFET for voltage regulation? I have attached the image for clarification. I just want someone to explain me why two cmos inverters are connected to the ...
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Determine the Number of Transistors Needed to Build CMOS circuit

I would like to determine the number of transistors that will be used in the CMOS circuit below. Is there a specific formula for it?
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CD4050 Voltage leaks, what can I be doing wrong?

As often as I see the CD4050 used as a logic level converter, I'm surprised that I haven't heard much about how it seems to leak voltage from the inputs into Vdd. I hope this isn't a case where the ...
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Electret Mic Capsule to Piezoelectric Disk

I'm working on a project that involves creating units/cells that "listen" and "talk" to each other. The principle being the circuitry I've tried is to use an Electret MIC Capsule to pick up sound, ...
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How to construct CMOS equivalent of an XNOR gate using AND, OR, NOT gates?

I am new to digital logic and I am confused hot to construct CMOS equivalent for XNOR gate using AND, OR, and NOT gates. I found XNOR circuit implemented with gates. And what I did is I plugged CMOS ...
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Comparison of 180nm and 65nm CMOS technology in consideration of delay, power and energy consumption

how would each of them typically compare with respect to delay, power and energy consumption? (Used in digital circuits)
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Replacing resistors with active load in active filter

I am building a low pass filter IC in 0.25 micron CMOS. My design requires 14 Mega-Ohm resistors. I want to replace them with an active load in order to save space. If possible I would like to use a ...
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Choosing R when designing CMOS Amplifier

I am trying to design a two stage amp like the one pictured above. I want the overall small-signal gain, |Av| = vo / vid = 240 V/V = (47.6 dB). I know in theory how to achieve this but am having ...
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Is there relation between logic chip names and their internal structure

I know that for instance an ATMega328 is a 8 bit MCU with 32k of program space, the same can be said for most other MCUs and some other ICs with a direct relation between the name and internal specs. ...
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Transistor count in NAND or NOR implementation of boolean algebra?

I have a complex output function in boolean algebra ( Where '~' means NOT): F=~( (a c ~d) + (a ~c ~d) + (~a c) + (~ a c d) + (a c ! d b) ) I know this can be simplified down to: F = (~a ~c) + (a d) ...
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How to open recent schmatic on Tanner Eda Tools v13.0

This is my first time working with Tanner Eda Tools. I designed the circuit and then I saved the T-spice and S-edit and exported the PDFs successfully. My first problem is that I couldn't open my ...
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Howto convert “0=floating / 1=Vcc” to CMOS compatible “0=ground / 1=Vcc” signal

I'm playing around with CMOS logic using CD#### dip packages. As far I understand input pins should never be left floating, always connect them to Vcc or ground. Unfortunately my digital source ...
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Applying euler path to CMOS schematic with inverter

I've discovered that tracing the Euler path of a CMOS schematic can aid in creating compact stick diagrams. I have an issue, though. Of all the lectures I've read on the net, the pull-up and ...
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Simplifying CMOS schematic to reduce number of transistors

I know the basics in creating a schematic in CMOS, wherein in a(n inverted) boolean expression, if there is a: NOR - NMOS should be in parallel, PMOS in series; NAND - NMOS in series, PMOS in ...
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Why TTL logic gates are faster when compared to CMOS logic gates? [duplicate]

In TTL families resistors are used and number of stages between input and output terminals is comparatively high. Still operation speed of TTL is better than CMOS. Why?
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Understanding the Texas Instruments CD4075 datasheet table

I downloaded the CD4075 IC datasheet and I'm having trouble understanding the lines labelled "Output High (Source) Current" in the table below. The table shows current values relative to temperature ...
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adjust clock frequency using Timing Error Avoidance Technique

I am following the next example as is depicted on the diagram, in order to adjust the clock frequency of a multiplier to its maximum. The System works as follows: The flip-flop at the input to the ...
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Improving my impulse counter circuit

I just started studying electrical engineering this semester, and I'm currently working on following impulse counter: The circuit is basically a power supply regulated to 5V, a pendulum acting as ...
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falling delay inverters VLSI CMOS

How do I obtain the falling delay driving by signal A: Data: ...