"Complementary Metal-Oxide Semiconductor" is a circuit topology which uses a combination of PMOS and NMOS transistors to create logic gates. Most current digital logic is implemented as CMOS.

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Ultra low power 555 timer circuit

I am trying to design a circuit involving an LMC555 CMOS timer operating as a monostable multivibrator. Essentially, I want a momentary switch to turn on a set of LEDs for ~20 seconds and then turn ...
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46 views

How to properly use CMOS chips, specifically 74HCs [on hold]

I can't find an in-depth guide anywhere on how to properly use these chips. Even reading the datasheets thoroughly and wiring the chips up fails for me. Is there any guide out there on how to properly ...
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34 views

How can CMOS technology be used for Audio Signal Processing [closed]

So I'm a bit of a newbie. I am studying both these subjects and I am trying to understand what products currently exist that require the use of both domains of electrical engineering. Need this help ...
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53 views

Question regarding introduction to Digital System Design [closed]

I am a computer engineering student who find trouble understanding the concepts below. I have looked over wikipedia and my notes again and again and still have trouble putting all the concepts ...
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62 views

What used to happen when the non-rechargeable CMOS battery ran out? [migrated]

I'm taking a uni course on electrical engineering and my textbook says that the CMOS battery used to last between 2 and 10 years. Since preserving BIOS settings seems quite important to me, I was ...
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Multistage CMOS amplifier design

my professor gave us a task to design a multistage amplifier using NMOS and PMOS transistors with a minimum width W=18um, 1.8v battery(multiple if needed and any sort of resistor/capacitor. The only ...
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45 views

DMOS construction

I am learning for my exam , and i am not sure if this DMOS construction si correct. Did i make any mistake or is it as it should be?
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51 views

Does CMOS J/K trigger need pull-up resistor

I want to use J/K trigger and I was told that usually IC outputs need pull-up resistor, but if I understand it correctly the following J/K trigger is based on CMOS: TI J/K trigger And it seems to me ...
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2answers
235 views

Why can't CMOS simply be made of n-type enhancement mode MOSFETs and n-type depletion mode MOSFETs?

According to my textbook, a CMOS must use both PMOS and NMOS transistors because a CMOS needs transistors that follow the positive logic system and transistors that don't follow the positive logic ...
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29 views

MOS parallel to antenna - antenna clamp, antenna modulator

I would like to understand the following thing: in RFID passive circuits there are MOS transistors, which work as a clamp or a modulator. These transistors are in parallel to antenna. Drain is ...
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5answers
362 views

Assistance with CMOS simulation

It's been a very long time since I took intro level EE courses. I'm working on a hobby project and as a refresher I figured I would simulate a CMOS inverter. For the life of me I can't figure out why ...
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35 views

native mos: how to turn off

I am studying about native mos and want to use it for my oscillator. However, I can't seem to find any document describing how it works and how to use it. How to turn off native mos? I know that ...
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1answer
30 views

Different voltage characteristics of CMOS NAND gate for different connections

Recently, I've played with a simple 2-input 1-output NAND gate realised in CMOS technology as shown in Fig. 1. Fig. 1. CMOS NAND scheme. I took some measurements of volteges U(output) vs. ...
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59 views

What is the meaning of Bootstrapping Phenomenon in MOSFET,What are its Consequences & How to avoid it?

According to what i have read from book Bootstrapping occurs because of capacitance b/w Gate & drain of mosfet,Bootstrapping Phenomenon results into Glitches at the output.I have read from ...
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2answers
34 views

Why is Vtyp less than Vmin on a CMOS chip

Regarding the chip 74HC08 On the table describing Static Characteristics (Section 9). Why is the typical VIH lower than the minimum value. And vice versa for VIL
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1answer
55 views

CMOS Gate and Coupling Noise from Loose Wires

I am currently working on this small circuit which as you can see, has to level shift a 3.3v 1Hz PPS signal into a 5v pulse. Everything is marvelous when I measure the level shifted pulse with ...
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1answer
54 views

what is telescopic Mos load

i have a design project, which includes designing a single stage amplifier (cmos device) i have to use telescopic p mos load to design degenerated common source single stage amplifier. what exactly is ...
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34 views

CMOS op amp subtractor deviation

I constructed a single stage differential amp and used it to make a subtractor. The input amplitudes are 2 mV and 3 mV, however the output is about 1.4 mV. Can anyone tell me why?
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50 views

CMOS Fabrication Process - Ion Implantation

During the process of producing the source and drain of the MOSFET, people use a technique called ion implantation. So my question is why use ion not atom? Thanks very much!
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1answer
40 views

How to design Digital logic gate using TFET logic?

In my recent project, I need to design digital logic gates using TFET instead of CMOS logic. Can someone Suggest any simulator or procedure which support design using TFET logic?
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1answer
77 views

How to prevent internal MOSFET from being precgharged?

For MOSFET circuits: simulate this circuit – Schematic created using CircuitLab Say, how do we make sure that the gates M3, M4 are never pre-charged, so that they will always produce the ...
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1answer
100 views

Truth table to transistor diagram and Boolean experssion to transistor diagram

I'm having a little trouble, making transistor level diagrams based off truth tables and Boolean expressions. I was doing a problem to which I understand the first part, but I am unsure on how to do ...
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62 views

Routing audio signal with CMOS Analog Multiplexer

I am quite new to electronics but I'm planning to build a device for routing analog audio inputs (cinch) to one output. I want to select one input channel (using a raspberry pi) to forward to the ...
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40 views

Where are the source and drain of each MOS transistor in this CMOS mask layout?

Here is the mask layout: I need to label source and drain of each MOS transistor but don't have much of an idea how. Can somebody help me with this please? Thanks.
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1answer
231 views

Basic TIE HIGH and TIE LOW circuits in Digital VLSI Design

I am trying to understand how a basic TIE HIGH and TIE LOW circuit that are based on diode connected MOSFETs followed by a PMOS pullup or NMOS pull down for TIEHI/TIELO accordingly work ? How does ...
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46 views

Choice of components for basic CMOS logic gates

I'm a hobbyist and I just went through some basic cmos logic gate theory, which I would like to put into practice : build simple logic gates (inverter, NOR, NAND...) and their combinations, eg a ...
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46 views

Silent audio switching using “specialty” CMOS switches?

Companies like Analog devices offer various CMOS switches with very low Ron and high resistance uniformity over freq. and signal amplitude (ADG1421, ADG1422, ADG1423, ADG5433, ADG5434...). What is ...
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39 views

When does the NMOS form the channel? VGS > VTH or VGB > VTH?

When does the NMOS form the channel? VGS > VTH or VGB > VTH? I see that textbook talks about VGS > VTH, channel formed, but the capacitor is formed between the gate and the body, so i think it ...
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279 views

CMOS: Why is an nMOS transistor a bad conductor of high logic, but a good conductor of low?

I can't find an answer that addresses this and makes sense to me. I know that V_t is subtracted from the 'output', but I don't understand why.
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1answer
48 views

Programmable Priority Encoder

I have been searching about programmable priority encoder but have not find a good explanation on it. I know about priority encoder. But generally what is 'programmable' priority encoder are? Can ...
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1answer
169 views

Please help me explain the overshoot and undershoot in CMOS inverter

Rabaey book says that: Notice especially the overshoots on the simulated output signals. These are caused by the gate-drain capacitances of the inverter transistors, which couple the steep ...
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86 views

Biasing an Operational Amplifier

Consider a simple two stage CMOS operational amplifier. When it's designed for given specification and is being used as an Op-amp block, doesn't its bias gets disturbed when any arbitrary voltage is ...
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129 views

on-chip low-pass filter with sub-Hertz cutoff frequency

Sometime ago I had to implement an on-chip (CMOS 65nm) low-pass filter (first order) with very low cutoff frequency (lower than 100mHz). I used PMOS pseudo resistors and momcap, and had to check all ...
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N Well, P Well, twin well and triple well pros and cons

Why each of the techniques mentioned in the title was developed in the first place? what is the advantage of each technique? I have been searching the internet for these questions but all I found was ...
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How can I protect an input signal to unpowered CMOS?

My circuit has a battery charger and an ATMega88. The ATMega needs to sense the state of the battery charger - but if the battery is too low, the ATMega may not have power. I know it's bad to drive a ...
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62 views

Create a CMOS circuit from a logic function F=~A+B

I tried to draw the a CMOS logic circuit, but I don't know whether is is right or not. The function is: \$ F = \overline{A} + B \$ $$ F = \overline{A} + B $$ $$ \overline{F} = ...
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Connecting unused logic gates

Logic gates like AND, OR, NOT etc. often come packed as arrays in ICs. Sometimes not all gates are used in a project. I would like to know how the remaining unused gates should be connected to ...
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1answer
68 views

Can the CMOS 4014b be used as a SIPO shift register?

I'm currently working on a school project that requires the use of an 8-bit shift register. I collected the components for the project on the last day of school rather hurriedly, and I picked the ...
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1answer
68 views

What will be this CMOS logic circuit's Truth Table?

I encountered with this MOSFET logic circuit and asked to find which logic gate it represent. simulate this circuit – Schematic created using CircuitLab How can I calculate it's logic ...
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61 views

CMOS Logic system

When I was practicing logic circuit design using PMOS and NMOS , It's said that we have to use all PMOS for Pull Up Network (PUN ) and NMOS for Pull Down Network (PDN). But we know that for input ...
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218 views

First chip with 1000 or more transistors?

I am wondering what was the first chip ever with over 1000 transistors? I already am aware of the following: The Intel 4004 was the first commercially available single-chip microprocessor and it ...
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1answer
60 views

Modern 3.3V CMOS Logic gates

I wonder what series of 3.3V CMOS logic gates are the standard in the year 2015. Decades ago, when I learned about digital logic the 7400 TTL series was just going out of favor for the CD4000 series. ...
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106 views

I want to make a cd4049 cmos inverter spice model

I know the cd4049 is just two FET's but I don't know how I can model those transistors to be at least near what one would expect from the behavior of the IC. Also, what parameters are absolutely ...
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77 views

best/worst rise/fall of 2 input cmos nand gate

The truth table of a 2 input cmos nand gate is- A B Y 0 0 1 0 1 1 1 0 1 1 1 0 As far as I know the first row is the best rise and the last row is the best(only) ...
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1answer
37 views

What determines the # of pins of a cmos Imaging sensor?

Why do some cmos Imaging sensors have 48 pins and others 36 and some 34...e.c.t? I'm new to these sensors and I don't really understand the connectivity differences.
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59 views

How many transistors in Y = ((A+B+C).D)' in CMOS?

There is an example for Y = ((A+B+C).D)' in here. How do I know how many transistors it has? For instance NAND and NOR in CMOS both have two transistors, but I don't really know how to count ...
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2answers
359 views

Why is CMOS fall time faster than rise time?

I've just started a computer architecture class, and the slides from a lecture says that the reason why fall time is faster than rise time is that the NMOS electrons have more mobility than PMOS which ...
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1answer
227 views

OmniVision CMOS sensor package name for camera modules?

I seen few camera modules by OV, that come on a flex cable like the one below (OV2640) How does this package called? I see on the OV website COB, CSP, uCSP,CLGA, but I suspect they're without the ...
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Video via STM32F746NG (ARM Cortex M7) VS SM320DM6446 (ARM9)?

I am interestedin getting a Video feed from a CMOS sensor module like the OV2640 or OV7670. I found that the STM32F746NG has a camera interface which is useful, but I also found out that the ...
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1answer
43 views

Using an analog demultiplexer as a digital demultiplexer

If I want to use an analog de/multiplexer as a digital demultiplexer, do I have to use pull-up / pull-down resistors? For example when driving a CMOS IC like the 4015 with the CMOS analog 4051, do I ...