Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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What are the stages of a graphics pipeline?

A MIPS pipeline has following stages: Instruction fetch Instruction decode and register fetch Execute Memory access Register write back Does such a "classic" ...
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22 views

Processor does fetch, decode, execute, memory read/write and register read/write. How can this result in more than 5 pipeline stages?

I have read this marvelous book on processor architecture. It teaches that: The classic RISC pipeline comprises: ...
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10 views

ALUOP for a single cycle datapath control

When designing a single cycle data path control unit using PLA (main control and ALU control) My question is how do I choose the ALUop bits and how to make its truth table for each instruction and ...
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2answers
67 views

Is it OK to use the USB 5v pin as power source?

I am doing some stuff in my case and I need a power source for one LED from inside my case. I looked up and there are two +5v pins on a USB header inside my case. Is it OK to use them as power ...
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0answers
23 views

find cache hit rate for direct mapped cache memory

I have this practice exam problem which I am having trouble with. I have gone over many slides but haven't been able to really get it. The question is I currently have an 8 block main memory with ...
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1answer
27 views

single cycle vs multicycle datapath execution times

I have a question where I need to calculate the execution time for a program for single cycle and multicycle datapath. I think I may be doing it incorrectly since the multicycle execution time is ...
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2answers
180 views

Are only word sizes used as structural elements in machine computation?

Research: I have been looking for some time online. everything i know in-fact. ive liked sparse matrix representations, i have found gate level sharing optimization after 'formula reduction' and ...
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1answer
33 views

Two dimensional 512 byte (byte addressable) RAM from 16 byte chips

Assume it is decided to design a two dimensional 512 byte (byte addressable) RAM from 16 byte chips. Each of the 16 byte chips has two select-lines. The chip is enabled only if both of the ...
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1answer
63 views

multicycle datapath vs single cycle datapath

I have a fairly simple question but have not been able to find a good answer googling. I understand how pipelining works by having 1 cycle per step, each instruction takes 5 cycles and they start ...
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4answers
2k views

How many clock cycles does a RISC/CISC instruction take to execute?

According to Digital Design and Computer Architecture by Harris and Harris, there are several ways to implement a MIPS processor, including the following: The single-cycle microarchitecture ...
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1answer
45 views

is it possible to mix chipsets

I'm designing a home made game console motherboard, and want to integrate the ATI Mobility Radeon 9000 GPU in it. The problem is, the Northbridge I picked only supports PCI Express, and the GPU uses ...
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31 views

Learning Booth's Algorithm, I Can't Find the Issue on Final Result

I am practicing using Booth's algorithm to multiply a positive number and a negative number (specifically -12 * 4). I have included my attempt, but i can't find the issue. If someone can help me out, ...
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0answers
36 views

Secondary Level address translation (EPT/RVI) TLB implementation

hope this is the right place to ask for the following: Consider a processor/cpu with support for Secondary Level address translation (SLAT) technology (Intel EPT/AMD RVI). TLB caching is used to ...
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1answer
111 views

What is happening in the diagram of LC3?

This is a diagram of the LC3 Computer I am trying to understand what is happening in the parts I highlighted. The part I had highlighted had the instruction bit sign extended to 16 bits and then ...
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3answers
72 views

Benefit of (logically/virtually) separate I/O and memory bus

In my course on embedded systems, it is explained that memory inputs can be separated from I/O inputs using a "mode bit" for the address decoder. The most obvious advantage of this is that the amount ...
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1answer
40 views

Simple Mux Equation finding, need help?

How we can find the equation of following simple diagram ? My TA solved it as : C.Not(B).A + B.Not(A)
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2answers
59 views

Is it possible to simulate hardware of MIPS architecture computer defined using Verilog/VHDL?

I am reading Digital Design and Computer Architecture book and if I will be persistent then I will have MIPS architecture computer at the end, implemented from scratch by me . I wonder is it ...
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1answer
300 views

Micro and Nano Memory, Calculate Reducing Bits?

I ran into a question: in digital system with micro-programmed control circuit, total of 32 distinct pattern operation signal is ...
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1answer
28 views

Which are the spec bits in this cache?

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. The physical address is 50 bits, numbered from 0 to 49 (with 0 being the least significant ...
3
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3answers
112 views

Logical Design Operation, A Simple Questions?

I'm so sorry if I ask my first question that so simple. My filed is Math and Computer science. I self-study Digital Design. My challenge is how we can find the operation of the two following ...
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1answer
24 views

What is the difference between a virtually tagged and a physically tagged memory system?

I study computer architecture and this question came. What is the difference between a virtually tagged and a physically tagged memory system?
3
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1answer
88 views

adding two 64-bits number with m-bit carry ripple adder and multiplexer, a questions?

I ran into a question from computer architecture class. The professor says that for adding two 64-bit numbers A and B we use m-bit carry ripple adders and multiplexers such as following: and that ...
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0answers
22 views

Where can I find literature on PCMOS (Probabilistic CMOS)

PCMOS is relatively new technology and I'd like to learn more about its inner workings. I have managed to find couple of papers on PCMOS on google scholar but they are all from 2006-8 so I was ...
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1answer
64 views

Logic Gate Cookbook [closed]

Is there a concise book that brings together all of the different Logic devices that can be implemented with basic logic gates? I have several digital/computer architecture books that have the ...
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1answer
98 views

How the lw (load word) instruction works on the MIPS Unicycle (Implementation)

I'm reading the Computer Organization and Design book from David A. Patterson and John L. Hennessy. Specifically, I have a question about the implementation of a MIPS Unicycle. So, in the book, they ...
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3answers
153 views

How Can A Coded Firmware Control Hardware [closed]

I really want to know how could a virtual coded program really affect and imitate and animate a piece of hardware. I Have Always Seen The Diagram Of Processors In the Book Showing ALU and CPU as The ...
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1answer
49 views

Difference between multiple pipelines and superscalar?

I have read some threads and the wiki articles, but still don't seem to understand what exactly the difference is between having multiple parallel pipelines and the superscalar architecture. I know ...
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2answers
75 views

Simplifying Circuits

I have a question regarding simplifying a circuit of a function below that has 5 logic gates in original. f = (A + B) * (C + D) + (A + B) * (C + D)' + C = (A + B) * ((C + D) + (C + D)') + C = (A ...
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6answers
2k views

How to efficiently design the opcode for a CPU?

I am building a simple 16-bit CPU in Logisim and have the ALU ready and the opcodes that I want to have. Now I find it really hard to find the right coding for the commands so that the different ...
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1answer
119 views

Why does the A8 have twice as many transistors than the Haswell processor yet runs on less power?

There's something I don't get - I am always under the impression that the more transistors we pack in, the more energy it consumes and the hotter it gets (assuming we haven't shrunk the die). However, ...
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2answers
174 views

Booth multiplication algorithm, why it works?

Just learned about Booth's multiplication algorithm, and from what I understand if the multiplier least significant bit (MLB) is equal to the previous significant bit in that multiplier (MPLB) then we ...
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2answers
178 views

Where is the best place I can go to learn everything about the electronics-side of computers? [closed]

Throughout my childhood, I grew up learning about electronics and computers. I am starting to get to the point where I want to incorporate my knowledge of both into a single project. I have tried ...
0
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2answers
93 views

You need at least four states to exploit the advantages of a Mealy machine over a Moore machine

What's meant by this question? "You need at least four states to exploit the advantages of a Mealy machine over a Moore machine." I'm trying to wrap my head around this but I'm not sure "what" ...
2
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1answer
109 views

Inherent exploitability and power state machines

I'm working on understanding power state machines in regard to mobile computing devices. Most of the information on this subject seems to stem from this article. It's not particularly important to the ...
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1answer
385 views

Determining memory address width from memory size

Given a computer A with 1024 x 16 memory and a computer B with 16K x 32 memory, how big are the registers of an Accumulator, program counter, instruction, temporary register, address register, data ...
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3answers
94 views

Finding Instruction Count

Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz. Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. We have a particular program we wish to run. When ...
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1answer
68 views

implementing direct addressing mode for a load instruction on a mips archtitecture

Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows |OPT code|rs|rd|immediate| |6 bits |5 bits|5 bits|16 bits| The OPT code is the ...
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0answers
101 views

Calculate Instructions per second MIPS

I'm trying to solve this problem for a MIPS processor: Suppose the data cache is perfect but the instruction cache has a 5% miss rate. On a cache miss, the processor stalls for 20 ns to access main ...
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1answer
244 views

CPU Execution Time / Performance

I'm trying to solve a question concerning performance. I have the final answer (24 * 10^9)but I can't determine how to get there. I know the formula for performance is Execution time: CPI * I * ...
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0answers
94 views

How to compare processor speeds based on architexture

Is there any rule-of-thumb for comparing processor speed based on architecture? I'm researching single-board computers, and I'm trying to compare ones using ARM processors (e.g. Beaglebone Black, ...
0
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1answer
50 views

Spread spectrum 400 KHz

I got a 6-phase DC-DC converter. Fsw=400 kHz, synchronization by external clock(CPLD). I need a spread spectrum 400 kHz. What's the best way? All chips what I've seen before worked on MHz and above. ...
2
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3answers
105 views

Curious how does ALU addressing work like in Assembly code?

When writing assembly code, say R1 = R2 + R3, it is pretty easy to understand the addressing procedure because all registers are close to the ALU. But I find it hard to see how does the ALU go to the ...
0
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2answers
368 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
0
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0answers
58 views

How to implement a pipelined integer divider

I need to implement a pipelined integer divider for my 64-bit microprocessor. I have tried reading up on this, but I am still confused. Any advice would be appreciated.
3
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6answers
439 views

How to implement an 8-bit CPU?

I'm trying to create a CPU, using 8-bit instructions, and there will be 9 or 10 of them. I have an add, subtract, multiply, load, store, branch if zero, branch if not zero, print (to display), input ...
4
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2answers
1k views

How does a ps2 mouse send data to a computer? [closed]

I want to read data from a mouse with the help of Arduino. I want to calculate relative motion between two objects. My questions are 1) Is it possible? 2) How is mouse interfaced with Arduino?
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1answer
274 views

Calculate Speedup

What is the overall speedup of a system spending 65% of its time on I/O with a disk upgrade that provides for 50% greater throughput. The formula should be Amdahl's law: overall speedup = 1 / (1 ...
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0answers
44 views

How can I connect this ram-ish memory layout

In the picture on the web, I want to connect the two inverters that are ringing around each other, I want to connect them to the data-line. I can't seem to figure out how to properly connect them in ...
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3answers
185 views

How to make the hottest CPU temperature?

Besides just running an infinite loop, are there any tricks (like maybe cache misses?) to making a CPU as hot as possible? This could be architecture specific or not.
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1answer
240 views

Use of $at register in MIPS?

Register r1 or $at, is it's sole use in pseudoinstructions? If so, is this the sole solution to enable pseudoinstructions within the architecture?