Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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Fractional Decimal to Base7 Conversion with Radix Points?

I was hoping someone on here could help explain Decimal to Base7 conversions with Radix points. I'm pursuing my Bachelors Degree in Computer Science with 12 courses remaining, currently in a Computer ...
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2answers
44 views

Decimal-Binary-Hex-Base7 Conversions with Radix Points?

I was hoping someone on here could help explain number base conversions with Radix points. I'm pursuing my Bachelors Degree in Computer Science with 12 courses remaining, currently in a Computer ...
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2answers
48 views

Average Cycles Per Instruction

We have two different computers with the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. Computer M1 has a clock rate of 80 MHz and Computer M2 has ...
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20 views

Calculating Cpi with Miss Rate

In my assignment I have the following question: The processor has a clock rate of 1 GHZ. The miss rate in the instruction cache is 1.5%. The miss rate in the data cache is 4%. 30% of the instruction ...
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1answer
60 views

Why do dual-rank DIMMs have twice the bandwidth of quad-rank DIMMs? [closed]

I'm looking at the RAM compatibility table for my motherboard: and it shows that dual-rank (DRx4) memory modules can operate at twice the speed of quad-rank (QRx4) memory modules (1600 MT/s vs 800 ...
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105 views

Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [closed]

The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates. In the first year of Make Magazine - they describe a person who builds a simple ...
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2answers
69 views

How do I hold a signal high from one high pulse?

Assuming I send a signal wirelessly to a receiver connected to a fan. if the receiver detects that a pulse is there, it switches on the fan. the fan should stay on until it detects another high pulse, ...
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1answer
76 views

Three way set associative cache with LRU replacement

So I am going through a homework exercise, and I am not understanding the solution to the problem. We are given a sequence of memory references and we are to use a three-way set associative cache with ...
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4answers
2k views

How can a CPU deliver more than one instruction per cycle?

Wikipedia's Instructions per second page says that an i7 3630QM deliver ~110,000 MIPS at a frequency of 3.2 GHz; it would be (110/3.2 instructions) / 4 core = ~8.6 instructions per cycle per ...
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1answer
199 views

Why does Intel produce core i3, core i5 and core i7 processors; but not core i2, core i4 or core i6 processors? [closed]

Why does Intel produce core i3, core i5 and core i7 processors; but not core i2, core i4 or core i6 processors? What is the reason behind this?
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2answers
163 views

Suggestions for Ternary Computer Parts

I am thinking of creating a ternary computer from scratch, mostly as a hobby project, are there any parts out there that I could use? Or would I have to create them from scratch? If so, what would be ...
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1answer
222 views

Were can I find a simple CPU Design tutorial / book? [closed]

I basically want to know how to make(In hardware and in a simulator) a simple CPU. A book that covers low level stuff like, like logic gates, and more high level stuff like a complete CPU. Ive tried ...
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57 views

Pipelining and Branches (MIPS)

I'm having some trouble determining how to figure out which cycle these instructions are in for the following question: For each instruction show which stage of the traditional MIPS five-stage ...
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3answers
177 views

Is a digital bit represented by any two discrete signals?

I am trying to understand computers from the building blocks up. I know computers use transistors to amplify voltages, and this is used for arithmetic, such as a MOSFET. However, what really makes ...
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5answers
987 views

“Halt and Catch Fire” BIOS cloning scene unrealistic?

The first episode of the TV series "Halt and Catch Fire" (inspired by the early days of Compaq) has two characters starting to clone the IBM PC BIOS in 1983 by creating a circuit that would display ...
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1answer
61 views

How is the zero flag set in terms of hardware? [duplicate]

I'm angling this as a general question on the assumption that it doesn't differ significantly with architecture - at least at the level I'm asking. I'm curious how - in terms of hardware, not the ...
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2answers
428 views

CPUs for retro computer school project

I'm a student in an IT school and we are trying to think of a project we could use to show 1st year students how things work behind the stage and we eventually thought of making a retro computer. ...
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0answers
71 views

Are there any registers that are read_clear in PC devices?

As we know, in x86 PC devices, there are some kinds of registers that are write_clear, that is, if we write "1" to the register, the register will be cleared. So I want to know if there are any ...
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1answer
154 views

Choice of number of chip select pins in a RAM

I was going through Mano's "Computer architecture " , in chapter memory organization they have used a RAM chip with 2 chip select pins CS1 and CS2' but i can't think of the reason why , all the chip ...
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1answer
75 views

Timing on a pipeline

I'm basically reviewing for a test in my computer organization class and there's a question about pipelining. The questions is: "If the pipeline consists of 6 stages and each stage executes its ...
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8answers
190 views

Why can computer circuits recognise only two states?

Computers can only understand binary (that is 0s or 1s). I want to know Is there any way that computers can understand more than 2 states. I know that It is much harder to build components that use ...
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1answer
68 views

misunderstanding of a Computer Architecture

I have the following architecture , and the timing diagram below . my question is , it's seem that no 'relation' or dependency between control logic and Extender , but at timing diagram , the time of ...
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1answer
41 views

SATA in Samsung Exynos

Please take a look at the picture below. You can see that Samsung integrates SATA 3 into the Exynos 5 Dual. So does that mean that smartphones which use Exynos 5 will be able to connect to hard ...
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49 views

Sparse and dense branch prediction

In the context of branch prediction in a computer architecture, what are sparse and dense branch predictors? There seem to be no resources about these terms on the internet.
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2answers
49 views

What are the basics of using ROM-based controller in lieu of discrete logic

In Computer Architecture and Organization, how can one use ROM-based controllers instead of discrete logic? My teacher explained a bit, but I can't find any details anywhere online (well, I looked on ...
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1answer
175 views

What does banking mean when applied to registers?

This answer to a question on StackOverflow about what banking means in the context of ARM's banked registers indicates that there is some confusion about the meaning of banking when applied to ...
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2answers
394 views

CPU Cache implementation in VHDL

I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL. I know the required theory for carrying out this ...
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1answer
90 views

What happens if a process needs more pages than number of entries in page table?

I am having a little trouble understanding the concept of paging. Below is a simple example to illustrate my question. Suppose main memory has 128 bytes, organized into 32 pages of size 4 bytes each, ...
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56 views

How does a software intruction materialise to hardware action? [duplicate]

Please feel free to rephrase / reinterpret the question. Rephrased - RM: How does a program which can be represented by high level language commands or opcodes or a series of 1's and 0's get ...
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1answer
121 views

Why do we use (0,+V) in digital electronics (eg processors) instead of (-V/2,+V/2)? [closed]

Would making the default voltages for 0 and 1 where relevant +|- V/2 save 1/2 power?
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1answer
44 views

How is the Second level of Cache Accessed

Since the processors have more than one level f memory, how is the 2nd level of Cache accessed. i.e., Access both the first level of Cache and 2nd level are Cache are accessed at the same time. If ...
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2answers
100 views

What happens on a Cache miss?

In the present day processors more than one level of memory is present for trying for the realization of an ideal memory system and to do more work for clock cycle more than one instruction is in the ...
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1answer
113 views

what is microcoded architecture in computer architecture

I want to know what is microcoded microarchitecture of an instruction set architecture (ISA) and why is it used? What is the difference between microcoded architecture and single cycle ...
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1answer
141 views

Question about an Intel USB Host Controller power supplied per USB port

I had a general question regarding the Intel(R) 82801FB/FBM USB Universal Host Controller (ICH6). The ICH6 has five USB Host controllers in it, with (I'm assuming) two physical USB ports per ...
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1answer
63 views

Computer Architect Book Reccomendation [closed]

Best Book For Computer Architect , As I have to build SAP this semester. Most people told me it is very difficult to make a SimpleAsPossible 8 bit Computer up and running therefore any suggestions ...
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2answers
108 views

Should “get new sensor data” be its own task in an RTOS?

I am new to RTOS coding practices/architectures, and am specifically learning on RTX. Should I have a get_new_sensor_data task for each sensor, or is sensor data usually taken care of by some other ...
5
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3answers
237 views

Clocked edge-triggered timing (contamination delay)

I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
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1answer
91 views

Choosing Altera Quartus II clock rate for stopper

I'm using Altera Quartus II to built a stopper. I'm using 2 counters and I need to choose the right clock rate to get pulse every 1 sec. There are only two options in Quartus for the clock: 27Mhz and ...
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1answer
334 views

Why do we need the MOESI/MESIF protocols?

As I understand, those two protocols add an extra state to identify which cache should respond to a miss request from another cache for a particular cache-line. But, in the MESI protocol, only one ...
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38 views

Is my interpretation of this problem regarding a 7-word mux correct?

I have a problem on an assignment which states to draw a block diagram for a 7-word MUX and determine how many control switches it should have. I'm not exactly sure what the problem means by "7-Word." ...
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103 views

Virtual Memory, Cache, and TLB's

I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question. I'm trying to study for an exam ...
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1answer
158 views

Building a simple PC - looking for a CPU [closed]

I would like to build a computer. It is a child's dream that I had and now that I am at college, I finally gain the knowledge I need. I want it to be simple. I admire the early designs of 1990's ...
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2answers
134 views

Programming microcontrollers in ASM or C & how it's done

Just to clarify on these topics: If I were to program a microcontroller in ASM I would use an assembler, of course. The assembler would compile the code into opcodes (machine code?)(generally 1:1 ...
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1answer
141 views

What software to graphically design a simple schematic? [duplicate]

I need to draw a schematic similar to that shown in the figure attached in this question. Are there softwares that allow to graphically design a schematic like that?
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1answer
256 views

What does “CL” stand for in this processor architecture block diagram?

I'm learning about pipelining but can't understand this abbreviation: "CL". You can see it in processors' schemes. It is shown with with and without a line above it; what is the line for? Diagram ...
4
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3answers
685 views

How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency?

I am not new to computer architecture but I have only academic experience with micro-architecture implementation. I have heard and read this many times but never really bothered to understand the ...
2
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1answer
89 views

Memory Organization in Computer

How is memory stored in a computer? Is it 1 bit per address so in order to get the value of an integer (32 bits) it must go through 32 addresses, get all the bits of 0's and 1's? I am a bit confused ...
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0answers
145 views

How does a computer work? [closed]

I am a software programmer.I am very much curious to know about the behind the scenes of how actually a computer works. By HOW I mean:On the hardware level. My knowledge about software programming ...
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1answer
633 views

How many bits are used for the tag, block, and offset fields for the representation of a memory address?

A small byte-addressable embedded computer system, with a word length of 32 bits, has a main memory consisting of 4 KBytes. It also has a small data cache capable of holding eight 32-bit words, ...
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1answer
533 views

What are ALMs, LEs and ALUTs?

Does ALM mean "Adaptive logic module"? www.altera.com/literature/ds/ds_nios2_perf.pdf‎ Jul 1, 2013 - One ALUT is equivalent to about 1.25 LEs. Does LE mean logic element and ALUT means ...