Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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Difference between multiple pipelines and superscalar?

I have read some threads and the wiki articles, but still don't seem to understand what exactly the difference is between having multiple parallel pipelines and the superscalar architecture. I know ...
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2answers
64 views

Simplifying Circuits

I have a question regarding simplifying a circuit of a function below that has 5 logic gates in original. f = (A + B) * (C + D) + (A + B) * (C + D)' + C = (A + B) * ((C + D) + (C + D)') + C = (A ...
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6answers
2k views

How to efficiently design the opcode for a CPU?

I am building a simple 16-bit CPU in Logisim and have the ALU ready and the opcodes that I want to have. Now I find it really hard to find the right coding for the commands so that the different ...
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100 views

Why does the A8 have twice as many transistors than the Haswell processor yet runs on less power?

There's something I don't get - I am always under the impression that the more transistors we pack in, the more energy it consumes and the hotter it gets (assuming we haven't shrunk the die). However, ...
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103 views

Booth multiplication algorithm, why it works?

Just learned about Booth's multiplication algorithm, and from what I understand if the multiplier least significant bit (MLB) is equal to the previous significant bit in that multiplier (MPLB) then we ...
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141 views

Where is the best place I can go to learn everything about the electronics-side of computers? [closed]

Throughout my childhood, I grew up learning about electronics and computers. I am starting to get to the point where I want to incorporate my knowledge of both into a single project. I have tried ...
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2answers
77 views

You need at least four states to exploit the advantages of a Mealy machine over a Moore machine

What's meant by this question? "You need at least four states to exploit the advantages of a Mealy machine over a Moore machine." I'm trying to wrap my head around this but I'm not sure "what" ...
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1answer
72 views

Inherent exploitability and power state machines

I'm working on understanding power state machines in regard to mobile computing devices. Most of the information on this subject seems to stem from this article. It's not particularly important to the ...
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1answer
120 views

Determining memory address width from memory size

Given a computer A with 1024 x 16 memory and a computer B with 16K x 32 memory, how big are the registers of an Accumulator, program counter, instruction, temporary register, address register, data ...
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3answers
68 views

Finding Instruction Count

Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz. Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. We have a particular program we wish to run. When ...
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1answer
53 views

implementing direct addressing mode for a load instruction on a mips archtitecture

Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows |OPT code|rs|rd|immediate| |6 bits |5 bits|5 bits|16 bits| The OPT code is the ...
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0answers
50 views

Calculate Instructions per second MIPS

I'm trying to solve this problem for a MIPS processor: Suppose the data cache is perfect but the instruction cache has a 5% miss rate. On a cache miss, the processor stalls for 20 ns to access main ...
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1answer
67 views

CPU Execution Time / Performance

I'm trying to solve a question concerning performance. I have the final answer (24 * 10^9)but I can't determine how to get there. I know the formula for performance is Execution time: CPI * I * ...
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0answers
75 views

How to compare processor speeds based on architexture

Is there any rule-of-thumb for comparing processor speed based on architecture? I'm researching single-board computers, and I'm trying to compare ones using ARM processors (e.g. Beaglebone Black, ...
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1answer
46 views

Spread spectrum 400 KHz

I got a 6-phase DC-DC converter. Fsw=400 kHz, synchronization by external clock(CPLD). I need a spread spectrum 400 kHz. What's the best way? All chips what I've seen before worked on MHz and above. ...
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3answers
75 views

Curious how does ALU addressing work like in Assembly code?

When writing assembly code, say R1 = R2 + R3, it is pretty easy to understand the addressing procedure because all registers are close to the ALU. But I find it hard to see how does the ALU go to the ...
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1answer
132 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
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0answers
45 views

How to implement a pipelined integer divider

I need to implement a pipelined integer divider for my 64-bit microprocessor. I have tried reading up on this, but I am still confused. Any advice would be appreciated.
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6answers
306 views

How to implement an 8-bit CPU?

I'm trying to create a CPU, using 8-bit instructions, and there will be 9 or 10 of them. I have an add, subtract, multiply, load, store, branch if zero, branch if not zero, print (to display), input ...
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2answers
851 views

How does a ps2 mouse send data to a computer? [closed]

I want to read data from a mouse with the help of Arduino. I want to calculate relative motion between two objects. My questions are 1) Is it possible? 2) How is mouse interfaced with Arduino?
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0answers
130 views

Calculate Speedup

What is the overall speedup of a system spending 65% of its time on I/O with a disk upgrade that provides for 50% greater throughput. The formula should be Amdahl's law: overall speedup = 1 / (1 ...
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0answers
42 views

How can I connect this ram-ish memory layout

In the picture on the web, I want to connect the two inverters that are ringing around each other, I want to connect them to the data-line. I can't seem to figure out how to properly connect them in ...
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3answers
168 views

How to make the hottest CPU temperature?

Besides just running an infinite loop, are there any tricks (like maybe cache misses?) to making a CPU as hot as possible? This could be architecture specific or not.
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1answer
76 views

Use of $at register in MIPS?

Register r1 or $at, is it's sole use in pseudoinstructions? If so, is this the sole solution to enable pseudoinstructions within the architecture?
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0answers
32 views

Help with harder version of carry chain adder?

I am designing an addr circuit given cin = 0, given a nand of the operands i want to add, their xor, and nor. I have drawn it in a software but i am not getting the right output, i have tried to ...
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1answer
136 views

Calculate Paging System

I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it. A paging system has the following parameters: 2^32 bytes of physical memory; page size of ...
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1answer
83 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
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2answers
108 views

I need help with verilog code, I am in trouble?

I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
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1answer
41 views

How should this code look like in verilog?

I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
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4answers
128 views

2-bit branch prediction accuracy

I am trying to solve this problem, the answer should be 15/20 = 75%. However, I am not sure how this was calculated and want to understand the underlying concept. A program core consists of five ...
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0answers
8 views

2-bit branch prediction accuracy [duplicate]

I am trying to solve this problem, the answer should be 15/20 = 75%. However, I am not sure how this was calculated and want to understand the underlying concept. A program core consists of five ...
0
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0answers
50 views

Virtually indexed physically tagged cache

I'm trying to understand the concept and calculations for solving this problem. I know the answer is 10 bits. ...
2
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1answer
92 views

What could this PLA be doing?

The picture below shows a PLA, I have done part (a) and found out that; $$ F_0 = A_0 \mathbin{\oplus} B_0 \\ F_1 = A_0B_0 + (\overline{A_0} + \overline{B_0})(A_1 \mathbin{\oplus} B_1) \\ F_2 = ...
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0answers
57 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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1answer
100 views

5-stage pipelined implementation (RISC) of a microprocessor

I'm trying to solve two questions about a RISC 5-staged pipeline that is not exactly like MIPS found here (everything is included in this post). Consider the non-pipelined implementation of a simple ...
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1answer
81 views

ISA efficiency code compaction and memory traffic

I'm having issues understanding this problem and am new to ISA's. Here's a problem with 3 questions and my biggest question is, what is supposed to happen? Specifically, the HLL Code at the bottom. ...
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1answer
54 views

How do you reduce an 8 output ALU to a 4 or 3 output ALU?

I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...
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1answer
82 views

Modify MEMORY component to more sensibly Load/Store value?

I have created the following electrical circuit using Logisim: My ALU takes in 2 8-bit values and performs the operation set forth by the [Op Setter]. In particular, when the [Op] code is [100], ...
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2answers
99 views

Can I use the 12V line of a computer PSU to power my circuits?

Or is there any issues I should be wary of? I need at least 7A on a 12V line, but I've found that a computer PSUs are significantly cheaper.
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1answer
117 views

How do you store A or B in a RAM of a CPU datapath?

I have an assignment to make a CPU, but am confused with how f_left and f_right are going to be used. I think they are to store ...
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1answer
194 views

Connect ALU to CPU in Logism Circuit Design and output to 7-segment Display?

I've been playing around in Logisim to get some experience in designing basic electrical circuits. While I'm sure not the best, I was able to put together a functional ALU: 1-Bit: This ALU is ...
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2answers
154 views

Where can I find common circuitry implementations of different computer system components?

Mostly out of interest, I'm trying to understand common circuit-level implementations of computer components. I understand that implementations may differ widely, but I'd like to see examples. It ...
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0answers
17 views

Fractional Decimal to Base7 Conversion with Radix Points? [duplicate]

I was hoping someone on here could help explain Decimal to Base7 conversions with Radix points. I'm pursuing my Bachelors Degree in Computer Science with 12 courses remaining, currently in a Computer ...
0
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3answers
166 views

Decimal-Binary-Hex-Base7 Conversions with Radix Points?

I was hoping someone on here could help explain number base conversions with Radix points. I'm pursuing my Bachelors Degree in Computer Science with 12 courses remaining, currently in a Computer ...
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2answers
74 views

Average Cycles Per Instruction

We have two different computers with the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. Computer M1 has a clock rate of 80 MHz and Computer M2 has ...
0
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1answer
82 views

Calculating Cpi with Miss Rate

In my assignment I have the following question: The processor has a clock rate of 1 GHZ. The miss rate in the instruction cache is 1.5%. The miss rate in the data cache is 4%. 30% of the instruction ...
0
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1answer
76 views

Why do dual-rank DIMMs have twice the bandwidth of quad-rank DIMMs? [closed]

I'm looking at the RAM compatibility table for my motherboard: and it shows that dual-rank (DRx4) memory modules can operate at twice the speed of quad-rank (QRx4) memory modules (1600 MT/s vs 800 ...
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2answers
202 views

Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [closed]

The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates. In the first year of Make Magazine - they describe a person who builds a simple ...
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2answers
82 views

How do I hold a signal high from one high pulse?

Assuming I send a signal wirelessly to a receiver connected to a fan. if the receiver detects that a pulse is there, it switches on the fan. the fan should stay on until it detects another high pulse, ...
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1answer
428 views

Three way set associative cache with LRU replacement

So I am going through a homework exercise, and I am not understanding the solution to the problem. We are given a sequence of memory references and we are to use a three-way set associative cache with ...