Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

learn more… | top users | synonyms

0
votes
0answers
47 views

When designing a processor for a particular application, how does one determine the instruction set?

When processor is designed specifically for lets say graphics application and I am sure there are other examples, the instruction set of the processor is designed to contain specific instructions that ...
0
votes
1answer
74 views

How much faster would optical computation be?

If (when) we could figure out a way to do computations with light as opposed to electrons within circuits, how much faster would our computers be?
0
votes
0answers
60 views

Floating point multiplication

I'm trying to understand how to implement a floating point multiplier. In order to do that i've looked up at three books where basically the issue is threated in the same way (i.e. not handling of the ...
2
votes
2answers
60 views

Are neuromorphic computers considered digital computers?

This might be a pretty simple question, but I am wondering if neuromorphic computers using non Von Neumann architectures such as the IBM TrueNorth chip are still considered digital computers. I have ...
0
votes
2answers
26 views

How can you have immediates in the SUBLEQ one instruction computer?

I'm thinking about making a SUBLEQ based CPU on FPGA. SUBLEQ (subtract and branch if less than or equal to zero) is an instruction which is universal. However, how can you have immediates/constants ...
0
votes
0answers
30 views

Processor does fetch, decode, execute, memory read/write and register read/write. How can this result in more than 5 pipeline stages?

I have read this marvelous book on processor architecture. It teaches that: The classic RISC pipeline comprises: ...
0
votes
0answers
11 views

ALUOP for a single cycle datapath control

When designing a single cycle data path control unit using PLA (main control and ALU control) My question is how do I choose the ALUop bits and how to make its truth table for each instruction and ...
0
votes
2answers
71 views

Is it OK to use the USB 5v pin as power source?

I am doing some stuff in my case and I need a power source for one LED from inside my case. I looked up and there are two +5v pins on a USB header inside my case. Is it OK to use them as power ...
1
vote
0answers
30 views

find cache hit rate for direct mapped cache memory

I have this practice exam problem which I am having trouble with. I have gone over many slides but haven't been able to really get it. The question is I currently have an 8 block main memory with ...
1
vote
1answer
29 views

single cycle vs multicycle datapath execution times

I have a question where I need to calculate the execution time for a program for single cycle and multicycle datapath. I think I may be doing it incorrectly since the multicycle execution time is ...
-2
votes
2answers
180 views

Are only word sizes used as structural elements in machine computation?

Research: I have been looking for some time online. everything i know in-fact. ive liked sparse matrix representations, i have found gate level sharing optimization after 'formula reduction' and ...
0
votes
1answer
37 views

Two dimensional 512 byte (byte addressable) RAM from 16 byte chips

Assume it is decided to design a two dimensional 512 byte (byte addressable) RAM from 16 byte chips. Each of the 16 byte chips has two select-lines. The chip is enabled only if both of the ...
1
vote
1answer
83 views

multicycle datapath vs single cycle datapath

I have a fairly simple question but have not been able to find a good answer googling. I understand how pipelining works by having 1 cycle per step, each instruction takes 5 cycles and they start ...
10
votes
4answers
2k views

How many clock cycles does a RISC/CISC instruction take to execute?

According to Digital Design and Computer Architecture by Harris and Harris, there are several ways to implement a MIPS processor, including the following: The single-cycle microarchitecture ...
0
votes
1answer
48 views

is it possible to mix chipsets

I'm designing a home made game console motherboard, and want to integrate the ATI Mobility Radeon 9000 GPU in it. The problem is, the Northbridge I picked only supports PCI Express, and the GPU uses ...
0
votes
0answers
31 views

Learning Booth's Algorithm, I Can't Find the Issue on Final Result

I am practicing using Booth's algorithm to multiply a positive number and a negative number (specifically -12 * 4). I have included my attempt, but i can't find the issue. If someone can help me out, ...
0
votes
0answers
40 views

Secondary Level address translation (EPT/RVI) TLB implementation

hope this is the right place to ask for the following: Consider a processor/cpu with support for Secondary Level address translation (SLAT) technology (Intel EPT/AMD RVI). TLB caching is used to ...
0
votes
1answer
130 views

What is happening in the diagram of LC3?

This is a diagram of the LC3 Computer I am trying to understand what is happening in the parts I highlighted. The part I had highlighted had the instruction bit sign extended to 16 bits and then ...
1
vote
3answers
74 views

Benefit of (logically/virtually) separate I/O and memory bus

In my course on embedded systems, it is explained that memory inputs can be separated from I/O inputs using a "mode bit" for the address decoder. The most obvious advantage of this is that the amount ...
1
vote
1answer
41 views

Simple Mux Equation finding, need help?

How we can find the equation of following simple diagram ? My TA solved it as : C.Not(B).A + B.Not(A)
0
votes
2answers
65 views

Is it possible to simulate hardware of MIPS architecture computer defined using Verilog/VHDL?

I am reading Digital Design and Computer Architecture book and if I will be persistent then I will have MIPS architecture computer at the end, implemented from scratch by me . I wonder is it ...
1
vote
1answer
303 views

Micro and Nano Memory, Calculate Reducing Bits?

I ran into a question: in digital system with micro-programmed control circuit, total of 32 distinct pattern operation signal is ...
0
votes
1answer
28 views

Which are the spec bits in this cache?

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. The physical address is 50 bits, numbered from 0 to 49 (with 0 being the least significant ...
3
votes
3answers
123 views

Logical Design Operation, A Simple Questions?

I'm so sorry if I ask my first question that so simple. My filed is Math and Computer science. I self-study Digital Design. My challenge is how we can find the operation of the two following ...
0
votes
1answer
28 views

What is the difference between a virtually tagged and a physically tagged memory system?

I study computer architecture and this question came. What is the difference between a virtually tagged and a physically tagged memory system?
3
votes
1answer
98 views

adding two 64-bits number with m-bit carry ripple adder and multiplexer, a questions?

I ran into a question from computer architecture class. The professor says that for adding two 64-bit numbers A and B we use m-bit carry ripple adders and multiplexers such as following: and that ...
1
vote
0answers
23 views

Where can I find literature on PCMOS (Probabilistic CMOS)

PCMOS is relatively new technology and I'd like to learn more about its inner workings. I have managed to find couple of papers on PCMOS on google scholar but they are all from 2006-8 so I was ...
-4
votes
1answer
68 views

Logic Gate Cookbook [closed]

Is there a concise book that brings together all of the different Logic devices that can be implemented with basic logic gates? I have several digital/computer architecture books that have the ...
1
vote
1answer
104 views

How the lw (load word) instruction works on the MIPS Unicycle (Implementation)

I'm reading the Computer Organization and Design book from David A. Patterson and John L. Hennessy. Specifically, I have a question about the implementation of a MIPS Unicycle. So, in the book, they ...
0
votes
3answers
162 views

How Can A Coded Firmware Control Hardware [closed]

I really want to know how could a virtual coded program really affect and imitate and animate a piece of hardware. I Have Always Seen The Diagram Of Processors In the Book Showing ALU and CPU as The ...
0
votes
1answer
53 views

Difference between multiple pipelines and superscalar?

I have read some threads and the wiki articles, but still don't seem to understand what exactly the difference is between having multiple parallel pipelines and the superscalar architecture. I know ...
2
votes
2answers
76 views

Simplifying Circuits

I have a question regarding simplifying a circuit of a function below that has 5 logic gates in original. f = (A + B) * (C + D) + (A + B) * (C + D)' + C = (A + B) * ((C + D) + (C + D)') + C = (A ...
10
votes
6answers
2k views

How to efficiently design the opcode for a CPU?

I am building a simple 16-bit CPU in Logisim and have the ALU ready and the opcodes that I want to have. Now I find it really hard to find the right coding for the commands so that the different ...
0
votes
1answer
122 views

Why does the A8 have twice as many transistors than the Haswell processor yet runs on less power?

There's something I don't get - I am always under the impression that the more transistors we pack in, the more energy it consumes and the hotter it gets (assuming we haven't shrunk the die). However, ...
1
vote
2answers
194 views

Booth multiplication algorithm, why it works?

Just learned about Booth's multiplication algorithm, and from what I understand if the multiplier least significant bit (MLB) is equal to the previous significant bit in that multiplier (MPLB) then we ...
-2
votes
2answers
181 views

Where is the best place I can go to learn everything about the electronics-side of computers? [closed]

Throughout my childhood, I grew up learning about electronics and computers. I am starting to get to the point where I want to incorporate my knowledge of both into a single project. I have tried ...
0
votes
2answers
94 views

You need at least four states to exploit the advantages of a Mealy machine over a Moore machine

What's meant by this question? "You need at least four states to exploit the advantages of a Mealy machine over a Moore machine." I'm trying to wrap my head around this but I'm not sure "what" ...
2
votes
1answer
109 views

Inherent exploitability and power state machines

I'm working on understanding power state machines in regard to mobile computing devices. Most of the information on this subject seems to stem from this article. It's not particularly important to the ...
0
votes
1answer
450 views

Determining memory address width from memory size

Given a computer A with 1024 x 16 memory and a computer B with 16K x 32 memory, how big are the registers of an Accumulator, program counter, instruction, temporary register, address register, data ...
0
votes
3answers
101 views

Finding Instruction Count

Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz. Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. We have a particular program we wish to run. When ...
1
vote
1answer
70 views

implementing direct addressing mode for a load instruction on a mips archtitecture

Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows |OPT code|rs|rd|immediate| |6 bits |5 bits|5 bits|16 bits| The OPT code is the ...
0
votes
0answers
106 views

Calculate Instructions per second MIPS

I'm trying to solve this problem for a MIPS processor: Suppose the data cache is perfect but the instruction cache has a 5% miss rate. On a cache miss, the processor stalls for 20 ns to access main ...
1
vote
1answer
268 views

CPU Execution Time / Performance

I'm trying to solve a question concerning performance. I have the final answer (24 * 10^9)but I can't determine how to get there. I know the formula for performance is Execution time: CPI * I * ...
1
vote
0answers
97 views

How to compare processor speeds based on architexture

Is there any rule-of-thumb for comparing processor speed based on architecture? I'm researching single-board computers, and I'm trying to compare ones using ARM processors (e.g. Beaglebone Black, ...
0
votes
1answer
51 views

Spread spectrum 400 KHz

I got a 6-phase DC-DC converter. Fsw=400 kHz, synchronization by external clock(CPLD). I need a spread spectrum 400 kHz. What's the best way? All chips what I've seen before worked on MHz and above. ...
2
votes
3answers
108 views

Curious how does ALU addressing work like in Assembly code?

When writing assembly code, say R1 = R2 + R3, it is pretty easy to understand the addressing procedure because all registers are close to the ALU. But I find it hard to see how does the ALU go to the ...
0
votes
2answers
401 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
0
votes
0answers
63 views

How to implement a pipelined integer divider

I need to implement a pipelined integer divider for my 64-bit microprocessor. I have tried reading up on this, but I am still confused. Any advice would be appreciated.
3
votes
6answers
457 views

How to implement an 8-bit CPU?

I'm trying to create a CPU, using 8-bit instructions, and there will be 9 or 10 of them. I have an add, subtract, multiply, load, store, branch if zero, branch if not zero, print (to display), input ...
4
votes
2answers
1k views

How does a ps2 mouse send data to a computer? [closed]

I want to read data from a mouse with the help of Arduino. I want to calculate relative motion between two objects. My questions are 1) Is it possible? 2) How is mouse interfaced with Arduino?