Tagged Questions

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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memory mapped I/O or I/O mapped I/O in ATM systems [on hold]

memory mapped I/O or I/O mapped I/O, which one is used in ATM? and why?
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0answers
27 views

Help with harder version of carry chain adder?

I am designing an addr circuit given cin = 0, given a nand of the operands i want to add, their xor, and nor. I have drawn it in a software but i am not getting the right output, i have tried to ...
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1answer
32 views

Calculate Paging System

I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it. A paging system has the following parameters: 2^32 bytes of physical memory; page size of ...
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1answer
59 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
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2answers
63 views

I need help with verilog code, I am in trouble?

I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
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1answer
33 views

How should this code look like in verilog?

I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
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4answers
41 views

2-bit branch prediction accuracy

I am trying to solve this problem, the answer should be 15/20 = 75%. However, I am not sure how this was calculated and want to understand the underlying concept. A program core consists of five ...
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0answers
6 views

2-bit branch prediction accuracy [duplicate]

I am trying to solve this problem, the answer should be 15/20 = 75%. However, I am not sure how this was calculated and want to understand the underlying concept. A program core consists of five ...
0
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0answers
23 views

Virtually indexed physically tagged cache

I'm trying to understand the concept and calculations for solving this problem. I know the answer is 10 bits. ...
2
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0answers
52 views

What could this PLA be doing?

The picture below shows a PLA, I have done part (a) and found out that; F0 = A0 xor B0 F1 = A0B0 + (A0' + B0')(A1 xor B1) F2 = A0B0(A1 + B1) + A1B1 What may this circuit be doing, I can't see a ...
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0answers
41 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
0
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1answer
63 views

5-stage pipelined implementation (RISC) of a microprocessor

I'm trying to solve two questions about a RISC 5-staged pipeline that is not exactly like MIPS found here (everything is included in this post). Consider the non-pipelined implementation of a simple ...
0
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1answer
52 views

ISA efficiency code compaction and memory traffic

I'm having issues understanding this problem and am new to ISA's. Here's a problem with 3 questions and my biggest question is, what is supposed to happen? Specifically, the HLL Code at the bottom. ...
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1answer
48 views

How do you reduce an 8 output ALU to a 4 or 3 output ALU?

I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...
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vote
1answer
44 views

Modify MEMORY component to more sensibly Load/Store value?

I have created the following electrical circuit using Logisim: My ALU takes in 2 8-bit values and performs the operation set forth by the [Op Setter]. In particular, when the [Op] code is [100], ...
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2answers
66 views

Can I use the 12V line of a computer PSU to power my circuits?

Or is there any issues I should be wary of? I need at least 7A on a 12V line, but I've found that a computer PSUs are significantly cheaper.
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1answer
56 views

How do you store A or B in a RAM of a CPU datapath?

I have an assignment to make a CPU, but am confused with how f_left and f_right are going to be used. I think they are to store ...
1
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1answer
38 views

Connect ALU to CPU in Logism Circuit Design and output to 7-segment Display?

I've been playing around in Logisim to get some experience in designing basic electrical circuits. While I'm sure not the best, I was able to put together a functional ALU: 1-Bit: This ALU is ...
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2answers
147 views

Where can I find common circuitry implementations of different computer system components?

Mostly out of interest, I'm trying to understand common circuit-level implementations of computer components. I understand that implementations may differ widely, but I'd like to see examples. It ...
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0answers
17 views

Fractional Decimal to Base7 Conversion with Radix Points? [duplicate]

I was hoping someone on here could help explain Decimal to Base7 conversions with Radix points. I'm pursuing my Bachelors Degree in Computer Science with 12 courses remaining, currently in a Computer ...
0
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3answers
91 views

Decimal-Binary-Hex-Base7 Conversions with Radix Points?

I was hoping someone on here could help explain number base conversions with Radix points. I'm pursuing my Bachelors Degree in Computer Science with 12 courses remaining, currently in a Computer ...
0
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2answers
54 views

Average Cycles Per Instruction

We have two different computers with the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. Computer M1 has a clock rate of 80 MHz and Computer M2 has ...
0
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1answer
27 views

Calculating Cpi with Miss Rate

In my assignment I have the following question: The processor has a clock rate of 1 GHZ. The miss rate in the instruction cache is 1.5%. The miss rate in the data cache is 4%. 30% of the instruction ...
0
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1answer
60 views

Why do dual-rank DIMMs have twice the bandwidth of quad-rank DIMMs? [closed]

I'm looking at the RAM compatibility table for my motherboard: and it shows that dual-rank (DRx4) memory modules can operate at twice the speed of quad-rank (QRx4) memory modules (1600 MT/s vs 800 ...
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2answers
125 views

Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [closed]

The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates. In the first year of Make Magazine - they describe a person who builds a simple ...
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2answers
73 views

How do I hold a signal high from one high pulse?

Assuming I send a signal wirelessly to a receiver connected to a fan. if the receiver detects that a pulse is there, it switches on the fan. the fan should stay on until it detects another high pulse, ...
1
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1answer
90 views

Three way set associative cache with LRU replacement

So I am going through a homework exercise, and I am not understanding the solution to the problem. We are given a sequence of memory references and we are to use a three-way set associative cache with ...
17
votes
4answers
3k views

How can a CPU deliver more than one instruction per cycle?

Wikipedia's Instructions per second page says that an i7 3630QM deliver ~110,000 MIPS at a frequency of 3.2 GHz; it would be (110/3.2 instructions) / 4 core = ~8.6 instructions per cycle per ...
0
votes
1answer
253 views

Why does Intel produce core i3, core i5 and core i7 processors; but not core i2, core i4 or core i6 processors? [closed]

Why does Intel produce core i3, core i5 and core i7 processors; but not core i2, core i4 or core i6 processors? What is the reason behind this?
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2answers
180 views

Suggestions for Ternary Computer Parts

I am thinking of creating a ternary computer from scratch, mostly as a hobby project, are there any parts out there that I could use? Or would I have to create them from scratch? If so, what would be ...
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votes
1answer
291 views

Were can I find a simple CPU Design tutorial / book? [closed]

I basically want to know how to make(In hardware and in a simulator) a simple CPU. A book that covers low level stuff like, like logic gates, and more high level stuff like a complete CPU. Ive tried ...
1
vote
0answers
59 views

Pipelining and Branches (MIPS)

I'm having some trouble determining how to figure out which cycle these instructions are in for the following question: For each instruction show which stage of the traditional MIPS five-stage ...
1
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3answers
191 views

Is a digital bit represented by any two discrete signals?

I am trying to understand computers from the building blocks up. I know computers use transistors to amplify voltages, and this is used for arithmetic, such as a MOSFET. However, what really makes ...
3
votes
5answers
1k views

“Halt and Catch Fire” BIOS cloning scene unrealistic?

The first episode of the TV series "Halt and Catch Fire" (inspired by the early days of Compaq) has two characters starting to clone the IBM PC BIOS in 1983 by creating a circuit that would display ...
1
vote
1answer
68 views

How is the zero flag set in terms of hardware? [duplicate]

I'm angling this as a general question on the assumption that it doesn't differ significantly with architecture - at least at the level I'm asking. I'm curious how - in terms of hardware, not the ...
8
votes
2answers
436 views

CPUs for retro computer school project

I'm a student in an IT school and we are trying to think of a project we could use to show 1st year students how things work behind the stage and we eventually thought of making a retro computer. ...
0
votes
0answers
71 views

Are there any registers that are read_clear in PC devices?

As we know, in x86 PC devices, there are some kinds of registers that are write_clear, that is, if we write "1" to the register, the register will be cleared. So I want to know if there are any ...
2
votes
1answer
174 views

Choice of number of chip select pins in a RAM

I was going through Mano's "Computer architecture " , in chapter memory organization they have used a RAM chip with 2 chip select pins CS1 and CS2' but i can't think of the reason why , all the chip ...
-1
votes
1answer
79 views

Timing on a pipeline

I'm basically reviewing for a test in my computer organization class and there's a question about pipelining. The questions is: "If the pipeline consists of 6 stages and each stage executes its ...
4
votes
8answers
197 views

Why can computer circuits recognise only two states?

Computers can only understand binary (that is 0s or 1s). I want to know Is there any way that computers can understand more than 2 states. I know that It is much harder to build components that use ...
0
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1answer
69 views

misunderstanding of a Computer Architecture

I have the following architecture , and the timing diagram below . my question is , it's seem that no 'relation' or dependency between control logic and Extender , but at timing diagram , the time of ...
0
votes
1answer
43 views

SATA in Samsung Exynos

Please take a look at the picture below. You can see that Samsung integrates SATA 3 into the Exynos 5 Dual. So does that mean that smartphones which use Exynos 5 will be able to connect to hard ...
0
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0answers
49 views

Sparse and dense branch prediction

In the context of branch prediction in a computer architecture, what are sparse and dense branch predictors? There seem to be no resources about these terms on the internet.
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2answers
49 views

What are the basics of using ROM-based controller in lieu of discrete logic

In Computer Architecture and Organization, how can one use ROM-based controllers instead of discrete logic? My teacher explained a bit, but I can't find any details anywhere online (well, I looked on ...
7
votes
1answer
254 views

What does banking mean when applied to registers?

This answer to a question on StackOverflow about what banking means in the context of ARM's banked registers indicates that there is some confusion about the meaning of banking when applied to ...
0
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2answers
433 views

CPU Cache implementation in VHDL

I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL. I know the required theory for carrying out this ...
2
votes
1answer
92 views

What happens if a process needs more pages than number of entries in page table?

I am having a little trouble understanding the concept of paging. Below is a simple example to illustrate my question. Suppose main memory has 128 bytes, organized into 32 pages of size 4 bytes each, ...
0
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0answers
56 views

How does a software intruction materialise to hardware action? [duplicate]

Please feel free to rephrase / reinterpret the question. Rephrased - RM: How does a program which can be represented by high level language commands or opcodes or a series of 1's and 0's get ...
0
votes
1answer
123 views

Why do we use (0,+V) in digital electronics (eg processors) instead of (-V/2,+V/2)? [closed]

Would making the default voltages for 0 and 1 where relevant +|- V/2 save 1/2 power?
0
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1answer
44 views

How is the Second level of Cache Accessed

Since the processors have more than one level f memory, how is the 2nd level of Cache accessed. i.e., Access both the first level of Cache and 2nd level are Cache are accessed at the same time. If ...