Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

learn more… | top users | synonyms

4
votes
8answers
117 views

Why can computer circuits recognise only two states?

Computers can only understand binary (that is 0s or 1s). I want to know Is there any way that computers can understand more than 2 states. I know that It is much harder to build components that use ...
0
votes
1answer
57 views

misunderstanding of a Computer Architecture

I have the following architecture , and the timing diagram below . my question is , it's seem that no 'relation' or dependency between control logic and Extender , but at timing diagram , the time of ...
0
votes
1answer
35 views

SATA in Samsung Exynos

Please take a look at the picture below. You can see that Samsung integrates SATA 3 into the Exynos 5 Dual. So does that mean that smartphones which use Exynos 5 will be able to connect to hard ...
0
votes
0answers
40 views

Sparse and dense branch prediction

In the context of branch prediction in a computer architecture, what are sparse and dense branch predictors? There seem to be no resources about these terms on the internet.
0
votes
2answers
40 views

What are the basics of using ROM-based controller in lieu of discrete logic

In Computer Architecture and Organization, how can one use ROM-based controllers instead of discrete logic? My teacher explained a bit, but I can't find any details anywhere online (well, I looked on ...
4
votes
1answer
43 views

What does banking mean when applied to registers?

This answer to a question on StackOverflow about what banking means in the context of ARM's banked registers indicates that there is some confusion about the meaning of banking when applied to ...
0
votes
2answers
141 views

CPU Cache implementation in VHDL

I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL. I know the required theory for carrying out this ...
2
votes
1answer
66 views

What happens if a process needs more pages than number of entries in page table?

I am having a little trouble understanding the concept of paging. Below is a simple example to illustrate my question. Suppose main memory has 128 bytes, organized into 32 pages of size 4 bytes each, ...
0
votes
0answers
52 views

How does a software intruction materialise to hardware action? [duplicate]

Please feel free to rephrase / reinterpret the question. Rephrased - RM: How does a program which can be represented by high level language commands or opcodes or a series of 1's and 0's get ...
0
votes
1answer
113 views

Why do we use (0,+V) in digital electronics (eg processors) instead of (-V/2,+V/2)? [closed]

Would making the default voltages for 0 and 1 where relevant +|- V/2 save 1/2 power?
0
votes
1answer
42 views

How is the Second level of Cache Accessed

Since the processors have more than one level f memory, how is the 2nd level of Cache accessed. i.e., Access both the first level of Cache and 2nd level are Cache are accessed at the same time. If ...
0
votes
2answers
90 views

What happens on a Cache miss?

In the present day processors more than one level of memory is present for trying for the realization of an ideal memory system and to do more work for clock cycle more than one instruction is in the ...
-1
votes
1answer
61 views

what is microcoded architecture in computer architecture

I want to know what is microcoded microarchitecture of an instruction set architecture (ISA) and why is it used? What is the difference between microcoded architecture and single cycle ...
7
votes
1answer
78 views

Question about an Intel USB Host Controller power supplied per USB port

I had a general question regarding the Intel(R) 82801FB/FBM USB Universal Host Controller (ICH6). The ICH6 has five USB Host controllers in it, with (I'm assuming) two physical USB ports per ...
0
votes
1answer
56 views

Computer Architect Book Reccomendation [closed]

Best Book For Computer Architect , As I have to build SAP this semester. Most people told me it is very difficult to make a SimpleAsPossible 8 bit Computer up and running therefore any suggestions ...
4
votes
2answers
99 views

Should “get new sensor data” be its own task in an RTOS?

I am new to RTOS coding practices/architectures, and am specifically learning on RTX. Should I have a get_new_sensor_data task for each sensor, or is sensor data usually taken care of by some other ...
4
votes
3answers
134 views

Clocked edge-triggered timing (contamination delay)

I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
1
vote
1answer
64 views

Choosing Altera Quartus II clock rate for stopper

I'm using Altera Quartus II to built a stopper. I'm using 2 counters and I need to choose the right clock rate to get pulse every 1 sec. There are only two options in Quartus for the clock: 27Mhz and ...
1
vote
1answer
127 views

Why do we need the MOESI/MESIF protocols?

As I understand, those two protocols add an extra state to identify which cache should respond to a miss request from another cache for a particular cache-line. But, in the MESI protocol, only one ...
0
votes
0answers
36 views

Is my interpretation of this problem regarding a 7-word mux correct?

I have a problem on an assignment which states to draw a block diagram for a 7-word MUX and determine how many control switches it should have. I'm not exactly sure what the problem means by "7-Word." ...
0
votes
0answers
70 views

Virtual Memory, Cache, and TLB's

I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question. I'm trying to study for an exam ...
2
votes
1answer
123 views

Building a simple PC - looking for a CPU [closed]

I would like to build a computer. It is a child's dream that I had and now that I am at college, I finally gain the knowledge I need. I want it to be simple. I admire the early designs of 1990's ...
0
votes
2answers
118 views

Programming microcontrollers in ASM or C & how it's done

Just to clarify on these topics: If I were to program a microcontroller in ASM I would use an assembler, of course. The assembler would compile the code into opcodes (machine code?)(generally 1:1 ...
0
votes
1answer
105 views

What software to graphically design a simple schematic? [duplicate]

I need to draw a schematic similar to that shown in the figure attached in this question. Are there softwares that allow to graphically design a schematic like that?
0
votes
0answers
35 views

Memory technology survey?

I did a comparison on what I could find about access times for different memory systems, could you please say if these numbers are approimately correct (I use an Altera DE2 FPGA)? SDRAM: Slower that ...
0
votes
1answer
186 views

What does “CL” stand for in this processor architecture block diagram?

I'm learning about pipelining but can't understand this abbreviation: "CL". You can see it in processors' schemes. It is shown with with and without a line above it; what is the line for? Diagram ...
4
votes
3answers
414 views

How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency?

I am not new to computer architecture but I have only academic experience with micro-architecture implementation. I have heard and read this many times but never really bothered to understand the ...
2
votes
1answer
83 views

Memory Organization in Computer

How is memory stored in a computer? Is it 1 bit per address so in order to get the value of an integer (32 bits) it must go through 32 addresses, get all the bits of 0's and 1's? I am a bit confused ...
2
votes
0answers
139 views

How does a computer work? [closed]

I am a software programmer.I am very much curious to know about the behind the scenes of how actually a computer works. By HOW I mean:On the hardware level. My knowledge about software programming ...
0
votes
1answer
321 views

How many bits are used for the tag, block, and offset fields for the representation of a memory address?

A small byte-addressable embedded computer system, with a word length of 32 bits, has a main memory consisting of 4 KBytes. It also has a small data cache capable of holding eight 32-bit words, ...
1
vote
1answer
256 views

What are ALMs, LEs and ALUTs?

Does ALM mean "Adaptive logic module"? www.altera.com/literature/ds/ds_nios2_perf.pdf‎ Jul 1, 2013 - One ALUT is equivalent to about 1.25 LEs. Does LE mean logic element and ALUT means ...
2
votes
1answer
346 views

How to wire a system for Nios 2 in Qsys?

I've managed to reduce the number of errors but I still have some: ...
0
votes
0answers
113 views

How to resolve these errors in QSys

I have this error message: ...
0
votes
3answers
83 views

How is 'specific' data found and taken from a Semiconductor Memory Source?

In a semiconductor memory chip, each bit of binary data is stored in a tiny circuit called a memory cell consisting of one to several transistors. Volatile type. Suppose an application stored its ...
11
votes
4answers
362 views

Do computers speed up at higher temperatures?

At higher temperatures, will computers get faster? Evidently, one always wants cool a computer down as higher temperatures can damage core components. However, is it an interplay between silicon, ...
0
votes
0answers
305 views

SAP-1 (Simple as Possible) W Bus

I'm currently investigating the SAP-1 to build in order to grasp a really good understanding of simple 8 bit computers. There are a few questions that I would like clearing up. What exactly is the ...
1
vote
3answers
245 views

Is it true that copying is the most CPU intensive operation?

A mech engineer said that copying puts more load on the microprocessor than "other" operations (e.g. moving data or creating the same amount of new data). Is this true? Can you elaborate? I understand ...
0
votes
1answer
69 views

Ratio between register and primary memory access?

I've been doing research to find how much faster register access is compared to primary memory. I find the ration is about 100 times faster, can that be correct, has it always been about that number ...
0
votes
0answers
57 views

MIC1 Architecture High bit Circuit

Does anyone know what the MIC1 High bit circuit looks like? Or at least the truth table so that I can construct it and get an understanding of it. Here is a picture of the Architecture. The high bit ...
1
vote
2answers
602 views

Differences, uses, and theory of volatile and nonvolatile memory?

I understand the basics of volatile and nonvolatile memory. Volatile memory requires a constant power supply to retain data whereas non-volatile memory does not require a constant power supply to ...
0
votes
2answers
211 views

Is the registry file made from SRAM?

I study computer engineering and I read Hennessy's book about Computer Organization where it's described how the microprocessor does pipelining and that the microproceossor has on-chip cache, as much ...
1
vote
2answers
220 views

Does anyone know the hardware of a Nike+ SportWatch GPS?

I have one of these devices and I would really love to figure out if it is possible to write and push my own firmware into the device. The software on the watch is pretty limited and I would like to ...
1
vote
1answer
64 views

unable to understand write policy in Cache memory

I am studying write policies in cache memory ( for first time ). I am able to understand the 'write-through' but i am not able to understand 'write back' and the problems associated with it . Please ...
1
vote
2answers
441 views

Instruction Register? Whats it's purpose/how is it connected? (And what happens after)

So im learning the SAP 1 Computer Architecture. Most things I get pretty well, but from what I understand: (Lets pretend it's an 8bit and address is 4 bits and opcode is 4bit) ...
1
vote
2answers
222 views

Classic RISC pipeline question

Consider the following instruction sequence: Add R3, R4, R5 (R4+R5->R3) Or R2, R4, R5 (R4 OR R5->R2) Add R1, R2, R3 (R2+R3->R1) Assuming no data ...
0
votes
1answer
88 views

What's the difference between delayed branch and branch prediction?

I'm studying how delayed branch works and I'm trying to distinguish delayed branch from branch prediction. What is the difference? Is delayed branch a means to facilitate a control hazard?
0
votes
1answer
51 views

How to calculate the address fields for a cache?

I've a homework question about 32-bit cache memories: For a cache memory that has size 16kB (16384 byte) and blocksize 2 words, state the names and the sizes of each field of the address that ...
1
vote
2answers
160 views

What is the meaning of “Register.Rd”?

Reading Hennesy's book "Computer Organization and Design" it is mentioned "Register.Rd" and "Register.Rs" but what does it mean? The .Rd, .Rt and .Rs parts I can't understand, on page 365:
0
votes
1answer
106 views

How is sign extension used in practice?

In wikipedia it says what sign extension is but it doesn't say what it's used for or when it is used. I read Hennesy's book "Computer Organization and Design" and it has a sign-extension mechanism ...
2
votes
1answer
146 views

What does RWM mean?

I'm studying computer hardware and the acronym "RWM" appears, so I wonder what it means? It has to do with LOADs and STOREs of instructions.