Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

learn more… | top users | synonyms

-3
votes
1answer
53 views

Amount of adress lines and i/o needed [on hold]

I am having trouble solving this question, I was hoping someone can help. How many address lines and input-output data lines are needed for 2kX16 16MX32 4GX64
0
votes
1answer
76 views

Confused what computer architecture is in real [on hold]

I am quite sure that this is a question which will be marked as "primarily opinion-based" but I would still like to ask it here only as you do not get so many intellectual, experienced and skilled ...
0
votes
1answer
39 views

Understanding computer organisation and architecture [closed]

What are some of the user friendly books for "computer organisation and architechture" which are best for self study. Such a text that one can grasps the big picture, and understandhow various things ...
0
votes
2answers
59 views

Why cant absolute delays be used in ASIC?

Verilog allows the definition of absolute delays when modelling hardware but the ASIC synthesizer will strip these out. Why does it do this?
1
vote
3answers
162 views

How can a powersupply have a large input volt range

I see that computer power supplies that can take a voltage input of anything between 90V and 260V at a frequency between 47Hz and 63Hz. Meanwhile it can output power at a very precise voltage. How ...
0
votes
4answers
93 views

direct mapping cache question

I have been doing the question below in what I thought was the correct way. After doing some more reading I am now slightly confused and would appreciate some clarification. Previously I was just ...
0
votes
1answer
32 views

solving pipelining data hazards using stalls

I have a question about fixing data hazards in a pipelined datapath using stalls. I have read slightly varying things on this. Some lectures I have found put the instruction decode (ID) in the same ...
0
votes
1answer
19 views

Exclusive execution unit in pipeline stage for execution of memory access instructions

I was studying pipeline concept in microarchitecture. My professor told me that memory read and write operations take longer time to execute since DRAM has a maximum frequency of 1333Mhz. Hence, when ...
0
votes
0answers
48 views

Understanding the mechanism of branch prediction buffer

I am learning about 'Dynamic Branch Prediction' using the branch prediction buffer, also called branch history table (BHT). The professor told us said that the BHT is being used in the instruction ...
-2
votes
1answer
72 views

Where is the control, address and data bus in a computer

So have been reading up on data buses, address buses and control buses and I understand what they do, but am confused about where they can physically be found. Some books/sites I have found state that ...
2
votes
2answers
249 views

What is the difference between full and partial address decoding?

Could someone please explain the difference between full address decoding and partial address decoding? I am reading the chapter on digital logic in "Structured Computer Organization", 6th ed. by ...
1
vote
1answer
93 views

Design an 8x4 memory chip using 2x1 memory chips? [duplicate]

I have been given this task to design a single 8x4 memory chip using only 2x1 memory chips. I have been searching everywhere on google for some decent information or example of how this is done, but ...
1
vote
1answer
108 views

Do registers have a multiplexer?

We are learning about general purpose shift registers. My professor draws them with like multiplexers connected to the D's of each flip flop. So in an example of a register with a 4 bit input and ...
0
votes
1answer
60 views

Error-Detecting Code and ASCII Character Code?

As ASCII character code uses seven bit to encode 128 characters and most computers manipulate an eighth-bit quantity as one byte and ASCII characters are stored one per eight bit, and an additional ...
0
votes
1answer
213 views

How many nibbles?

The question reads: You know a byte is 8 bits. We call a 4 bit-quantity a nibble.If a byte-addressable memory has a 14-bit address, how many nibbles of storage are in this memory? My answer: Now I ...
1
vote
1answer
112 views

Interfacing RAM to a DIY computer

I am a relatively newbie to electronics but hopefully this question is not very non sensical: I am following a guide to build a 8 bit computer. The guide requires a RAM which has a 4 address bit and ...
-3
votes
1answer
96 views

How some bits are turned on while others remain off

How does the computer turns physically different bits on and off? I mean that the electricity flows to the transistors in order to turn them on or off but there are many transistors so what part in ...
0
votes
2answers
90 views

Does the databus size matter for determining the range of the memory addresses?

If you have byte addressable memory, does it matter if you have a 32 bit or 64 bit databus for the range of the memory addresses for the words of the memory? E.g. : Assume a 32-bit word. If you have ...
1
vote
0answers
48 views

Operator synthesis VHDL, numeric_std.vhd

if i include the library numeric_std.vhd (the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...
0
votes
1answer
104 views

How to relate memory address to physical components in RAM?

I am trying to understand how are the micro-scale components arranged to relay address information to the Operating system software. What are the components that make up the ram which actually ...
2
votes
1answer
226 views

What multi/many-core (micro)processors/controllers should I use for “embarrassingly parallel” computations? [closed]

This is my first question ever on this site, so I hope I don't mess this up. :D I'll try to be as specific as possible. What I need: Something that I can program in C (or a C-like language). I ...
0
votes
3answers
113 views

How are alphabetic characters programmed into a computer?

I'm no cs student, I'm a programmer. I have a couple of questions and a few assumptions that I will make here (correct me if I'm wrong please). From my understanding is that all the sequences of 1 ...
0
votes
0answers
57 views

When designing a processor for a particular application, how does one determine the instruction set?

When processor is designed specifically for lets say graphics application and I am sure there are other examples, the instruction set of the processor is designed to contain specific instructions that ...
0
votes
1answer
95 views

How much faster would optical computation be?

If (when) we could figure out a way to do computations with light as opposed to electrons within circuits, how much faster would our computers be?
0
votes
0answers
73 views

Floating point multiplication

I'm trying to understand how to implement a floating point multiplier. In order to do that i've looked up at three books where basically the issue is threated in the same way (i.e. not handling of the ...
2
votes
2answers
79 views

Are neuromorphic computers considered digital computers?

This might be a pretty simple question, but I am wondering if neuromorphic computers using non Von Neumann architectures such as the IBM TrueNorth chip are still considered digital computers. I have ...
0
votes
2answers
44 views

How can you have immediates in the SUBLEQ one instruction computer?

I'm thinking about making a SUBLEQ based CPU on FPGA. SUBLEQ (subtract and branch if less than or equal to zero) is an instruction which is universal. However, how can you have immediates/constants ...
0
votes
0answers
78 views

Processor does fetch, decode, execute, memory read/write and register read/write. How can this result in more than 5 pipeline stages?

I have read this marvelous book on processor architecture. It teaches that: The classic RISC pipeline comprises: ...
0
votes
0answers
22 views

ALUOP for a single cycle datapath control

When designing a single cycle data path control unit using PLA (main control and ALU control) My question is how do I choose the ALUop bits and how to make its truth table for each instruction and ...
1
vote
2answers
77 views

Is it OK to use the USB 5v pin as power source?

I am doing some stuff in my case and I need a power source for one LED from inside my case. I looked up and there are two +5v pins on a USB header inside my case. Is it OK to use them as power ...
1
vote
0answers
65 views

find cache hit rate for direct mapped cache memory

I have this practice exam problem which I am having trouble with. I have gone over many slides but haven't been able to really get it. The question is I currently have an 8 block main memory with ...
1
vote
1answer
105 views

single cycle vs multicycle datapath execution times

I have a question where I need to calculate the execution time for a program for single cycle and multicycle datapath. I think I may be doing it incorrectly since the multicycle execution time is ...
-2
votes
2answers
187 views

Are only word sizes used as structural elements in machine computation?

Research: I have been looking for some time online. everything i know in-fact. ive liked sparse matrix representations, i have found gate level sharing optimization after 'formula reduction' and ...
0
votes
1answer
69 views

Two dimensional 512 byte (byte addressable) RAM from 16 byte chips

Assume it is decided to design a two dimensional 512 byte (byte addressable) RAM from 16 byte chips. Each of the 16 byte chips has two select-lines. The chip is enabled only if both of the ...
1
vote
1answer
349 views

multicycle datapath vs single cycle datapath

I have a fairly simple question but have not been able to find a good answer googling. I understand how pipelining works by having 1 cycle per step, each instruction takes 5 cycles and they start ...
10
votes
4answers
4k views

How many clock cycles does a RISC/CISC instruction take to execute?

According to Digital Design and Computer Architecture by Harris and Harris, there are several ways to implement a MIPS processor, including the following: The single-cycle microarchitecture ...
0
votes
1answer
56 views

is it possible to mix chipsets

I'm designing a home made game console motherboard, and want to integrate the ATI Mobility Radeon 9000 GPU in it. The problem is, the Northbridge I picked only supports PCI Express, and the GPU uses ...
0
votes
0answers
37 views

Learning Booth's Algorithm, I Can't Find the Issue on Final Result

I am practicing using Booth's algorithm to multiply a positive number and a negative number (specifically -12 * 4). I have included my attempt, but i can't find the issue. If someone can help me out, ...
-1
votes
1answer
257 views

What is happening in the diagram of LC3?

This is a diagram of the LC3 Computer I am trying to understand what is happening in the parts I highlighted. The part I had highlighted had the instruction bit sign extended to 16 bits and then ...
1
vote
3answers
99 views

Benefit of (logically/virtually) separate I/O and memory bus

In my course on embedded systems, it is explained that memory inputs can be separated from I/O inputs using a "mode bit" for the address decoder. The most obvious advantage of this is that the amount ...
1
vote
1answer
56 views

Simple Mux Equation finding, need help?

How we can find the equation of following simple diagram ? My TA solved it as : C.Not(B).A + B.Not(A)
0
votes
2answers
113 views

Is it possible to simulate hardware of MIPS architecture computer defined using Verilog/VHDL?

I am reading Digital Design and Computer Architecture book and if I will be persistent then I will have MIPS architecture computer at the end, implemented from scratch by me . I wonder is it ...
1
vote
1answer
321 views

Micro and Nano Memory, Calculate Reducing Bits?

I ran into a question: in digital system with micro-programmed control circuit, total of 32 distinct pattern operation signal is ...
0
votes
1answer
30 views

Which are the spec bits in this cache?

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. The physical address is 50 bits, numbered from 0 to 49 (with 0 being the least significant ...
3
votes
3answers
208 views

Logical Design Operation, A Simple Questions?

I'm so sorry if I ask my first question that so simple. My filed is Math and Computer science. I self-study Digital Design. My challenge is how we can find the operation of the two following ...
0
votes
1answer
69 views

What is the difference between a virtually tagged and a physically tagged memory system?

I study computer architecture and this question came. What is the difference between a virtually tagged and a physically tagged memory system?
3
votes
1answer
221 views

adding two 64-bits number with m-bit carry ripple adder and multiplexer, a questions?

I ran into a question from computer architecture class. The professor says that for adding two 64-bit numbers A and B we use m-bit carry ripple adders and multiplexers such as following: and that ...
0
votes
0answers
44 views

Where can I find literature on PCMOS (Probabilistic CMOS)

PCMOS is relatively new technology and I'd like to learn more about its inner workings. I have managed to find couple of papers on PCMOS on google scholar but they are all from 2006-8 so I was ...
-4
votes
1answer
83 views

Logic Gate Cookbook [closed]

Is there a concise book that brings together all of the different Logic devices that can be implemented with basic logic gates? I have several digital/computer architecture books that have the ...
1
vote
1answer
187 views

How the lw (load word) instruction works on the MIPS Unicycle (Implementation)

I'm reading the Computer Organization and Design book from David A. Patterson and John L. Hennessy. Specifically, I have a question about the implementation of a MIPS Unicycle. So, in the book, they ...