Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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Secondary Level address translation (EPT/RVI) TLB implementation

hope this is the right place to ask for the following: Consider a processor/cpu with support for Secondary Level address translation (SLAT) technology (Intel EPT/AMD RVI). TLB caching is used to ...
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1answer
15 views

What is happening in the diagram of LC3?

This is a diagram of the LC3 Computer I am trying to understand what is happening in the parts I highlighted. The part I had highlighted had the instruction bit sign extended to 16 bits and then ...
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3answers
62 views

Benefit of (logically/virtually) separate I/O and memory bus

In my course on embedded systems, it is explained that memory inputs can be separated from I/O inputs using a "mode bit" for the address decoder. The most obvious advantage of this is that the amount ...
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1answer
25 views

Simple Mux Equaion finding, need help?

How we can find the equation of following simple diagram ? My TA solve as : C.Not(B).A + B.Not(A)
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2answers
36 views

Is it possible to simulate hardware of MIPS architecture computer defined using Verilog/VHDL?

I am reading Digital Design and Computer Architecture book and if I will be persistent then I will have MIPS architecture computer at the end, implemented from scratch by me . I wonder is it ...
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1answer
265 views
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Micro and Nano Memory, Calculate Reducing Bits?

I ran into a question: in digital system with micro-programmed control circuit, total of 32 distinct pattern operation signal is ...
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1answer
23 views

Which are the spec bits in this cache?

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. The physical address is 50 bits, numbered from 0 to 49 (with 0 being the least significant ...
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3answers
96 views

Logical Design Operation, A Simple Questions?

I'm so sorry if I ask my first question that so simple. My filed is Math and Computer science. I self-study Digital Design. My challenge is how we can find the operation of the two following ...
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1answer
16 views

What is the difference between a virtually tagged and a physically tagged memory system?

I study computer architecture and this question came. What is the difference between a virtually tagged and a physically tagged memory system?
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1answer
60 views

adding two 64-bits number with m-bit carry ripple adder and multiplexer, a questions?

I ran into a question from computer architecture class. The professor says that for adding two 64-bit numbers A and B we use m-bit carry ripple adders and multiplexers such as following: and that ...
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0answers
16 views

Where can I find literature on PCMOS (Probabilistic CMOS)

PCMOS is relatively new technology and I'd like to learn more about its inner workings. I have managed to find couple of papers on PCMOS on google scholar but they are all from 2006-8 so I was ...
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1answer
52 views

Logic Gate Cookbook [closed]

Is there a concise book that brings together all of the different Logic devices that can be implemented with basic logic gates? I have several digital/computer architecture books that have the ...
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1answer
56 views

How the lw (load word) instruction works on the MIPS Unicycle (Implementation)

I'm reading the Computer Organization and Design book from David A. Patterson and John L. Hennessy. Specifically, I have a question about the implementation of a MIPS Unicycle. So, in the book, they ...
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3answers
139 views

How Can A Coded Firmware Control Hardware [closed]

I really want to know how could a virtual coded program really affect and imitate and animate a piece of hardware. I Have Always Seen The Diagram Of Processors In the Book Showing ALU and CPU as The ...
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1answer
41 views

Difference between multiple pipelines and superscalar?

I have read some threads and the wiki articles, but still don't seem to understand what exactly the difference is between having multiple parallel pipelines and the superscalar architecture. I know ...
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2answers
71 views

Simplifying Circuits

I have a question regarding simplifying a circuit of a function below that has 5 logic gates in original. f = (A + B) * (C + D) + (A + B) * (C + D)' + C = (A + B) * ((C + D) + (C + D)') + C = (A ...
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6answers
2k views

How to efficiently design the opcode for a CPU?

I am building a simple 16-bit CPU in Logisim and have the ALU ready and the opcodes that I want to have. Now I find it really hard to find the right coding for the commands so that the different ...
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1answer
115 views

Why does the A8 have twice as many transistors than the Haswell processor yet runs on less power?

There's something I don't get - I am always under the impression that the more transistors we pack in, the more energy it consumes and the hotter it gets (assuming we haven't shrunk the die). However, ...
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2answers
133 views

Booth multiplication algorithm, why it works?

Just learned about Booth's multiplication algorithm, and from what I understand if the multiplier least significant bit (MLB) is equal to the previous significant bit in that multiplier (MPLB) then we ...
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2answers
153 views

Where is the best place I can go to learn everything about the electronics-side of computers? [closed]

Throughout my childhood, I grew up learning about electronics and computers. I am starting to get to the point where I want to incorporate my knowledge of both into a single project. I have tried ...
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2answers
84 views

You need at least four states to exploit the advantages of a Mealy machine over a Moore machine

What's meant by this question? "You need at least four states to exploit the advantages of a Mealy machine over a Moore machine." I'm trying to wrap my head around this but I'm not sure "what" ...
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1answer
89 views

Inherent exploitability and power state machines

I'm working on understanding power state machines in regard to mobile computing devices. Most of the information on this subject seems to stem from this article. It's not particularly important to the ...
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1answer
199 views

Determining memory address width from memory size

Given a computer A with 1024 x 16 memory and a computer B with 16K x 32 memory, how big are the registers of an Accumulator, program counter, instruction, temporary register, address register, data ...
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3answers
81 views

Finding Instruction Count

Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz. Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. We have a particular program we wish to run. When ...
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1answer
64 views

implementing direct addressing mode for a load instruction on a mips archtitecture

Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows |OPT code|rs|rd|immediate| |6 bits |5 bits|5 bits|16 bits| The OPT code is the ...
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0answers
71 views

Calculate Instructions per second MIPS

I'm trying to solve this problem for a MIPS processor: Suppose the data cache is perfect but the instruction cache has a 5% miss rate. On a cache miss, the processor stalls for 20 ns to access main ...
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1answer
109 views

CPU Execution Time / Performance

I'm trying to solve a question concerning performance. I have the final answer (24 * 10^9)but I can't determine how to get there. I know the formula for performance is Execution time: CPI * I * ...
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83 views

How to compare processor speeds based on architexture

Is there any rule-of-thumb for comparing processor speed based on architecture? I'm researching single-board computers, and I'm trying to compare ones using ARM processors (e.g. Beaglebone Black, ...
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1answer
47 views

Spread spectrum 400 KHz

I got a 6-phase DC-DC converter. Fsw=400 kHz, synchronization by external clock(CPLD). I need a spread spectrum 400 kHz. What's the best way? All chips what I've seen before worked on MHz and above. ...
2
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3answers
89 views

Curious how does ALU addressing work like in Assembly code?

When writing assembly code, say R1 = R2 + R3, it is pretty easy to understand the addressing procedure because all registers are close to the ALU. But I find it hard to see how does the ALU go to the ...
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1answer
262 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
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0answers
51 views

How to implement a pipelined integer divider

I need to implement a pipelined integer divider for my 64-bit microprocessor. I have tried reading up on this, but I am still confused. Any advice would be appreciated.
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6answers
377 views

How to implement an 8-bit CPU?

I'm trying to create a CPU, using 8-bit instructions, and there will be 9 or 10 of them. I have an add, subtract, multiply, load, store, branch if zero, branch if not zero, print (to display), input ...
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2answers
912 views

How does a ps2 mouse send data to a computer? [closed]

I want to read data from a mouse with the help of Arduino. I want to calculate relative motion between two objects. My questions are 1) Is it possible? 2) How is mouse interfaced with Arduino?
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152 views

Calculate Speedup

What is the overall speedup of a system spending 65% of its time on I/O with a disk upgrade that provides for 50% greater throughput. The formula should be Amdahl's law: overall speedup = 1 / (1 ...
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0answers
44 views

How can I connect this ram-ish memory layout

In the picture on the web, I want to connect the two inverters that are ringing around each other, I want to connect them to the data-line. I can't seem to figure out how to properly connect them in ...
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3answers
175 views

How to make the hottest CPU temperature?

Besides just running an infinite loop, are there any tricks (like maybe cache misses?) to making a CPU as hot as possible? This could be architecture specific or not.
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1answer
147 views

Use of $at register in MIPS?

Register r1 or $at, is it's sole use in pseudoinstructions? If so, is this the sole solution to enable pseudoinstructions within the architecture?
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33 views

Help with harder version of carry chain adder?

I am designing an addr circuit given cin = 0, given a nand of the operands i want to add, their xor, and nor. I have drawn it in a software but i am not getting the right output, i have tried to ...
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1answer
267 views

Calculate Paging System

I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it. A paging system has the following parameters: 2^32 bytes of physical memory; page size of ...
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1answer
95 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
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2answers
146 views

I need help with verilog code, I am in trouble?

I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
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1answer
43 views

How should this code look like in verilog?

I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
2
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4answers
191 views

2-bit branch prediction accuracy

I am trying to solve this problem, the answer should be 15/20 = 75%. However, I am not sure how this was calculated and want to understand the underlying concept. A program core consists of five ...
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0answers
8 views

2-bit branch prediction accuracy [duplicate]

I am trying to solve this problem, the answer should be 15/20 = 75%. However, I am not sure how this was calculated and want to understand the underlying concept. A program core consists of five ...
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0answers
69 views

Virtually indexed physically tagged cache

I'm trying to understand the concept and calculations for solving this problem. I know the answer is 10 bits. ...
2
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1answer
95 views

What could this PLA be doing?

The picture below shows a PLA, I have done part (a) and found out that; $$ F_0 = A_0 \mathbin{\oplus} B_0 \\ F_1 = A_0B_0 + (\overline{A_0} + \overline{B_0})(A_1 \mathbin{\oplus} B_1) \\ F_2 = ...
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61 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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1answer
114 views

5-stage pipelined implementation (RISC) of a microprocessor

I'm trying to solve two questions about a RISC 5-staged pipeline that is not exactly like MIPS found here (everything is included in this post). Consider the non-pipelined implementation of a simple ...
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1answer
90 views

ISA efficiency code compaction and memory traffic

I'm having issues understanding this problem and am new to ISA's. Here's a problem with 3 questions and my biggest question is, what is supposed to happen? Specifically, the HLL Code at the bottom. ...