I am novice to high speed design. Before getting in to DDR, I recently learned about impedance matching and how it is done, likewise I learned about length matching and how it is done.(Baby steps ...
We have some controlled impedance traces on layer 4 of a board. Layer 3 is a GND plane. Layer 5 is a 3.3V plane. Both planes are unbroken (they occupy the entire layer), with the exception of vias and ...