A CPU, or Central Processing Unit, is the heart of any digital computer.

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How to calculate cache size?

A cache with a line size of L 32-bit words, S number of sets, W ways, and addresses are made up of A bits. Assume that the cache is word addressed, i.e., the low two bits of the address are ...
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21 views

FPU stress test - CPU overheating and pc freeze [closed]

I have the following brand new hardware for the moment: Intel i7 4790k Asus Maximus Extreme VI C2 2 8gb Kingston HyperX Beast 2400mhz dual Channel RAM Cooler Master Nepton 280L watercooling Be Quiet ...
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44 views

How do you store A or B in a RAM of a CPU datapath?

I have an assignment to make a CPU, but am confused with how f_left and f_right are going to be used. I think they are to store ...
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4answers
114 views

How does a CPU choose a path? [closed]

This is the most baffling question of all other concepts. I ask my teacher "How does the computer choose a path?" "They program it" "How do they program it?" "..." I have a basic understanding ...
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0answers
37 views

Pipeline Processor Calculation

My assignment deals with calculations of pipelined CPU and single cycle CPU clock rates. The following data is given, about the time each operation takes to execute: ...
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1answer
58 views

RAM and data copying/moving

I was wondering about the copying/moving of data in RAM and I couldn't help but thing about the possibility of having the RAM process basic memory operations such as copying/moving of memory, if ...
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1answer
101 views

How to program pentium CPU [closed]

I have two perfectly good CPUs-one a Pentium m, the other a Pentium III-and they're just sitting in antistatic bags and bubble wrap doing nothing. I want to use them for SOMETHING, I know their ...
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1answer
69 views

How to test OpenSPARC CPU?

There are several open-source general-purpose CPUs, and the most advanced of them seems to be OpenSPARC T2 (correct me, if I'm wrong). I want to find out, with what effort I can build a machine, ...
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2answers
63 views

Processor Budgeting

How do I figure out if a microcontroller has enough processing speed to handle particularly "intensive" tasks? Specifically, I am a university student looking to design a robot that uses OpenCV and a ...
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1answer
70 views

CPU and clock rate

As I understand it, CPUs generate electrical pulses using a quartz crystal. The rate the pulses are generated (taking into account various multipliers) give the processing speed which all components ...
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4answers
3k views

How can a CPU deliver more than one instruction per cycle?

Wikipedia's Instructions per second page says that an i7 3630QM deliver ~110,000 MIPS at a frequency of 3.2 GHz; it would be (110/3.2 instructions) / 4 core = ~8.6 instructions per cycle per ...
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84 views

How many people might have been involved in the design of the Macintosh SE? [closed]

It is really difficult for me to know how many people were in charge of the development of this electronic wonder. When I'm struggling to properly comprehend transistors and how they work, these ...
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96 views

Why long pipelines are preferred over high CPU clock?

Why modern CPU vendors prefers increasing the maximum length of the pipeline over increasing the clock? Accordingly my understanding, increasing either increases the number of gate switches and so ...
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7answers
6k views

What limits CPU speed?

I've recently talked with a friend about LaTeX compilation. LaTeX can use only one core to compile. So for the speed of LaTeX compiliation, the clock speed of the CPU is most important (see Tips for ...
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6answers
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How does a non-FPGA (ie a PC with a CPU, RAM, hard drive) mimic logic gates?

I know that an FPGA uses look-up tables (LUTs) to synthesize logic gates. A LUT is a block of RAM that is indexed by a number of inputs. The output is the value stored at that memory address. The ...
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2answers
176 views

Why does Intel looks so advanced compared to other foundries, engraving fineness-wise? [closed]

Latest chips from Intel were 22nm, and they are now targeting 14nm (coming in 2014 or 2015 it seems). On the other hand, Global Foundries or TSMC struggle since several years to go beyond the 28nm ...
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1answer
269 views

Were can I find a simple CPU Design tutorial / book? [closed]

I basically want to know how to make(In hardware and in a simulator) a simple CPU. A book that covers low level stuff like, like logic gates, and more high level stuff like a complete CPU. Ive tried ...
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178 views

What are these hardware components, and how do I control them?

My father received a video card in the mail last week. He gave it to me and I dismantled the card to get to just the video player and other components. The labels here are based on my experience ...
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1answer
55 views

What defines whether a CPU should be in LGA of PGA package?

All modern Intel CPUs I know are in LGA package. At the same time, AMD CPUs mostly are in PGA packages, with only server ones packaged in LGA. What are the reasons for Intel to use and AMD to not use ...
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1answer
240 views

AC/DC 4W vs 2A GSM transmission bursts

I have a big problem with the power supply of a SIM900. I designed my own board with a 220VAC-5VDC tracopower, an ARM9 CPU, and a GSM/GPRS SIM900 module. The output of the tracopower is 5V - 800 mA ...
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1answer
219 views

Why a lower voltage is better for modern fast CPU and other similar chips?

I started to use computers in the 1980's. As far as I remember 8bit CPUs of those times like Z80 were often powered by 5 V and used the same voltage for I/O signals. Later CPUs run at higher speeds ...
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3answers
88 views

Is quantum tunneling in transistors patterned?

Quantum tunneling is a problem when engineering a nano scale transistor. Generating random numbers is a common issue in computer science. I'm not an expert in either of these fields, but to someone ...
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2answers
132 views

PCI-Express Processor/Co-processor cards [closed]

I am hoping someone might be able to help: In the days when I started with computing (C64 and later Amigas) expansion slot cards with co-processing ability were relatively common. I am looking for ...
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3answers
439 views

Why is L1 cache faster than L2 cache?

I'm trying to understand why certain CPU cache memories are faster than others. When comparing cache memory to something like main memory, there are differences in memory type (SRAM vs DRAM), and ...
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1answer
80 views

Hardware accelleration for Python dict?

I wondered if it were possible to accelerate in hardware the Python dict? Dicts are mappings between a key and value that form a large part of the backbone of how Python works. Everything is an ...
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1answer
66 views

how the CPU start by execution stored in motherboards flash memory chip [closed]

I had read that at start, the CPU program counter register is fill with F000. I though that: PC registers contain the next instruction address. This address is send to the address bus and value ...
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2answers
336 views

How does a GPU/CPU communicate with a standard display output? (hdmi/dvi/etc) [closed]

I am interested in how the cpu/gpu presents (to whatever equipment that it does) video data after it has been processed. I have been told that the video is processed by the cpu/gpu and then sent to an ...
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1answer
83 views

Dynamic energy and dynamic power in microprocessors

In a class I'm learning about dynamic energy and dynamic power and the notes seem to be incomplete. ...
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2answers
97 views

Programming with ARM without microcontroller context [closed]

I want to make an application that will use ARM CPU. Am I bound to using microcontrollers? The thing is the microcontrollers that have ARM as a base are really big in physical size. Can I create a ...
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3answers
3k views

How can an FPGA outperform a CPU

I hear of people using FPGAs to improve performance of systems that do things like bit-coin mining, electronic trading, and protein folding. How can an FPGA compete with a CPU on performance when ...
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1answer
89 views

Combining CPU and RAM on stacked silicon

Xilinx developed a way to combine multiple dies in a single package by using a silicon interposer (I don't know whether they're actually are the first ones to do this). This way, they achieve huge ...
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2answers
93 views

How many electrons does it take to switch on a transistor [closed]

How many electrons does it take to switch on a transistor, I read somewhere that Inel had made some electrical "paths" so small that they can allow only individual electrons to flow at a time, or ...
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1answer
72 views

CISC, microcode execution flow

Say we have 16 bit processor and such CISC instruction: 0001 0010 0100 1000 As far as I understood from the answer on related question In the process of decoding, this CISC instruction will be ...
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1answer
661 views

ARM9 vs ARM11 performance? [closed]

This may be a loaded question, but is there a general understanding of the performance increase per clock between ARM9 and ARM11? Say, for a math-heavy function (FFT)? Thanks!
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166 views

Xbee not responding timely. Large delay between each transmission

I have prepared a setup for 2 Xbees one connected to the PC via XCTU and the other interfaced with Atmega 168. The terminal software will send 1 and the xbee with Atmega 168 will return 1. The code ...
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139 views

What happens when the same interrupt is caused during an ISR? [closed]

To handle an interrupt the processor jumps to an interrupt service routine (ISR). If this ISR generates the same interrupt then this can result in: a) program error b) hardware error c) stack ...
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1answer
511 views

What is the fastest logic gate?

I have been told that the fastest logic gate family is ECL. My first question: Is this true? In this or another family (Depending on the answer to the above question), Is there any particular gate ...
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1answer
89 views

What is the Global Descriptor Table memory type?

What type of memory type is used for the Global Descriptor Table in an Intel Core 2 CPU? Is it just EEPROM or does the CPU normally use another type of NVRAM?
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2answers
116 views

How interrupts handle does work on a physical layer

I want to understand how HW IRQ does work on a physical layer. I ask my question considering a specific example. As known after a packet coming to a network adapter a hardware interrupt is signalling. ...
2
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1answer
449 views

Why does capacitor charge slowly but discharge quickly?

I've designed this circuit using Multism 10.1 : This circuit is part of clock generator for 8088 uP: Why does the wave of ch1 of Oscilloscope which represent the voltage across the capacitor take ...
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2answers
227 views

What is the function of the capacitor and the diode here?

This photo: is taken from the book: The Intel Microprocessor Family: Hardware and Software Principles and Applications, pageĀ 298. This is a 8284 (clock generator) for the 8088 microprocessor. What ...
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3answers
163 views

Why the frequency of single-core CPUs has stopped increasing? [duplicate]

I wonder why CPU vendors stopped producing CPU with frequencies above 3.0 - 3.6 Ghz and switched to using multi-core CPUs? What was the reason behind this step? Was there a physical constraint or the ...
3
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1answer
162 views

Building a simple PC - looking for a CPU [closed]

I would like to build a computer. It is a child's dream that I had and now that I am at college, I finally gain the knowledge I need. I want it to be simple. I admire the early designs of 1990's ...
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2answers
237 views

How to avoid input/output conflicts with a bus

How does a system bus work? I don't understand how can a circuit avoid input/output issues with a bus. I included an image to better explain my thinking. The circuit has 2 general purpose ...
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1answer
235 views

Is the speed of light the upper bound on CPU speed? [closed]

Edit: As this my first question in this site I was a bit confused how to pose the question. Because of the way I had put the question before has made it trouble to understand What is the fastest ...
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1answer
146 views

What software to graphically design a simple schematic? [duplicate]

I need to draw a schematic similar to that shown in the figure attached in this question. Are there softwares that allow to graphically design a schematic like that?
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0answers
101 views

Doubts in two level cache system

A computer system has an L1 cache, an L2 cache, and a main memory unity connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times ...
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1answer
161 views

minimum clock cycles needed?

The instruction call Rn,sub is a two word instruction.Assuming that PC is incremented during the fetch cycle of the first word of the instruction,its resister transfer operation is ...
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185 views

Why vectored interrupts are not possible?

vectored interrupts are not possible if a cpu has single interrupt request line and single interrupt grant line while multiple interrupting devices are possible . Is the above statement is correct ...
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5answers
183 views

How does register type modifier work on different CPU architectures?

This question is to clarify my doubt against this register storage class. when a variable is register qualified ,compiler puts the variable in a cpu register other than RAM for ease of access. so ...