A CPU, or Central Processing Unit, is the heart of any digital computer.

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How is data transmitted on different media?

Thinking about computers primarily, I'm trying to get my head around how data is transmitted along various transmission media. In particular, I'm getting confused between the use of electromagnetic ...
2
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1answer
44 views

How instruction skipping is avoided during procedure calls in pipelined architectures?

I have a question regarding a PC register (IP in x86 lingo). In most architectures it is updated during an execution stage and thus stores an address of a next instruction to be fetched. It seemed ...
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0answers
45 views

Finding the effective switched capacitance in Intel processors

I need to able to calculate the power consumption of an Intel processor using the equation, P = C * (V^2)*f where C, V and f are the effective switched ...
0
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1answer
40 views

How to calculate how much data a Core 2 duo E8 can write to the RAM per second?

I'd like to know how exactly I could calculate how much data the Core 2 duo E8 can write to the RAM per second, given that it is not overclocked and the RAM is 333MHz-DDR3?
12
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5answers
2k views

Does a CPU completely freeze when using a DMA?

I have pretty straightforward question, but I couldn't find an answer to it anywhere. On a Von-Neumann system where code and data live in the same RAM, the CPU must fetch all its instructions from ...
1
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1answer
41 views

Microinstructions: Why is H = H – MDR illegal if H and MDR use two different buses?

The book here (on page 14) states this: Similarly, H = H – MDR is illegal too, because the only possible source of a subtrahend (the value being subtracted) is the H register. From my ...
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1answer
54 views

1 bit shannon entropy CPU instructions? [closed]

It has been proved, that the xor operator is suitable for entropy accumulation, due to its theoretical shannon entropy of 1 bit. There are six truth tables with ...
1
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1answer
47 views

GFlops for IBM Power8 processor

What is the number of GFlops per cpu cycle for IBM Power8? Flops per cpu cycle is obtained as ( number of double precision floating point numbers fitting into one vector processing unit (if any) ) * ...
9
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6answers
598 views

memory for the simplest possible computer (Pi0K)

I'd like to build the simplest possible computer. I don't care about speed or storage, indeed having slow speed and low storage is a huge advantage as I want to build it out of transistors (ideally ...
3
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4answers
539 views

Real time operating systems

I have been asked this question: “Do you think the system will need deterministic time or real time responses?” The problem I have is distinguishing the difference between the two. I know that a real ...
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2answers
44 views

What happens if a branch prediction overwrites a value?

We are just learning about branch prediction so I might not totally understand how they work, but as I understand it, the branches are set to predict either taken or not taken. The pipeline will start ...
0
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1answer
57 views

Can an FPGA connected to a CPU via PCIE access peripheral devices?

Is it possible for an FPGA connected via PCIE to a CPU, to directly access peripherals (USB Ports, data, Ethernet, etc) connected to the same CPU via a chipset? I had an Intel based system in mind, ...
0
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1answer
43 views

Choosing components to clone ZX80

I have an idee fixe to make a clone of Sinclair's ZX80 computer. So now I'm trying to find out which ICs I need for the basic prototype - and here are a few questions: it seems ...
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3answers
65 views

Programmed IO vs interrupt for devices

Although I can understand the difference between programmed IO (PIO) and interrupt (INT) transfers, still there is something vague. In PIO, the processor repeatedly checks READY pin to see if the ...
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1answer
48 views

Performance comparison of dual core and quad core processors with same TDP

Athlon X2 340 (dual core) and Athlon X4 740 (quad core) from AMD have same architecture and both have same TDP (65W). They also have roughly similar frequency. Does this means that at full load, the ...
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1answer
73 views

Where is the control, address and data bus in a computer

So have been reading up on data buses, address buses and control buses and I understand what they do, but am confused about where they can physically be found. Some books/sites I have found state that ...
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0answers
27 views

State Machine for I-type MIPS instructions

I need to design a multi-cycle CPU in Verilog for MIPS instructions, but I'm still trying to fully understand the datapath and control. I found a state machine design for a MIPS instruction ...
0
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1answer
60 views

ESD protection for work with CPU/GPU

I am ready to perform a BGA reballing operation on my ps3's CPU and GPU chips. Should i take into consideration electrostatic discharge or is it not needed? How can i protect from these dangers? Are ...
1
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1answer
522 views

Is there a way to build a 2k*12 RAM using only 2 4k*4 Chips

Okay so I know when I need to build a parallel design I can put them near each other and make a 4k*8 to expand the databus. But on this one I only need to use half of them and the databus length is ...
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1answer
49 views

What kinds of parallel RAM are there?

I have basically no experience in electrical engineering or hardware design, but as an experienced software engineer, I recently took an interest in designing my own CPU. I followed the ...
0
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1answer
102 views

What are the CPU activity steps for the fetch-decode-execute cycle

So in all the phases of the fetch-decode-execute cycle, it says that the "store" phase is used to store any resultant data from the execute phase. What are the CPU steps for that phase? I heard that ...
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1answer
91 views

How do I convert ldi R17, 129 to machine code

What I got was 1110 1000 0001 0001 when I converted it to machine language. Is that right? Also what are the CPU activity steps and where am I going to use the address 0xF000? Is this the right CPU ...
3
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1answer
95 views

How do wires connect to transistors?

So I was looking at the schematic of NPN and PNP transistors which basically involved layered blocks of doped material stacked. My question is how do wires connect to these devices? I think this ...
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1answer
90 views

How does a CPU change frequency? [duplicate]

From what I've found on the internet, CPU clocks work with piezoelectric material to produce a very stable oscillating signal but those materials must change in shape or size to get a different ...
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1answer
54 views

CPU ports and cache controllers

I have seen CPUs conforming to Harvard architecture with dedicated ports for program memory and data memory. I have also seen that instruction and data caches (read-through caches) are connected to ...
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2answers
94 views

AND gate with a single input in a diagram

consider the following diagram: http://ee-classes.usc.edu/ee459/library/datasheets/DM74LS181.pdf ( page 3 ) The first AND gate at the top left of the schematic has only one input! What does this ...
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90 views

Does the databus size matter for determining the range of the memory addresses?

If you have byte addressable memory, does it matter if you have a 32 bit or 64 bit databus for the range of the memory addresses for the words of the memory? E.g. : Assume a 32-bit word. If you have ...
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2answers
139 views

When do I call it CPU and when IC-Chip?

Currently I'm a it confused. A IC (integrated Circuit) Chip implements one or many circuits on a chip in order to control any kind of stuff. However, a CPU is from my point of view also a BIG circuit ...
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3answers
144 views

How to link ALU to registers, RAM and Clock?

I've designed a basic 4-Bit ALU which computes A+B, A-B, B-A, and a few logic operations. I'm using a mux to determine which output appears at the multiplexer output. This is a basic start to a CPU as ...
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0answers
53 views

One chip-select/die-termination/clock-enabler for multiple DDR3 DRAM chips

I'm struggling to know how one DRAM chip select pin, DRAM_CS below can help the processor/CPU manage four DRAM chips? And also how can one clock enabler ...
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1answer
82 views

Is there a wire (a bus), albeit a very short one, between the CPU and its level-1 cache?

I was wondering what is the specific connection mechanism between the CPU and its level-1 cache so that in practice level-1 cache access time is reduced to match the CPU clock frequency? Do level-1 ...
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3answers
113 views

How are alphabetic characters programmed into a computer?

I'm no cs student, I'm a programmer. I have a couple of questions and a few assumptions that I will make here (correct me if I'm wrong please). From my understanding is that all the sequences of 1 ...
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1answer
143 views

Powering a 4-Pin stock CPU heatsink fan with an external power supply

I have scoured this website and the rest of the internet looking for a solution to my particular issue, but as of yet I have not found an answer. If this is a duplicate question I am sincerely sorry, ...
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3answers
236 views

Difference between Micro-Operations in RISC and CISC processors

I've read that the modern Intel processors use the CISC instructions on the top, which are converted into RISC-like simpler instructions in the form of Micro-Operations at the back-end. So if Intel ...
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1answer
44 views

ARM architecture and ARM ISA [duplicate]

I am new to world of ARM trying to understand the core concepts been reading forum where ARM architecture and ARM instruction set is used interchangeably. ARM architecture as i understand is a CPU ...
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1answer
82 views

PS2 or USB keyboard for custom CPU

I have made a CPU on an FPGA board. It works great but I cannot proceed to make a computer with it until I have an input. What use is a computer if it can talk to you, but you cannot talk to it? It ...
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1answer
74 views

Can MCU ROM and RAM limitations be scaled?

Please note: Although this specific question has to do with the 32-bit ARM SAM3X8E Cortex M3 series, it is really a generic question that should be applicable to all microcontrollers, and therefore ...
4
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1answer
83 views

Pull up resistor in NMOS logic value

For my senior high school project I decided to build a basic CPU from discrete components. I plan on using a 5V logic level and the current design calls for around 2000-3000 N-channel MOSFET ...
3
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1answer
72 views

Use different footprint for a SATA connector

I am designing an Linux Board which needs a SATA connector. Now im faced to choose between 2.5 HDD SATA connectors and the new mSATA (mini PCI express) connectors. For compatiblity and usuabillity ...
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2answers
208 views

Why does my ALU design delay outputting the results for two clock cycles since input of valid data?

Hello EE StackExchange! I have been trying to design a simple 8-bit CPU for several months now. However, I am experiencing a problem: The ALU outputs the result of the operation two clock cycles ...
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1answer
584 views

How do I build RAM/CPU with logic circuits? [closed]

I want to build a little 4 bit computer, out of logic circuits. I want RAM and a CPU and all that good stuff. My main problem is, should I work on RAM or CPU, which one would "teach" me more so that I ...
0
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1answer
84 views

Given the dynamic and static power consumption how does one determine the total power for the capacitive load?

I get that the capacitive load is determined which is also indicated by this question: $$\frac{Power}{Voltage^2 \times frequency} = Capacitive Load$$ However, I am not sure how power (which is ...
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1answer
50 views

Memory Question

Picture of memory bank and questions: for b) The CPU should use address 101100 to store A in chip 2 with the location 22. My thought process is that the first bit decides which ram chips will be ...
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2answers
123 views

How do devices with different external clock communicate between each other on a motherboard?

I don't have any pratical knowledge about eletronic circuit. Actually I am a high level software programer and I've just begin to learning about computer hardware and eletronics. Basically, I ...
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10answers
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Why is RAM not put on the CPU chip?

Modern CPUs are very fast compared to all things external, including memory (RAM). It is understandable, since CPU clock frequency has reached a point where it takes several clock ticks for an ...
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2answers
115 views

Why are Index Registers needed?

In a cpu, why are/were Index Registers needed? You can of course live without them, but why would you want them? Wikipedia says that they are used for vector/array operations, but I'm not really sure ...
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1answer
355 views

multicycle datapath vs single cycle datapath

I have a fairly simple question but have not been able to find a good answer googling. I understand how pipelining works by having 1 cycle per step, each instruction takes 5 cycles and they start ...
0
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1answer
96 views

Can you make a board like Intel Edison?

I have a project to design a new board to be used in specific application. The boards would control and take image from CMOS camera under ground. Because of limitation in power consumption and cost ...
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1answer
99 views

How fast cpu clock do you need to control camera?

I'm making a camera system with CMOS image sensor and micro controller. But I don't know yet how fast cpu clock I need. Assuming that I use 5MP cmos image sensor and take just still image with 1fps, ...
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1answer
32 views

Looking for datasheet for Alpha 21264C

Not too long back I did some reading on the Alpha CPU architecture and (probably out of a burst of nostalgic stupidity) procured a couple; there's only an issue - the ones I have are the 21264 ...