Cyclone is a family of FPGAs from Altera

learn more… | top users | synonyms

0
votes
1answer
29 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
1
vote
1answer
160 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
1
vote
1answer
64 views

A simple VHDL circuit won't display initial value

Here is my code and it's pretty simple. I'm to cycle through the first 8 letters of the alphabet on a Altera Cyclone II board. ...
0
votes
0answers
351 views

Shematics of the BeMicro CV eval board from Arrow

Where can I find the complete schematics of the board? Arrow sells an ultra low cost FPGA platform with a Cyclone V device on it for around 30$. Ok, for that price it has the bear minimum: 2 buttons, ...
2
votes
1answer
370 views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...
-2
votes
1answer
1k views

Generate sine wave in VHDL, with the use of 10-bits DAC [closed]

I want to generate a sine wave with 20Mhz frequency, using a FPGA (Cyclone 3 EP3C10E) and an external 10bit DAC converter (http://www.analog.com/static/imported-files/data_sheets/AD7533.pdf). I have ...
6
votes
2answers
696 views

PCIe fails on “polling compliance” state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that ...
2
votes
1answer
356 views

JTAG Design for altera cyclone 3

I am designing the JTAG for a Altera Cyclone 3 (EP3C5E144C8N). I was only aiming at normal JTAG, and do not need Active Serial. I have attached the schematic and board in the *.zip file ...
0
votes
0answers
251 views

USB bare metal on ARM Cortex A9

We are envisioning developing a new project using a Cyclone V SoC with a hardcore ARM Cortex A9 dual core processor. We are seriously considering going bare metal, but one of the main questions right ...
0
votes
2answers
186 views

symbols for ep3c5e144 and ep3c25e144 in Eagle

I am using ep3c5e144 to design a PCB board. Sadly, in Eagle I cant find the exact library and symbol for this device, but only its near relative ep3c25e144. I have some questions: How different is ...
5
votes
1answer
775 views

Altera: Change JTAG clock speed

I am having issues with JTAG with my Cyclone IV, specifically the JTAG clock. I am trying to change the JTAG clock frequency somewhere, but can't find where this is done in Quartus II. How can I ...
1
vote
1answer
219 views

Quartus II: Pin incompatible with a bank it is not on

I am using the pin planner of Quartus II to place my I/O signals on my Cyclone IV pins. I am stuck on the following fitter error: Error (169029): Pin adc0_in[0] is incompatible with I/O bank 3. ...
3
votes
2answers
156 views

Measuring Power from Altera Dev. Kit (CycloneIII)

The Altera CycloneIII starter kit that I have provides a jumper (J6) that is connected to VCCINT of the CycloneIII FPGA core for what seems to be the purpose of measuring the core's power consumption. ...
0
votes
1answer
125 views

Can I use LPDDR with Cyclone III FPGA?

I have seen the Cyclone III datasheet and it claims DDR and DDR2 compatible PHY. But was looking some good LPDDR chips for my design. Could I use the PHY inside of Cyclone III with LPDDR ic? Do you ...
2
votes
1answer
334 views

Altera Cyclone IV memory block Verilog module

This document explains the various characteristics of the Altera Cyclone IV memory blocks (known as "M9K"). However, there is no mention as to how these modules should be instantiated in Verilog. ...