Cyclone is a family of FPGAs from Altera

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Error (209015): Can't configure device. Expected JTAG ID code 0x02D010DD for device 2, but found JTAG ID code 0x00000000

I'm having a weird problem where i cant upload my design to the DE0-NANO board, gives me the weird error message which is the title of this question. Any other design uploads fine and I have done ...
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30 views

How to assign pins of Altera Cyclone II to 7 segment?

I am quite new to FPGA and I want to design a 1-digit counter on a 7-segment on an Altera development board. What I have done so far was to schematically design a bcd to 7-segment decoder in Quartus ...
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26 views

Using TCL (or other Script) file in Quartus to automate circuit creation

I have various simple modules (Verilog) written and included in my Quartus project file. Lets say each such module receives a 8 bit input, increments the value and outputs the new value. Depending ...
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1answer
28 views

Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
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1answer
34 views

Verilog outputting specific bit from register to output; getting constant 1's

I am trying to create an program that bit bangs a value from an FPGA to an arduino. In the module I created, every other clock cycle, the FPGAdata output should be set to the next bit of t. The ...
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2answers
86 views

Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...
2
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2answers
532 views

FPGA non-volatile progamming

I recently bought a Cyclone II FPGA here. I have been able to program it with a USB Blaster cable and the Altera Quartus Software. The problem is that when I disconnect power, I lose the program. ...
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52 views

Cyclone V LVTTL GPIO Termination

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO. The cyclone V datasheet show that no external termination is required as shown ...
2
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1answer
77 views

Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and ...
2
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1answer
140 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
2
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2answers
368 views

For a PLL Clock multiplier, where does the new clock come from?

If I understand it correctly, you use a PLL in an FPGA to get a higher clock from, say, a 50 MHz oscillator by synchronizing the faster clock to the slower reference one. Like if I had a 50MHz crystal ...
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1answer
253 views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
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1answer
2k views

Keypad Scanner Verilog code problem with state machine and column input

I am developing a Keypad both in hardware and Verilog using a DE2 Cyclone II board. I made a keypad using buttons (switches) that follows this schematic: The scanner works by setting the Column ...
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1answer
147 views

reuse Cyclone IV fpga Pasive serial configuration pin for SPI

Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ? This are the dual purpose pin options: if i set "use as Regular I/O" , i ...
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1answer
69 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
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1answer
635 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
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1answer
94 views

A simple VHDL circuit won't display initial value

Here is my code and it's pretty simple. I'm to cycle through the first 8 letters of the alphabet on a Altera Cyclone II board. ...
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777 views

Shematics of the BeMicro CV eval board from Arrow

Where can I find the complete schematics of the board? Arrow sells an ultra low cost FPGA platform with a Cyclone V device on it for around 30$. Ok, for that price it has the bear minimum: 2 buttons, ...
2
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1answer
780 views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...
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1answer
2k views

Generate sine wave in VHDL, with the use of 10-bits DAC [closed]

I want to generate a sine wave with 20Mhz frequency, using a FPGA (Cyclone 3 EP3C10E) and an external 10bit DAC converter (http://www.analog.com/static/imported-files/data_sheets/AD7533.pdf). I have ...
6
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2answers
1k views

PCIe fails on “polling compliance” state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that ...
2
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1answer
622 views

JTAG Design for altera cyclone 3

I am designing the JTAG for a Altera Cyclone 3 (EP3C5E144C8N). I was only aiming at normal JTAG, and do not need Active Serial. I have attached the schematic and board in the *.zip file (http://www....
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299 views

symbols for ep3c5e144 and ep3c25e144 in Eagle

I am using ep3c5e144 to design a PCB board. Sadly, in Eagle I cant find the exact library and symbol for this device, but only its near relative ep3c25e144. I have some questions: How different is ...
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1answer
1k views

Altera: Change JTAG clock speed

I am having issues with JTAG with my Cyclone IV, specifically the JTAG clock. I am trying to change the JTAG clock frequency somewhere, but can't find where this is done in Quartus II. How can I ...
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389 views

Quartus II: Pin incompatible with a bank it is not on

I am using the pin planner of Quartus II to place my I/O signals on my Cyclone IV pins. I am stuck on the following fitter error: Error (169029): Pin adc0_in[0] is incompatible with I/O bank 3. ...
3
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2answers
218 views

Measuring Power from Altera Dev. Kit (CycloneIII)

The Altera CycloneIII starter kit that I have provides a jumper (J6) that is connected to VCCINT of the CycloneIII FPGA core for what seems to be the purpose of measuring the core's power consumption. ...
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1answer
155 views

Can I use LPDDR with Cyclone III FPGA?

I have seen the Cyclone III datasheet and it claims DDR and DDR2 compatible PHY. But was looking some good LPDDR chips for my design. Could I use the PHY inside of Cyclone III with LPDDR ic? Do you ...
3
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1answer
566 views

Altera Cyclone IV memory block Verilog module

This document explains the various characteristics of the Altera Cyclone IV memory blocks (known as "M9K"). However, there is no mention as to how these modules should be instantiated in Verilog. ...