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0answers
96 views

Can I use full-size 64/72 bit DDR2/DDR3 memory module with CycloneV hardware controller of 24 + 24 bits?

I thinking of using Cyclone V FPGA and its hardware memory controller: There is "Cyclone V FPGA Multiport Memory Controller" document from Altera: ...
2
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1answer
45 views

DDR2 memory addressing error

I have a Freescale MPC8640-based board with 4 Micron DDR2 chips of 128Mx16 density (total of 1GB) attached to it. The memory has been mapped to address range from 0x0000_0000 to 0x3FFF_FFFF. While ...
2
votes
1answer
261 views

What is DDR software leveling?

What is DDR software leveling ? How it is different from DDR2 and DDR3 ? Why it is required and important ? Is there a hardware leveling ? I have found some explanation here about DDR3 and a ...
0
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2answers
367 views

How DDR2 SDRAM works?

I have the Xilinx Spartan-3AN Starter Kit and I need to use the on board DDR2 SDRAM (MT47H32M16CC-XX). Until now I only used Static RAM and this type of memory is new for me. Can someone explain me ...
8
votes
1answer
501 views

Is there a PCB-layout related reasoning behind DDR memory package and footprint?

BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between. Is there a reasoning behind the placement of these pads (in ...
2
votes
3answers
324 views

Single Board Computer (SBC) suggestion for interfacing with DMA

I am taking over a project where a Spartan 6 FPGA provides the interface between an ADC and a DDR2 memory chip. The FPGA takes 16-bit data out of the ADC and stores it into the RAM at a rate of 28MHz. ...
3
votes
1answer
202 views

Crosstalk on PCB

I am currently working on a PCB with DDR2 on it. We are bringing out the DDR2 CLK, DQS signals using pogo pins to make some timing measurements. The length of the pins are about 5 cm. The problem is ...
0
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2answers
156 views

Localized RAM readback errors: chip or timing issue?

I'm currently testing the hardware of a prototype board using DDR2 memory, and I get RAM readback errors when performing a memory test. The errors happen in this fashion: ...
4
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1answer
261 views

Will DDR2 memory work with DM pins tied to LOW, if no data masking is required?

I have a board with the LDM and UDM pins swapped. If they are tied to low, will the memory still 'work', given that data is always written to mod 4 addresses and always using all 4 bytes? Memory is ...
2
votes
2answers
371 views

DDR2-SDRAM Termination methods: passive vs. active

for a project I'm designing I am currently using a simple parallel Resistor Termination on the DDR2-Traces. But I'm wondering, what is the advantage of using a voltage regulator with ...
2
votes
1answer
638 views

Do I need to control trace impedance for DDR2 memory?

I am going to try to interface low-speed 8bit DDR2 chip to FPGA, and I've got some questions crucial to make it work :-) 3) What is up with controlled impedance of PCB traces? Why it's important? ...
3
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1answer
308 views

Do DDR2 chips and controllers have on-die termination?

I am going to try to interface a low-speed 8-bit DDR2 chip with an FPGA, and I've got some questions crucial to make it work: Is that correct that there is on-die termination on both DDR2 memory and ...