# Tagged Questions

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### Number of bits for tag, index, and block in a direct-mapped cache

Suppose you have a 64-byte cache on a system with 16-bit memory addresses. If the cache is direct-mapped and it has 10 bytes of tag overhead in total, how many bits are used for the tag, index, and ...
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### XOR gate; transistor level design [duplicate]

What would a transistor level design of an XOR gate look like?
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### Why does active low even exist?

In my career I've often encountered signals that are active low (Reset being the most common). I've even seen interfaces where all control signals are actively low. To me, this is very unintuitive ...
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### Pullup or direct drive when handling active low inputs/resets?

Active-low reset inputs seem to be a holdover from TTL logic where the falling edge was faster than the rising edge, so the falling edge was decided as more important to increase the maximum possible ...
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### Is this boolean expression reducible?

I have this boolean expression: F1 = a1'a2' + a1a2'. Could it be reduced even more?
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### Designing State Diagram for a 2 input sequence detector

For a lab exercise I have to design a 2-input sequence and Im struggling with the state diagram, as It has 2 inputs, i've designed it with one input before. the sequence to be detected is 1032 which ...
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### Is it possible to combine JK, SR and D filp flops in one circuit… and why?

I am taking a logic design class and the teacher asked this question. I know I can use whatever I want in one circuit, I mean using JK then use SR in another part, but if I was to design a sequential ...
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### Karnaugh Mapping Assignment [closed]

Design a combinational circuit with 3 inputs x, y and z and 3 outputs A, B, and C. When the binary input is 0, 1, 2, or 3. The binary output is one greater than the input. When the binary input is 4, ...
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### Suggestions for Digital Logic Design laboratory projects ? [closed]

What are some simple Digital Design projects that I can make using basic IC's in the laboratory like Logic gates, Counters, registers, mux/demux ... etc?
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### Need help with RTL (Register Transfer Level) circuit implementation - Euclidian GCD algorithm

I'm looking for help regarding the following algorithm and implementing the logic circuit. Here it is in pseudocode: ...
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### single cycle implementation with single memory

I've read that implementing a single cycle cpu requires two memories one for data and one for instructions. Why is this? Using a single memory with two read ports (see figure below) wouldn't it be ...
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### single-cycle design using and shared memory for both data and instruction

This is not really a question on electronics , it's more a question on logical design. I hope this is the right place to ask. How come it is not possible two use a single-cycle design and have a ...
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### Is there a more optimized way of making an incrementer than a full adder?

I'm designing a very simplistic microprocessor as a project to help learn VHDL. So I'm needing something to increment the 8 bit program counter. I will need to increment it by two. Is there a better ...