Digital electronics use a finite number of states, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.

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Implementing a boolean function using decoder and or gates

I am trying to implement the negation of a set of minterms. As a result my function looks something like: \$(A+\bar{B}+C)(\bar{A}+\bar{B}+C)(\bar{A}+\bar{B}+\bar{C})\$ I know how to implement it if ...
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1answer
42 views

Design a sequence detector that detects when the sequence “10”

Design a sequence detector that detects when the sequence “10” occurs in a stream of input (single bit input). Upon detecting “10”, the detector will produce an output of “0”, else output will be “1”. ...
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2answers
104 views

Circuit using logic gates

I'm working on an assignment where there are 3 inputs, 3 LEDs, 4 AND gates, a bread board and 6 NOT gates. I have to design a circuit using the given tools (it's not compulsory to use all the items) ...
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1answer
50 views

What does “number represented by the 5-tuple” mean?

As in from homework problem: Plot this function in K-map: \$F(A,B,C,D,E)\$ is 1 if the number represented by the 5-tuple (A,B,C,D,E) is even or divisible by 3. Does this mean I should ...
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2answers
80 views

Online arithmetic with radix 2 addition

I am having trouble working with OLA(online arithmetic addition) radix 2 SD(signed digit) addition MSDF(most significant digit first). If I have an 8 bits range unsigned number and a redundant and ...
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3answers
109 views

What exactly does a 10-transistor XOR gate look like?

I need a schematic for a 10-transistor xor gate, I have searched everywhere and I see 8, 12, 6, but I can't see 10. What does it look like in a transistor like picture?
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3answers
72 views

Is there any way to interface 4x4 matrix keypad using 2 IO lines

I have two IO lines and wants to interface 4x4 matrix keypad. Using MUX ICs I need 4 IO lines. Is there any method to achieve it using 2 IOs?
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1answer
132 views

Creating a logic function of a burglar alarm system for a bank

This is the problem from homework that I am stuck on: A burglar alarm system for a bank is to be operative only if a master switch at the police station has been turned on. Subject to this ...
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0answers
56 views

Info on the most used calculator ICs on the planet [closed]

Pick any standard (non-scientific, 7-segment) pocket calculator today, and you'll find the functioning to be very, very similar. Here's a generic one: They all have the four basic functions (Add, ...
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2answers
103 views

Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [closed]

The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates. In the first year of Make Magazine - they describe a person who builds a simple ...
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2answers
41 views

Digital selector switch SP4T

I'm building a multimode analogue filter for a synth project I am working on. I've been following some schematics I found in the wild. The project is working nicely on the breadboard so far but I ...
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0answers
41 views

2 Transistor 2:1 MUX with negative waveform

My PTL(Pass transistor logic) 2:1 mux show -ve waveform at at some inputs combination ckt and waveform show below: simulations perform at 180nm tech, 250mhz,1.8v power supply. How to cope this ...
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1answer
26 views

Logism: Add/Subtract 4-bit Oscillation Apparent Problem

I currently have a problem within my circuit design of 4-bit adder that has a function of subtraction in Logisim. My 4-bit adder has an output of 5-bit with maximum of decimal 30 (Because 1111 (15) + ...
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1answer
45 views

How can I trigger other circuits based on specific values of a 12 bit ripple counter?

I've built quite a few circuits but I've never really designed anything from a "schematics first" approach. Mostly just tinkered with designed and code until I got it right. Now, I want to build a ...
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1answer
77 views

Is it possible to construct a NOT gate if given only OR gates and XOR gates?

I was given this problem and I don't think it is possible since if both inputs are zero on a OR gate or a XOR gate, all outputs will be zero. Or am I wrong here?
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1answer
60 views

How can i send bits using a wien bridge oscilator?

so i have a string of bits that my shift register will be outputting one after another, i wanna use a wien bridge to send them into air. if a bit is a "1", i want the wien bridge to send a wave, and ...
2
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1answer
69 views

Clock Ringing/Noise

I'm trying to make a simple 32.768kHz clock circuit. On the datasheet for a crystal that I found, it included the following circuit: simulate this circuit – Schematic created using ...
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2answers
69 views

How do I hold a signal high from one high pulse?

Assuming I send a signal wirelessly to a receiver connected to a fan. if the receiver detects that a pulse is there, it switches on the fan. the fan should stay on until it detects another high pulse, ...
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1answer
36 views

Boolean Matrix and circuits

What are Boolean matrices? How can one represent Digital Circuits using them?Please see if the following link helps? http://comjnl.oxfordjournals.org/content/15/3/247.full.pdf
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1answer
61 views

Boolean Matrices and Transpose

How can one find the Transpose of a Boolean Matrix? Also how does one interpret the logical circuit represented by it.
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1answer
59 views

Floating a digital output pin of an IC

I'm using a FXLS8471Q accelerometer for a project using the SPI interface. The chip uses the same pins for SPI and I2C. To detect which interface the user desires, the chip samples the SA0 pin on ...
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3answers
130 views

Why do 74 series IC's have two ENABLE pins

I am using 74LS154 4 to 16 decoder Link to *.pdf here. It has two ACTIVE LOW 'ENABLE' pins at the input. What is the use of two ENABLE input pins is the question. Most of the 74 series IC's used in ...
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3answers
142 views

Are 3-8 input NAND gates common?

If I have, for example, 4-8 (or more) inputs that I need to AND together (or even NAND or OR) should I look for larger input devices like the 7430 NAND or is common practice to daisy chain multiple ...
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3answers
124 views

Pull up resistor

I'm software, not hardware, and would ask our electronics guy, but he's away on a site visit. Someone on StackOverflow suggested I repost this here. I get the basic idea of a pull up resistor as ...
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2answers
81 views

Interfacing incompletely documented logic signal where resistor affects output voltage level

So I've got this marginally documented 12V logic signal from something I have to regard as a black box that I'd like to interface to a pi or arduino (i.e. c 3V). I have 3 lines - 0V, +12V and signal ...
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1answer
47 views

Determining results for the carry out and sum operations on 8-bit operands

The problems I'm trying to solve are these: Determine the values for the carry C8 C7 C6 C5 C4 C3 C2 C1, given ...
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3answers
57 views

Convert 910 to an 8 bit, two’s complement number

Convert 910 to an 8 bit, two’s complement number. 0000 1001 1111 0111 0100 1000 0001 0010 I convert 910 to binary (910)_10 = (0000001110001110)_2 but when I reverse 10001110 to 01110001 in ...
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2answers
676 views

Simplify a logic expression - Where have I gone wrong?

I am trying to simplify a logic expression but I think I simplified it too much. The expression is as follows: $$\overline{\overline{(A \cdot B)} \cdot C \cdot (\overline{A}+\overline{(B+C)})}$$ ...
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1answer
89 views

2 Transistor XOR Cell Floating Output Problem

I designed the following 2T XOR cell for my full adder purpose: Theoretically it gives correct output for all input combinations. But on Tanner Eda using 180nm technology 5V supply, it gives logic ...
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84 views

6 Transistor Full Adder

I am working on a 6 Transistor Full Adder whose circuit diagram is The circuit works fine but there is a problem: it needs a 25k resistor at XNOR and SUM point to show the complete Full Adder ...
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2answers
146 views

Simplify a logic expression

I need to simplify the following logic expression: $$\begin{array}{|c|c|c|c|c|} \hline A & B & C & X & SOP \\ \hline 0 & 0 & 0 & 0 & \\ \hline 0 & 0 & 1 & ...
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1answer
144 views

Making 2-input AND gate, 2-input OR gate and NOT gate using only the “SAND” gate

Suppose there is a special gate called a SAND gate (Single-inversion AND) that looks like this: How can I make 2-input AND gate, 2-input OR gate and NOT gate using only the SAND gate? The truth ...
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3answers
90 views

Simple NOR gate (transistor-level) diagram

My question here is simple: I cannot understand how the input flows throughout the circuit. I understand the P and N type transistors; I could see why if A and B are both 0, and pass through the ...
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1answer
69 views

Lower Voltage LED organ

I am interested in adapting this Jameco kit schematic to my own needs. I have run into an issue though. I am not sure how to lower the voltage requirements. This circuit is built for 12V, I would like ...
2
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1answer
101 views

Practicality of Logic Gates for a newcomer

For my project, I was thinking of making a password lock using logic circuits. I have a basic understanding of logic gates and have a few designs. However, I have very little experience in how to ...
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3answers
82 views

Double Li-ion charging circuit logic

I'm currently trying to adapt a single li-ion battery charger based on the TP4056 to work with charging more than one battery. The idea is to use a logic circuit that is controlled by the IC's "FULL" ...
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2answers
53 views

Signal-driven 3 output logic gate decoder or switch?

I need to build a simple logic gate circuit such that when a single input signal or switch goes low it alternately activates one of three outputs as high. That is, every time it goes low the currently ...
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2answers
50 views

Difference between LVPECL and PECL

I want to use a counter MC100EP016A which requires PECL clock input. What is the difference between LVPECL and PECL? If a clock source provides LVPECL clock how can I use it with the MC100EP016A ...
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3answers
455 views

Logic design to circuit — how is it generally done?

So I've designed this CPU with purely logical components (basic logic gates), now how would I go about converting it into a circuit? I know that logical gates can be implemented using transistors, but ...
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2answers
66 views

Why increase in resistance of register used in circuit show lesser average power dissipation

I am working on 6 transistor full adder circuit. Red marked resistors (25k) are used to show all pattern of full adder correctly. But it show wired behavior. When I increase resistance from 25k to ...
2
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2answers
157 views

Equivalent of IC4026

I have tried to make a reaction timer using IC 4026. But due to unavailability of IC 4026 I want to replace it. Can I use 4017 instead of 4026?
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1answer
96 views

Beep patterns generator

I would like to generate the following beep patterns using a piezo buzzer: Single long beep Two short beeps Single short beep Is there any specific chip I can ...
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0answers
60 views

How ALU Perform decrement operation using LOGIC Zero

I google many ALU Block diagram for decrement operation.all same as shown below. This 1 bit alu perform 8 operation depending upon select line status Theoretically all operation seems works ...
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1answer
32 views

Initial state of SN74AUP2G80 dual FF

My understanding is that a basic FF will in general power-up into a meta-stable state that then resolves to either H or L (more or less quickly). My question is, does this apply to current ...
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1answer
94 views

n-channel MOSFET source load alternative

I'm trying to drive some RBG leds using MOSFETS. Let's say I have 2 individually RBG LEDS, each controlled by 12V, with each R, B and G with its own output to GND. What I want to control, is to be ...
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2answers
95 views

What is the meaning of Vtt

I was looking at the data sheet of a counter IC and the connection circuit diagram showed two connections: Vbb and Vtt What do ...
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1answer
60 views

Single Die Roll Counter Wrap Around Nested Ternary Conditional

I have to emulate a single die roll, therefore it needs to wrap back to one at 6. `D1 and `D6 correspond to my 3-bit state ...
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1answer
44 views

Minimum cover for this K-MAP to find minimum SOP; which is better, and why?

I used this K-MAP to find the minimum sum-of-products expression for this collection of minterms. I see that minterm-one could also have been "covered" by grouping it with minterm-five. I opted to ...
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40 views

Trouble analyzing this JK-Flip-Flop (negative edge triggered) timing diagram

Can someone check to see if this timing diagram for a negative-edge-triggered flip-flop looks correct? I see that as it's negative-edge triggered (bubble at clock input), and thus action occurs at ...
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0answers
47 views

what is the approach to design edge triggered d flip flop? [closed]

i know the circuit. I implement it using verilog and it giving result correct. like when we have to design any digital circuit we draw truth table. Optimize circuit using K-map and then implement. In ...