Digital electronics use a finite number of states, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.
6
votes
3answers
106 views
Understanding AND logic gate
I drew an AND gate as follows which mimics this diagram:
(source)
I understand how current flows between A and B(when both inputs are logical 1) because there is difference of voltage, maybe 6V, ...
1
vote
3answers
147 views
What components can an FPGA replace/emulate?
I've been under the impression that FPGAs were merely, well, field-programmable gate arrays, but I've seen some example schematics with resistors, capacitors, and such in them. As such, can an FPGA ...
1
vote
1answer
35 views
Purpose of the logic gate configurations on the Kenbak-1
I was just looking through the schematics of the Kenbak-1 computer (long story), and I found this:
simulate this circuit – Schematic created using CircuitLab
I hurt my brain a little bit ...
4
votes
3answers
138 views
Preference of NAND & NOR gates
What's so special about NAND & NOR(apart from being universal gates) that most books on digital design try to emphasize design using these gates?
Is it easy to manufacture or something?
-12
votes
0answers
101 views
I need to compete against AT&T's uverse digital receiver boxes [closed]
So someone made a bet that I couldn't make a better service than AT&T provides, even with $40,000,000.00 U.S.D.
That angered me, and just to give them a little taste of what I CAN do with ...
2
votes
1answer
95 views
Analogue and Digital Voltage Rail
What's the difference between an Analogue and Digital Voltage Rail?
Why their grounds have to be different?
1
vote
2answers
58 views
Designing a synchronous counter with d flip flops
I have to design a counter with two inputs: x and y. If y = 0, the counter behaves like a ...
-1
votes
2answers
134 views
Exotic logic gate
I have a negation operation and two types of "logic gates" with following outputs (A, B are inputs):
"gate" 1:
...
4
votes
1answer
47 views
How to implement HD74HC32 (quadruple 2-input positive-OR gate)?
I'm struggling to implement the HD74HC32 (quadruple 2-input positive-OR gate) package:
My breadboard looks as following:
Notes:
...
3
votes
1answer
117 views
Is there such a thing as a circuit that outputs 1 if the input is high-impedance, and 0 otherwise?
I am trying to design a circuit that outputs a logical 1 if the input is high-impedance, and a 0 otherwise.
Any idea how I might implement this? I would prefer to use off-the-shelf parts (no ...
1
vote
2answers
108 views
how to make a clock like this?
Could someone help me to make a clock that has outputs like this
there are 3 clock outputs
I have a reference schematic here, and this clock has 4 output and it made up of 2 flip flops, it uses ...
1
vote
1answer
113 views
How to understand the block diagram of microcontroller Architecture
I am started learning pic18f4550 controller . I find it difficult to understand the architecture block diagram . i cant understand how peripherals, cpu core (eg ALU), data bus , program bus are ...
4
votes
2answers
96 views
When is it appropriate to galvanically isolate components/subsytems?
As the question implies, how do you determine when it is appropriate to galvanically isolate parts of the same electrical system from one another?
For example, I'm currently constructing a tube ...
2
votes
2answers
104 views
Slow clock edge causing issues with D flip flop behavior
I'm trying to use a D flip flop and a pushbutton as a simple switch. My goal is this: every time I press the button, the output of the FF will switch state.
I put a circuit together in a simulator ...
1
vote
2answers
47 views
Constructing an Encoder
I understand an Encoder is 2^n input lines and n output lines`.
I want to construct an Encoder from scratch so I can understand how it works, so that I can construct any other Encoder in the future.
...
0
votes
1answer
84 views
Binary to Gray Code
I have built this 3-bit Binary to Gray Code circuit. I would like to know if it is correct.
I have used 2 Xor gates.
0
votes
1answer
54 views
Turn S R Latch Using a NOR gates into NAND
I can't post a picture so the question will use Boolean Algebra. For me an SR Latch is
S NOR Q' = Q
R NOR Q = Q'
I will represent Q' as P since Q' might be ...
0
votes
0answers
24 views
Resource for learning Digital Electronics [closed]
I would like to learn Digital Electronics(Boolean Algebra,GATES,K-Map,GreyCode,SHIFT registers,FLIP FLOPS).
Would you recommend resources similar to Murach's Book Series or Head First Series.
-3
votes
1answer
67 views
What is Block diagram? [closed]
I have to design a simple 8 bit processor with VHDL and the first step is to draw a single or schematic block diagram including registers, arithmetic operations, multiplexers, busses and control ...
0
votes
1answer
41 views
Adding 4-bit numbers to 16-bit shift register
I am trying to find a way to add four 4-bit binary numbers to a 16-bit shift register, one(group of 4 bits) by one. This way I can store 4 decimal numbers(0-9) in the register, adding them by pushing ...
0
votes
1answer
85 views
Sequential logic counters
I have an assignment to create a counter that counts in the following way depending on input y
if y = 0 -> 0, 6, 3, 2, 1, 0...
if y = 1 -> 0, 5, 4, 7, 2, 1, 0...
Also it has another input x if x = ...
1
vote
1answer
60 views
How to calculate Gate Delays in normal Adders and Carry Look Ahead Adders
In my textbook the gate delays for the n-bit ripple adder is given as \$ 2n \$ for \$c_n\$ bits and \$ 2n-1 \$ for \$ s_n-1 \$ for the circuit as shown below:
But, for a 4-bit Carry Look Ahead ...
1
vote
3answers
53 views
How do I decide the bandwidth of a driver through 'input transition rise and fall rate'?
I am carrying out a design with a driver:74LVC1G125 datasheet of 74LVC1G125. Signal that will go through this driver is about 600khz so I have to know the bandwaidth of 74LVC1G125. I have read the ...
3
votes
4answers
58 views
N-Ch FET with open-drain output
I stumbled across this line in this datasheet (page 10):
Serial Data Output Pin. Internal N-Ch FET with open-drain output that
requires external pull-up resistor. It shifts out the previous ...
0
votes
1answer
90 views
Circuit design example
What will a combinational logic circuit look like using any basic gates having the output=1 when the input=110 and 101?
1
vote
2answers
55 views
Parameterized net width in Verilog
Is something like this possible ?
parameter width;
wire[width-1] a_net = (width)'b0;
I basically need a variable to control the width of the right hand side. I ...
1
vote
2answers
131 views
Instruction Register? Whats it's purpose/how is it connected? (And what happens after)
So im learning the SAP 1 Computer Architecture. Most things I get pretty well, but from what I understand: (Lets pretend it's an 8bit and address is 4 bits and opcode is 4bit)
...
4
votes
3answers
101 views
FPGA Logic Gate Count
I found an FPGA board that I liked. It uses a Xilinx Spartan 6 LX45. When I went to the datasheet for the Spartan 6 series, it only said that there were 43,661 logic cells. How many gates does that ...
1
vote
1answer
75 views
Problem with the 74160 decade counter
As I am experiencing with different TTL components, I am having a ton of trouble with the 74160 decade counter. I don't know if it's my inexperience or if I'm dealing with a malfunctioning IC, but the ...
3
votes
1answer
134 views
Improving a Push-Button Debouncing Circuit
I'm having problems testing a 7490 decade counter, the switch sometimes toggles 2 or 3 counts (it's a pushbutton). This is already using this debouncing circuit I found:
(well great, I can't post ...
1
vote
1answer
39 views
Technology mapping
The function given is:
g=ACFG + ADEG + DHJ + BCFI
and i am asked to perform the reconverge theorem on this function which means taking all possible pairs of LUT that share the same input merge them ...
2
votes
1answer
53 views
Optimal Solution for function using Distributed Law [closed]
I was given the function:
\$ h = 𝐴.𝐵' + 𝐶 + 𝐵.𝐶'.𝐷 + 𝐵.𝐸 + 𝐵'.𝐶.𝐷'.𝐹 \$
I was told to construct it in the most optimal way using only any size NOR gate by applying distributive law.
I ...
0
votes
1answer
31 views
Logisim - Tunnel that outputs the OR result of all of its inputs
Consider this screenshot:
When the two values differ, I get this:
This makes sense, but it's a problem. I would like the tunnel to function like this: when it's getting mixed values, it outputs ...
-9
votes
1answer
81 views
Circuit Diagram Controller [closed]
I want to make a circuit diagram which will:
Read the speed of a servo
Divide the speed of servo
With the result of the division will be controlled the speed of an other motor like this: Servo ...
-5
votes
0answers
67 views
Applications with kernels that can be accelerated in hardware [closed]
Could you give me a list of applications with kernels that can be accelerated in hardware?
Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others.
To ...
1
vote
4answers
103 views
What is important in computer clocks' signal: signal edges or intervals when signal is stable? Will multiple value propagation occur?
I am trying to figure out some basics of digital electronics. We have all seen the squared graph of the computer clock signal:
I have read multiple articles on the Internet and still can't figure ...
0
votes
1answer
102 views
Help designing a simple counter
I would like to create a project to implement an asynchronous counter (I am just learning about sequential circuits), in which 2 8-segment displays will receive input from some sensor and will ...
2
votes
2answers
142 views
Multiplexing large LED matrix
I have a project which involves building a 64 x 48 (3072) LED matrix driven by a Raspberry PI computer. I am a first-year computer engineering student so I am still inexperienced with shift registers ...
2
votes
2answers
80 views
Easy resource to learn solving counter problems?
Could anybody please point me some direction on where I can learn to solve simple counter problems like counting in a given sequence using a given flip-flop? For example:
Create a counter counting ...
0
votes
1answer
56 views
Using on and off switches and logic gates
So I have 2 switches Representing:
Bit A
Bit B
And then I have :
AND gate
OR gate
Not gate
Some other gates like adder and comparator
I used the method described here because the Adder & ...
-3
votes
1answer
76 views
Building 8bits alu on breadboard [closed]
I want to build a 8 bit alu containing :
- 8 bit comparator
- 4 inverters
- 2 and gates
- 2 or gates
- 2 full adder 4 bits
- 10 leds
- 8 mux 8 to 1
e
My question is how much volt do I need to make ...
0
votes
0answers
60 views
Connecting RJ11 output to TTL to USB converter input through 5 pin TTL
I have a problem in connecting output of RJ11 to TTL socket of the TTL to USB converter.
Actually, I have a micro controller based device which has an RJ11 female port having six pins in it, which I ...
0
votes
3answers
93 views
Logic Circuits Vs Transistor Power Circuits
I have need to invert a signal to drive fets with hard/fast rise and fall times. I was told in another thread to use an inverter (NOT chip). This makes perfect sense to me since logic chips are ...
0
votes
2answers
84 views
Can Transmission gates be used to implement 3 State Logic?
In my application i need to use a common line shared between two peripherals, i have to indicate to the devices whenever the bus is free or not, hence i can't have push-pull output where the output is ...
2
votes
4answers
144 views
Most efficient way to select between 10 large buses?
I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so?
Currently I have the following SystemVerilog implementation
...
2
votes
1answer
66 views
In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?
I'm writing some verilog and simulating it using modelsim. I have a block that looks like this:
...
0
votes
2answers
89 views
Digital bargraph display driver circuit
.For a project I need to display a progress bar of the activity performed by my MCU. For this purpose I am going to use a bargraph display, but the problem is that bargraph display driver driver ...
1
vote
0answers
142 views
Error-Detection Circuit — How does this work?
I'm currently studying for finals (I have the solutions here already, so this isn't helping me bypass doing homework or anything like that.)
My professor has done an unsatisfactory job explaining ...
2
votes
3answers
139 views
Help with designing a circuit with logic gates
I want to build a circuit with the following design:
3 inputs
1 NOT gate
2 AND gates
1 OR gate
This is my truth table:
...
0
votes
0answers
69 views
Using D-Flip Flop for MSB and JK-FF for LSB
I have the above question as an exercise. I know how to do all of the operations. However, I didn't get the point where it says "You are required to use a D-FF for the
MSB, (A) and a JK-FF for the ...
