Digital electronics use a finite number of states, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.

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AND gate mysteriously and ludicrously slow

I've made a 3 input AND gate from 4 NANDs in order to daisy-chain 3 motor drivers jrk 21v3 and get the current value out of them. The problem is, the command is sent OK, the driver responds OK with ...
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5answers
239 views

Are all sequential circuits based on cross-coupled NAND or NOR gates?

So far, all the sequential circuits I see in the textbook use cross-coupled NAND or NOR gates. Is it possible to design a sequential circuit without them?
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0answers
36 views

Designing 1-to-2 demultiplexing circuit with a custom truth table

I'm trying to build a circuit with following truth table with CMOS logic. Pins are: I and A are inputs ...
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1answer
47 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
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1answer
31 views

How should this code look like in verilog?

I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
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42 views

Binary counters, homework help

When doing State Tables, in the 'Next State' column, is it always 'Present State' +1 (or if we have some arbitrary combination, the number after), even in repeating binary counters?
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0answers
49 views

What could this PLA be doing?

The picture below shows a PLA, I have done part (a) and found out that; F0 = A0 xor B0 F1 = A0B0 + (A0' + B0')(A1 xor B1) F2 = A0B0(A1 + B1) + A1B1 What may this circuit be doing, I can't see a ...
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0answers
35 views

Formation of logic gates using specific number of gates [on hold]

There are atmost 2^{2^{n/4}} circuits formed using n inputs and 2^{n/8} number of logic gates. How? Please help me.
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3answers
66 views

Breadboard with high frequency digital signals

I'm trying to interface an ADC chip with my FPGA. The ADC is on a breakout board that fits nicely into my breadboard (.1" pin spacing). The clock input from my FPGA into the breakout board is 12.5 ...
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1answer
45 views

How do you reduce an 8 output ALU to a 4 or 3 output ALU?

I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...
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1answer
205 views

Divisible-by-2 Circuit Help!

I'm having a little trouble with my boolean algebra and I was hoping you all can help me out. I've been given the task of designing a circuit that takes in a binary 4 digit number (X3X2X1X0) and ...
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1answer
42 views

Modify MEMORY component to more sensibly Load/Store value?

I have created the following electrical circuit using Logisim: My ALU takes in 2 8-bit values and performs the operation set forth by the [Op Setter]. In particular, when the [Op] code is [100], ...
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1answer
88 views

What's the point of Karnaugh maps?

You can't use them for more than 5 variables efficiently and no "real life" circuit has only 5 variables (except for the simplest of them). So what's the point of them? They seem pretty useless for ...
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2answers
53 views

Bias headphone audio signal for use with digital potentiometer?

I am attempting to control speaker volume via a digital potentiometer, the problem being that audio signal goes both above and below 0V, for regular potentiometers this is no problem but for digital ...
2
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3answers
416 views

Where does the power supply go in an SR Latch?

I understand how an SR Latch works: is S is 1, it will set Q to 1. If R is 1 it will set Q to 0. If both S and R are 0, the value of Q should remain unchanged (right?). So the circuit has these ...
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2answers
310 views

Why are synchronous counters synchronous?

Doesn't the input signal having to propagate through the AND gates cause a propagation delay anyway? With the asynchronous counter the delay was caused by the clock signal - with the synchronous ...
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1answer
66 views

Logic gates. BCD Multiplication. Karnaugh maps (I think)

I have to draw minimum combination of logic gates that multiply any BCD number with a 7. Output is also in BCD. It probably has something to do with Karnaugh maps, that's how we do this sort of ...
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1answer
67 views

When setting pin as input it getts pulled high, why?

I've hooked up a push button to GP1 and a LED to GP2 on my PIC12F683 and this is my code: ...
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1answer
35 views

Connect ALU to CPU in Logism Circuit Design and output to 7-segment Display?

I've been playing around in Logisim to get some experience in designing basic electrical circuits. While I'm sure not the best, I was able to put together a functional ALU: 1-Bit: This ALU is ...
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0answers
27 views

Possible to copy a circuit from 1 Logisim .circ file into another Logisim .circ file?

I'm using Logisim to experiment with Electrical Circuit design, and I was wondering if it is possible to copy a circuit created in 1 Logisim .circ file and place it into a different Logisim .circ file ...
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2answers
82 views

Circuit to throw out 1st bit of every 17-bit sequence?

I have a system that currently uses two Maxim DS1867 digital potentiometers in a daisy-chain configuration. In a new addition to the system I would like to use a new digital potentiometer part like ...
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2answers
58 views

Logic circuit with not gate-stability

simulate this circuit – Schematic created using CircuitLab Why is the first circuit unstable and the second one stable?
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1answer
116 views

Can someone implement this circuit using discrete components, please? [closed]

Can someone implement this circuit using discrete components, please?
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1answer
316 views

Design a 3-to-8 Decoder Using Only Three 2-to-4 Decoders

Using only three 2-to-4 decoders with enable and no other additional gates, implement a 3-to-8 decoder with enable. The inputs of the resulting 3-to-8 decoder should be labeled X[2..0] for the code ...
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2answers
83 views

How does one implement the following function with these tools provided?

Suppose I have a function defined as follows, such that it is expressed in POS form, with the product of the following max terms of 4 variables (A,B,C,D): 0,3,4,7,9,10,12,15 and I only have a 4 to 1 ...
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4answers
226 views

ICs Powering On With Random Values

I've been prototyping a circuit for a first year university engineering project and I've been running into some problems with one section of the circuit that has really stumped me. Basically the flip ...
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2answers
78 views

Replace mechanical switch with transistor? MOSFET? Relay?

If I have a switch in some consumer electronics that I take apart, and want to replace a mechanical switch with a digitally controlled one, which component should I use? The only problem I see with ...
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2answers
72 views

Designing an ABBA circuit (3 input, 2 output) inputs: (GND, +V, Logic)

I'm working on a relatively simple Arduino project and want to reach an elegant solution for a circuit. I'm not sure if there is an existing IC for what I want to do, but here is a diagram for what ...
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4answers
2k views

Why is the + sign commonly used as logic OR operator?

A few days ago I was asked, why it is pretty common to use the + instead of the v symbol as the boolean OR operator in digital ...
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2answers
96 views

Building “AND” and “OR” gates from tri-state drivers & inverters [Answered]

I'm working on a digital circuits assignment which asks me to prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. My attempt at doing so would be ...
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0answers
35 views

Simulation to find worst-case delay path

Assume there is a combinational logic function implemented by a CMOS logic inside (1 Pull Up network and 1 Pull Down network). From the intuition of RC Tree elmore delay analysis, we know that input ...
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1answer
52 views

Replace potentiometer with digital version (Speakers)

I am trying to get my PC speakers to be controlled by my arduino. I've taken apart the control and it seems very straight forward, just need a few questions about subbing the manual pots for digital ...
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2answers
349 views

Switching between battery and USB using diode OR logic

I have a Raspberry Pi that is powered by a USB cable from a Samsung charger. Now since my college has frequent power cuts, I designed a basic switch to automatically switch between a portable mobile ...
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0answers
64 views

Implementing a boolean function using decoder and or gates

I am trying to implement the negation of a set of minterms. As a result my function looks something like: \$(A+\bar{B}+C)(\bar{A}+\bar{B}+C)(\bar{A}+\bar{B}+\bar{C})\$ I know how to implement it if ...
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1answer
62 views

Design a sequence detector that detects when the sequence “10”

Design a sequence detector that detects when the sequence “10” occurs in a stream of input (single bit input). Upon detecting “10”, the detector will produce an output of “0”, else output will be “1”. ...
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2answers
109 views

Circuit using logic gates

I'm working on an assignment where there are 3 inputs, 3 LEDs, 4 AND gates, a bread board and 6 NOT gates. I have to design a circuit using the given tools (it's not compulsory to use all the items) ...
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1answer
54 views

What does “number represented by the 5-tuple” mean?

As in from homework problem: Plot this function in K-map: \$F(A,B,C,D,E)\$ is 1 if the number represented by the 5-tuple (A,B,C,D,E) is even or divisible by 3. Does this mean I should ...
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2answers
99 views

Online arithmetic with radix 2 addition

I am having trouble working with OLA(online arithmetic addition) radix 2 SD(signed digit) addition MSDF(most significant digit first). If I have an 8 bits range unsigned number and a redundant and ...
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3answers
130 views

What exactly does a 10-transistor XOR gate look like?

I need a schematic for a 10-transistor xor gate, I have searched everywhere and I see 8, 12, 6, but I can't see 10. What does it look like in a transistor like picture?
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3answers
84 views

Is there any way to interface 4x4 matrix keypad using 2 IO lines

I have two IO lines and wants to interface 4x4 matrix keypad. Using MUX ICs I need 4 IO lines. Is there any method to achieve it using 2 IOs?
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1answer
164 views

Creating a logic function of a burglar alarm system for a bank

This is the problem from homework that I am stuck on: A burglar alarm system for a bank is to be operative only if a master switch at the police station has been turned on. Subject to this ...
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2answers
121 views

Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [closed]

The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates. In the first year of Make Magazine - they describe a person who builds a simple ...
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2answers
60 views

Digital selector switch SP4T

I'm building a multimode analogue filter for a synth project I am working on. I've been following some schematics I found in the wild. The project is working nicely on the breadboard so far but I ...
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0answers
43 views

2 Transistor 2:1 MUX with negative waveform

My PTL(Pass transistor logic) 2:1 mux show -ve waveform at at some inputs combination ckt and waveform show below: simulations perform at 180nm tech, 250mhz,1.8v power supply. How to cope this ...
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1answer
42 views

Logism: Add/Subtract 4-bit Oscillation Apparent Problem

I currently have a problem within my circuit design of 4-bit adder that has a function of subtraction in Logisim. My 4-bit adder has an output of 5-bit with maximum of decimal 30 (Because 1111 (15) + ...
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1answer
47 views

How can I trigger other circuits based on specific values of a 12 bit ripple counter?

I've built quite a few circuits but I've never really designed anything from a "schematics first" approach. Mostly just tinkered with designed and code until I got it right. Now, I want to build a ...
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1answer
79 views

Is it possible to construct a NOT gate if given only OR gates and XOR gates?

I was given this problem and I don't think it is possible since if both inputs are zero on a OR gate or a XOR gate, all outputs will be zero. Or am I wrong here?
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1answer
102 views

How can i send bits using a wien bridge oscilator?

so i have a string of bits that my shift register will be outputting one after another, i wanna use a wien bridge to send them into air. if a bit is a "1", i want the wien bridge to send a wave, and ...
2
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1answer
88 views

Clock Ringing/Noise

I'm trying to make a simple 32.768kHz clock circuit. On the datasheet for a crystal that I found, it included the following circuit: simulate this circuit – Schematic created using ...
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2answers
73 views

How do I hold a signal high from one high pulse?

Assuming I send a signal wirelessly to a receiver connected to a fan. if the receiver detects that a pulse is there, it switches on the fan. the fan should stay on until it detects another high pulse, ...