Tagged Questions

-5
votes
0answers
61 views

Applications with kernels that can be accelerated in hardware [closed]

Could you give me a list of applications with kernels that can be accelerated in hardware? Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others. To ...
-1
votes
0answers
40 views

HD-SDI to SD-SDI

I need to convert a HD-SDI signal to SD-SDI. I have been looking into deserializers and fpga, but have not found a good solution yet. How can this be done? Preferred is a "simple" solution, that ...
2
votes
4answers
134 views

Most efficient way to select between 10 large buses?

I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so? Currently I have the following SystemVerilog implementation ...
2
votes
1answer
65 views

In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?

I'm writing some verilog and simulating it using modelsim. I have a block that looks like this: ...
-1
votes
1answer
130 views

Best FPGA to work with [closed]

I want to work on DSP and artificial intelligence for my freshman project, I was thinking on make an FPGA based system, the problem is that I have little experience working with FPGA's; I already know ...
6
votes
2answers
94 views

process timing on FPGA

I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one ...
2
votes
0answers
78 views

Digital automatic gain control? [duplicate]

Possible Duplicate: Calculating dBFs from RSSI My RF chip doesn't have any RSSI output, just ADC I and Q. I was wondering is it possible to determine RSSI from ADC's I and Q values and ...
0
votes
1answer
139 views

Regular or Irregular Hardware?

I have a hardware structure (described in logic diagram consisting of adders and multipliers) that is extremely regular, i.e., one small hardware is repeated again and again in the structure with ...
2
votes
1answer
245 views

Should I use pull up resistors in this configuration?

I am interfacing a 3.3V FPGA to a 5V DSP. I am using this bidirectional voltage transceiver: http://www.nxp.com/documents/data_sheet/GTL2000.pdf In the diagram in page 4 they're using pull up ...
1
vote
3answers
153 views

Ultra high bandwidth serial data stream

I have a ultra high bandwidth data stream (USB 2.0 Highspeed), on which I need to add an header for synchronization. This needs to be done, since the datastream needs to be transmitted wireless on a ...
2
votes
2answers
781 views

Syncing Signals with Global Clocks in FPGAs/CPLDs and Edge Detection

I am a newbie in digital logic design and I'm trying to get my head around syncing external signals to the global clock in an FPGA. For example, the SCK signal/clock fed to an FPGA by the SPI Master. ...
8
votes
2answers
907 views

When do I need to use a clock buffer IC?

I am designing a circuit and PCB for driving 7 DACs from an FPGA. (DAC is AD9762) Would it be possible to drive the clock inputs on all 7 DACs with a single clock output (from a PLL output pin) of ...
0
votes
0answers
143 views

Logic Design and FPGA [closed]

I'm a student in the fourth year in the faculty of the electronic engineering in Egypt. I'm so interested in studying computer architecture and hardware design of RAMs, CPUs ,etc. I need to learn ...
11
votes
6answers
645 views

What are the advantages of using FPGAs over TTL in intro computer architecture?

I teach the one and only computer architecture course at a liberal arts college. The course is required for the computer science major and minor. We do not have computer engineering, electrical ...
2
votes
1answer
138 views

System Generator: a block similar to a three state logic

does anyone what is the xilinx block for getting a three state logic?