Tagged Questions

2
votes
2answers
137 views

Difference between RTL and Behavioral verilog

Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
2
votes
3answers
100 views

VHDL Error (Simple Expression Expected)

I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the ...
2
votes
2answers
112 views

VHDL code not compiling

I'm new to VHDL and I cannot seem to get my code to compile. I've looked over the code to the best of my ability, but I do not see anything wrong with it from my current basic understanding of how it ...
3
votes
3answers
123 views

VHDL Logic Simplification

I've been having a common reoccurring issue when I write VHDL code. I end up writing code similar to this (as an example): ...
3
votes
1answer
194 views

How to embed a clock oscillator inside a digital block? Specifically, how is this defined for Synopsys DC?

I have to embed a clock oscillator inside my logic block for layout purposes. It's not an option to leave this block out and just bring the clock port in. Is there any way to define an internal net as ...
2
votes
1answer
190 views

RAM writing simulation in VHDL

Writing a value to RAM is a small part of my project, everything is working, but I cannot explain one thing related to RAM/digital timing. I will write a description in regards to picture I added. ...
2
votes
2answers
788 views

Syncing Signals with Global Clocks in FPGAs/CPLDs and Edge Detection

I am a newbie in digital logic design and I'm trying to get my head around syncing external signals to the global clock in an FPGA. For example, the SCK signal/clock fed to an FPGA by the SPI Master. ...
0
votes
0answers
143 views

Logic Design and FPGA [closed]

I'm a student in the fourth year in the faculty of the electronic engineering in Egypt. I'm so interested in studying computer architecture and hardware design of RAMs, CPUs ,etc. I need to learn ...
2
votes
2answers
936 views

What template in Microsoft Visio would one use to lay out a digital design?

What template in Microsoft Visio would one use to lay out a digital design? I draw up many schematics for the Adv. Digital Design course I'm in and cannot find the right template. Flow charts are too ...
4
votes
4answers
860 views

Is there a more optimized way of making an incrementer than a full adder?

I'm designing a very simplistic microprocessor as a project to help learn VHDL. So I'm needing something to increment the 8 bit program counter. I will need to increment it by two. Is there a better ...
4
votes
2answers
295 views

Is there a free cross-platform tool for pure digital gate-level schematic design and simulation?

I'm searching a software tool for teaching purpose in order to teach students digital hardware (starting from logic gates level). Do you have something in mind that will allow making simple graphical ...