Tagged Questions
1
vote
2answers
78 views
Post synthesis level simulation xilinx xst
I have written a verilog code and it is working fine at behavioral simulation level. After this I went for synthesizing the design using XST tool in Xilinx ISE 13.2. Running the post simulation level ...
2
votes
2answers
136 views
Difference between RTL and Behavioral verilog
Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
2
votes
3answers
98 views
VHDL Error (Simple Expression Expected)
I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the ...
0
votes
1answer
327 views
recommandation webpage/book to learn asmd chart over using verilog
I have searched so many website to take background about how asm chart is used in verilog code.However, I could not find any web cite with sufficient examples to learn asm chart. Can anyone give or ...
4
votes
2answers
295 views
Is there a free cross-platform tool for pure digital gate-level schematic design and simulation?
I'm searching a software tool for teaching purpose in order to teach students digital hardware (starting from logic gates level).
Do you have something in mind that will allow making simple graphical ...
