Tagged Questions

1
vote
2answers
28 views

Parameterized net width in Verilog

Is something like this possible ? parameter width; wire[width-1] a_net = (width)'b0; I basically need a variable to control the width of the right hand side. I ...
-5
votes
0answers
63 views

Applications with kernels that can be accelerated in hardware [closed]

Could you give me a list of applications with kernels that can be accelerated in hardware? Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others. To ...
2
votes
4answers
137 views

Most efficient way to select between 10 large buses?

I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so? Currently I have the following SystemVerilog implementation ...
2
votes
1answer
65 views

In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?

I'm writing some verilog and simulating it using modelsim. I have a block that looks like this: ...
0
votes
1answer
87 views

Do case statements inside a for loop work in verilog?

I am doing a code for radix-4 booth encoding for 8*8 multiplication. The logic is correct and there are no errors or warning. The output am getting is totally unrelated. i have posted the code below ...
1
vote
2answers
78 views

Post synthesis level simulation xilinx xst

I have written a verilog code and it is working fine at behavioral simulation level. After this I went for synthesizing the design using XST tool in Xilinx ISE 13.2. Running the post simulation level ...
2
votes
2answers
137 views

Difference between RTL and Behavioral verilog

Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
2
votes
1answer
115 views

How to find the critical path delay of a big combinational block

I have a 54*54 multiplier, i want to find the critical path delay.how do i go about, should i clock the module in order to find the delay?
2
votes
1answer
107 views

What does non-combinational area represent in synopsys design compiler

I have designed a ripple adder using full adders. In order to find delay incurred to perform this addition I included a clock in each full adder module. In my main code I instantiated these modules to ...
2
votes
2answers
142 views

Verilog asynchronous reads of regs - and design question

I'm trying to understand what the following bit of behavioral code, what kind of hardware it turns into: ...
2
votes
1answer
93 views

Verilog proper use of high impedance value?

In verilog, what are some examples of when one should opt to use the high impedance value Z? Thanks
3
votes
1answer
636 views

Verilog memory designs with multiple read/write ports - poor circuit performance when synthesized?

I am interested in designing (with verilog) some memory structures that have multiple (let's say 3) read/write ports. I've been doing some studying on architecture and what I've heard is that these ...
2
votes
1answer
148 views

Understanding basic behavioural Verilog: simple RAM module

My interest is more in what the actual synthesized circuit will look like, and what components it will be built from. Here is an example 64x1 RAM module: ...
0
votes
2answers
110 views

Verilog modules: estimating power consumption before physical design

What can a designer do to get an idea of how much power a various module with consume? It seems like there should exist some decent heuristics to go about doing this, else we would have to wait until ...
0
votes
2answers
129 views

Splitting a bit array in Verilog

i am designing a basic AES algorithm on verilog, and i need to split a 1828 bits array into 16 parts each one of 8 bits, for example (basic no 128 length example), if i receive in my 8 to 2 splitter ...
3
votes
2answers
263 views

Why does design_vision compile my carry-lookahead adder into a ripple-carry adder?

At my school we have Synopsis "design_vision" in the computer labs. I don't know how to use any of the features so to me it's just a schematic-drawing tool. Out of curiosity, I hand-coded in Verilog ...
0
votes
1answer
328 views

recommandation webpage/book to learn asmd chart over using verilog

I have searched so many website to take background about how asm chart is used in verilog code.However, I could not find any web cite with sufficient examples to learn asm chart. Can anyone give or ...
2
votes
3answers
437 views

recommendation to learn verilog

To learn verilog, can anyone recommend any web-page or book? I have never seen such type of a language before, so what you recommend should be for beginner.