# Tagged Questions

Digital electronics use a finite number of states, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.

160 views

### multiply binary numbers [closed]

Is it any book which explains how to multiply binary numbers and how to create appropriate digital circuit schema?(i.e. digital schema which compute the multiplication of the binary numbers).
917 views

The arduino reference states that you would use the following code to read the value from analog pin #5: int val1 = analogRead(5); However to read from digital ...
147 views

### Are most RAM/Memory cells done with Inverters?

As far as memory cells go (SRAM/ROM/Registers) in simple chips everything i've looked at seems to use the Two-Inverter CMOS schematic (Just from readings/googling and such). In I guess "real life" ...
442 views

### Why we need clock pulse in sequential circuits?

I need to know why do we need clock pulse in sequential circuits but not in combinational circuits?
131 views

### What should be considered when sizing trace widths for digital logic signals?

For traces that carry a static DC current, it's pretty easy to calculate the minimum trace width based on the required ampacity of the trace. However, I'm not sure what should be considered when ...
212 views

### Do case statements inside a for loop work in verilog?

I am doing a code for radix-4 booth encoding for 8*8 multiplication. The logic is correct and there are no errors or warning. The output am getting is totally unrelated. i have posted the code below ...
425 views

### Circuit works on breadboard but not PCB

I have a fairly simple circuit that works perfectly on the breadboard, but I am having a lot of trouble transferring it to a PCB. I am seeing very strange behavior which lies outside of my current ...
122 views

### combinations of binary digits for decimal numbers

Four bits are required to represent the ten decimal digits, and since there are 2^4 combinations of four binary digits, six combinations are not used and the code is said to contain redundancy. The ...
188 views

### Why do some pins have ~ signs next to their numbers?

I was looking at my Arduino Uno and I noticed that symbol by digital pins 11, 10, 9, ...
414 views

### Finding the no. of decoders required in cascading

I am trying to solve the following question. How many 3 to 8 decoders with an enable input are needed to construct a 6 to 64 line decoder without using any other logic gate. I have a Digital ...
191 views

### Magnitude comparator implementation

I have stuck on implementing magnitude comparator for 2-bit numbers (three functions - greater, equal, less). It is pretty easy to implement it with AND and OR gates, but the point is the task is to ...
139 views

### Addition modulo 26 in Digital Logic

I have two 5-bit signals, each guaranteed to be carrying a value between 0 and 25. I would like to add them together and get another 5-bit value between 0 and 25, simply taking the ...
176 views

### What is the name of this coding algorithm

as a school assignment we were given simple graph of FSM and the task is to design digital circuit described by this graph. Everything is fine I just followed my notes. While encoding the states I ...
1k views

### Why do we clock Flip Flops?

I am trying to understand Flip Flops & Latches. I am reading from Digital Logic book by Morris Mano. One thing I am not able to understand is why do we clock flip-flops ? I understand why do we ...
264 views

### Can someone help check my solution for this timing diagram?

I've been working on some timing diagrams and I keep mixing up the behaviors for the different flip flops. EDIT: I think I have the logic correct. If someone could please let me know if I'm ...
46 views

### ADC xbee series 1 VS xbee series 2

Can someone confirm to me that the Xbee series 1 modules may have more ADC pins than Xbee series 2? I saw this also into XCTU, if I use an XB24 modem i can set six ADC (from D0 to D5); instead if I ...
255 views

### What IC should I use to make a binary clock?

I am wanting to make a binary clock. A lot of the schematics I've found are for Arduinos or Raspberry Pi. As much as I appreciate the use of minicontrollers, I don't want to do that for this ...
654 views

### Given a gated SR latch, How do I make it a set dominant gated SR latch?

Another weirdly worded question in my digital logic book. It doesn't specifically define set-dominant or reset-dominant - nor does it show how to use these in practice with drawing circuit diagrams. ...
184 views

### How can an SR Flip Flop be made using a D Flip Flop and other Gates?

An SR flip flop is a flip flop that has set and reset inputs like a gated SR latch. How can an SR Flip Flop be made from using a D Flip Flop and other logic gates? I've done several searches online ...
128 views

### Invalid inputs in a SR Latch & Enabled SR Latch

Lets consider a SR Latch built with NOR gates. The invalid inputs are S=1, R=1. With enabled latch [gated latch], the invalid inputs are same, S=1, R=1. Now, lets consider, NAND gates, in SR Latch, ...
2k views

### Displaying a 2-digit integer on two 7-segment display

I'm having trouble displaying a binary number into a display. I'm not sure of how to split a number in binary into its individual numbers. For example, if I want to display 25, I want to split this ...
108 views

### ADC PCF8591 - change range for measuring

I'm doing my first project on my Raspberry pi with analogue signals, using the PCF8591 ADC. I managed very easily to measure 0 - 5 V with the chip, connecting the Reference Voltage (VREF, pin 14) ...
76 views

### Next-State Tables

Could someone give me some tips on how to approach state tables? I'm working through my textbook for an upcoming exam and I'm stuck at this problem: 17) Design a circuit that has an input clk, ...
1k views

### Number of bits for tag, index, and block in a direct-mapped cache

Suppose you have a 64-byte cache on a system with 16-bit memory addresses. If the cache is direct-mapped and it has 10 bytes of tag overhead in total, how many bits are used for the tag, index, and ...
143 views

### Positive and negative logic gates

This is a really basic topic but it's getting me confused. The truth table for any gate remains the same for both positive and negative logic, right? like for a NOR gate the truth table would always ...
317 views

### Mismatch between RTL-level simulation and post-synthesis simulation using xilinx xst

I have written a verilog code and RTL simulation is working fine. After this I synthesized the design using XST tool in Xilinx ISE 13.2. The post-synthesis simulation is showing some unexpected ...
105 views

### How to block/allow an i2c data signal to pass on to another device

I have three devices which I'm working on and one of them needs to control i2c communication between the other two. Each of the devices is based on an AtMega or AtTiny chip. The Controller (based on ...
144 views

### Single FET Bus Switch schematic in EAGLE

I've added a SN74CBT1G384DBV into my schematic in Eagle (which I want to use to enable/disable a logic signal line). Once placed into the schematic there only appear to be connection points for VCC ...
279 views

### Difference between RTL and Behavioral verilog

Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
625 views

### When do truth tables use the “Don't-care” term?

In which situation can be used the Don't-care term? Suppose that I want to use 6 symbols: I need 3 bits, which in turn can generate 8 combinations. Since the last ...
708 views

### Help verify 8x8x8 LED cube circuit

I am a beginning hobbyist when it comes to electronics. I have read lots of theory but I only have a little bit of hands on experience. I would like to build an 8x8x8 LED cube and I came up with this ...
233 views

### Is there a way to create a 2 bit / 4bit memory element using Flip Flop?

I have come across Flip-Flop memory elements & it seems really cool, So far i have only did Set, Reset Using Flip Flop, I am eager to know that Is there a way to create a 2 bit / 4bit memory ...
530 views

### Why is S=1, R=1 state forbidden in RS flip flop?

I have come across the RS flip flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the unstable or the ...
86 views

### How to detect and identify multiple points of contact

I am looking for a way to detect & distinguish multiple points of contact from force or pressure. I have asked a related question at the URL listed below: How to encode a large number of digital ...
364 views

### How to read the datasheet of a Digital transistor?

Could anybody please help in understanding the parameters of Digital transistor from its datasheet. Basically i need two parameters which decide the Maximum voltage for off state(0 state) and minimum ...
154 views

### How to simplify the actual function using K-maps?

So I'm trying to learn how to use Karnaugh maps. I've found what are the rules of simplification and how to apply them but every tutorial or lesson I find uses some generic function like "Here's how ...
125 views

### Domino logic output latching?

I've developed a domino circuit which calculate a simple logic function. I would like to latch the output "sum" into registers for further use. At the moment the logic goes to 0 during precharge as ...
95 views

### Can someone explain how this truth table was filled in from a Mealy model?

I'm having a bit of trouble figuring out how the truth table was filled in. I understand how to draw the diagram from the first table and I understand the boolean expression given from the truth ...
182 views

### How to find the critical path delay of a big combinational block

I have a 54*54 multiplier, i want to find the critical path delay.how do i go about, should i clock the module in order to find the delay?
537 views

### How to understand the SR Latch

I can't wrap my head around how the SR Latch works. Seemingly, you plug an input line from R, and another from S, and you are supposed to get results in Q and Q′. However, both R and S require input ...
174 views

### What does non-combinational area represent in synopsys design compiler

I have designed a ripple adder using full adders. In order to find delay incurred to perform this addition I included a clock in each full adder module. In my main code I instantiated these modules to ...
102 views

### 74 Series Logic Power switching with Gnd? (74Hc86)

I'm trying to cut power to the chip to "disable" all outputs without needing to know the input values or changing them. What happens if I use a NPN transistor to let the GND pin float and pull it to ...
122 views

### How to encode a large number of digital input signals into a signal result

I would like to know how I can detect simultaneous pulses on several wires. Essentially I will have several wires that will serve as connection points when pressed upon. A simple visualtization of ...
229 views

### Has anyone transmitted data across a badly coupled transformer and recovered the data correctly

EDITED June 9th 2013 to give more detail (hopefully) I've recently set-up a data transmission system on a rotating machine. The data was collected and serialized from several ADCs connected to strain ...
1k views

### XOR gate; transistor level design [duplicate]

What would a transistor level design of an XOR gate look like?
237 views

### Is there a glitch / race condition at the output of this circuit?

The input rising and falling edges occur at time t = 0. The propagation delays of the respective gates are 3 and 4 ns, as shown. According to my analysis, the waveforms are as below: As I've ...
185 views

### Automating Filling of Humidifier - Logical OR Gate

I have an Ultrasonic Humidifier that I use to humidify my shop. I have to fill its 2-gallon tank daily which is becoming a nuisance. Rather than connecting it to a larger tank, I have opted to ...
175 views

### Maximum clock frequency for multi-cycle vs pipeline

Suppose you have latencies: IF: 10 ns ID: 11 ns EX: 12 ns MEM: 13 ns WB: 14 ns What is the maximum possible clock frequency for a pipeline with this design? I ...