FIFO (First In, First Out) is one way of managing a buffer for data

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Trying to understand FIFO in hardware context

Wikipedia defines the FIFO in electronics as under: FIFOs are commonly used in electronic circuits for buffering and flow control which is from hardware to software. In its hardware form, a ...
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What is Asynchronous 245 FIFO mode?

Going through FT2232 to ADC0820 ADC Demo document I came across the term "Asynchronous 245 FIFO mode". I know it has something to do with FTDI chip but can someone tell me what exactly is this and ...
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Averlogic fifo experience?

I've got an fpga board that utilizes an averlogic fifo -- AL460. This should be the easiest part in the world to use -- it's basically a huge dual ported fifo with two independent clocks. I was ...
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Serial input, parallel output…then result to a FIFO

I have to implement a sort of switch architecture. The inputs for the switch are some serial bits that I have to group in a vector of size 35 to feed a FIFO queue. The scheme is pretty much like ...
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Send data from FIFO memory module to USB

I have a FIFO module running at 24MHz, producing 1 byte per clock. Then it produces 24MB/s. I need to send this data to PC through USB or Ethernet. How can I achieve this? Doesn't exist some USB ...
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635 views

How can I buffer SPI?

I have a board with a device that outputs data over SPI (as slave device) and a microcontroller. The device signals that data is available (24 bits) by setting a certain pin low, around 8000 times ...
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Async FIFO master / slave

Consider an asynchronous FIFO interface (e.g. FT245, FT2232H or comparable). Since there is no clock, how do you decide who deserved to be called master? Or do you call it controller instead?
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FIFO wrfull asserted when FIFO is not full

I have an issue with Altera FIFOs. It seems that the full signal wrfull gets asserted even when the FIFO is not full. My FIFOs are of size 8. The SignalTap traces ...
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Taking output from FIFO implemented in verilog

I have a big design implemented in Verilog. The design has FIFO as shown in the image below. Due to some reason I have to add a new "Consumer" block shown. The issue is, this block needs all the ...
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Designing with AC'97 - why does it not have a (FIFO) buffer?

The AC'97 codec seems to dominate the world of digital audio I/O but, what is weird is that it has neither interrupts nor buffers so that it is difficult to interface with a controller, which has ...
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Does a 250MHz FIFO chip exist?

If I have 8-bit parallel data being clocked out of a chip at 250MHz, is there some way I can buffer it? I only need to store about 1kB. Preferably this would be a FIFO. Does such a fast FIFO exist at ...
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FIFO : doubt in process(clk)

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