FIFO (First In, First Out) is one way of managing a buffer for data

learn more… | top users | synonyms

0
votes
2answers
79 views

Difference between buffer and mailbox

Peripherals in Micro-controllers usually provide a way for us to send and receive data from it. Usually this are memory mapped registers. I have come across few terminologies. The most often used one ...
1
vote
2answers
110 views

Serial Communication Rx ISR logic design

If im not wrong, an ISR is supposed to do minimal processing when it receives a data serially(via UART). Im planning on implementing such a protocol for communication between 2 systems via uart. This ...
0
votes
1answer
26 views

Xilinx Coregen FIFO as ZeroDelay model

My VHDL design contains a FIFO generated by Coregen from Vivado 15.3. I try to debug the design with a ZeroDelay simulation. But the core is not Zerodelay and makes short changes (much shorter that a ...
0
votes
1answer
51 views

FIFO for spartan 3AN : no storage on board but ok in simulation

I made a FIFO using the Core Generator and I'm trying to implement a code that use it... 1) By putting the switch (T9) ON, I start transmitting some datas to my fifo (Here H-e-l-l-o for test) 2) By ...
1
vote
1answer
231 views

ERROR:NgdBuild:604 using FIFO in VHDL

I would like to use a FIFO in VHDL, I used coregen to make it but when I want to use it into my project, I get this error : ERROR:NgdBuild:604 - logical block 'U101' with type '...
0
votes
1answer
76 views

FIFO in VHDL : ERROR:HDLParsers:3324

I'm programming a Spartan 3AN using ISE and I would like to implement a simple code that uses a Fifo : When I push a button, a data is sent to the FIFO and when I push another button, the fifo is ...
0
votes
3answers
280 views

VGA controller using FIFO memory, discrete ICs and Arduino Uno/Mega?

I love the Arduino boards. They're super easy to use and give me access to fairly powerful microcontrollers for all of about $12. Unfortunately, 16MHz isn't quite fast enough to display more than ...
2
votes
2answers
109 views

FIFO-related data transmission problems between microcontroller and PC

I have a situation in which a microcontroller is to perform a large number of ADC conversions and format the results into commands (or data packages) and send these to a PC using the UART. In order to ...
1
vote
1answer
170 views

Different ways of using UART

What is the difference when you send/receive data via Linux serial device file like ttyS3 and when you directly read/write from/to UART FIFO buffers? What situation is more safe and better? How ...
1
vote
2answers
541 views

How can I capture VGA (640x480) frames with RGB565 format from OV7670+FIFO (AL422B)?

I made a platform with LPC1788 (Cortex M3) which had external 8MB NOR flash and external 32MB (16bit) SDRAM. I connected them a CF7670C-V3 (OV7670+AL422B (FIFO)) camera module and I capture QVGA,QQVGA ...
0
votes
2answers
404 views

ov7670 camera module [closed]

I really need some help to figure out whether the ov7670 camera module I bought is with or without FIFO. I bought it from a local market.Can someone please tell me how can I find out whether the ...
2
votes
1answer
291 views

Setup and hold time violation constraints for Xilinx Fifo generator

I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual. I am using the fifo generator version 9.2 (manual ) to generate a fifo. I would like to ...
0
votes
1answer
289 views

How to interface 1 MSPS ADC with processing module in FPGA?

I have DE1-SoC board which contains 1 MSPS ADC, I am trying to take samples from ADC and process them. ADC Controller clock is 20 MHz and data is available every 16 clock cycles. The module that takes ...
1
vote
1answer
199 views

FIFO in ethernet module

In Ethernet module , why do we need FIFO block before the mac layer ? Can we bypass it ? Thanx in advance
0
votes
2answers
139 views

What is the jitter of an asynchronous FIFO?

I have an asynchronous FIFO (in a Stratix V FPGA) with two asynchronous read and write clocks of the same frequency of 100 MHz. As I understand, asynchronous FIFOs have a two-register ...
1
vote
1answer
160 views

using the clock of FPGA in system generator

I have designed a circuit in system generator. I am using a FIFO at the output. I want to connect the we pin of FIFO to the clock of FPGA, but I do not know how should I do it in System Generator. In ...
1
vote
1answer
170 views

An error in using FIFO block in system generator

I have designed a circuit in System Generator. I want to put a FIFO at the output before out gateway as shown in the below picture When I run it I face to the following error I should connect ...
4
votes
3answers
3k views

Trying to understand FIFO in hardware context

Wikipedia defines the FIFO in electronics as under: FIFOs are commonly used in electronic circuits for buffering and flow control which is from hardware to software. In its hardware form, a ...
2
votes
0answers
161 views

Send data from FIFO memory module to USB

I have a FIFO module running at 24MHz, producing 1 byte per clock. Then it produces 24MB/s. I need to send this data to PC through USB or Ethernet. How can I achieve this? Doesn't exist some USB ...
5
votes
1answer
3k views

How can I buffer SPI?

I have a board with a device that outputs data over SPI (as slave device) and a microcontroller. The device signals that data is available (24 bits) by setting a certain pin low, around 8000 times ...
0
votes
2answers
403 views

Async FIFO master / slave

Consider an asynchronous FIFO interface (e.g. FT245, FT2232H or comparable). Since there is no clock, how do you decide who deserved to be called master? Or do you call it controller instead?
2
votes
2answers
938 views

FIFO wrfull asserted when FIFO is not full

I have an issue with Altera FIFOs. It seems that the full signal wrfull gets asserted even when the FIFO is not full. My FIFOs are of size 8. The SignalTap traces ...
1
vote
2answers
554 views

Taking output from FIFO implemented in verilog

I have a big design implemented in Verilog. The design has FIFO as shown in the image below. Due to some reason I have to add a new "Consumer" block shown. The issue is, this block needs all the ...
3
votes
3answers
522 views

Designing with AC'97 - why does it not have a (FIFO) buffer?

The AC'97 codec seems to dominate the world of digital audio I/O but, what is weird is that it has neither interrupts nor buffers so that it is difficult to interface with a controller, which has ...
4
votes
2answers
440 views

Does a 250MHz FIFO chip exist?

If I have 8-bit parallel data being clocked out of a chip at 250MHz, is there some way I can buffer it? I only need to store about 1kB. Preferably this would be a FIFO. Does such a fast FIFO exist at ...
0
votes
3answers
770 views

FIFO : doubt in process(clk)

...
-1
votes
2answers
10k views