a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

learn more… | top users | synonyms

1
vote
2answers
68 views

register with enable signal, problem of understanding simulation results

I simulated a 32-bit register with an enable input in Vivado. The following things are unclear to me: I don't understand why 0xFFFFFFFF is latched at 5 ns and not the previous value 0x0abcdeff. ...
0
votes
1answer
33 views

Delays of logical flip-flops

I have two flips flops as so. The clocks are connected, even though it is not shown in the picture. Given this image, I am trying to figure whether the contamination delay or the propagation delay of ...
0
votes
1answer
46 views

Asynchronous JK Flip-Flop in VHDL

and thanks for your help. I wrote the code for an Asynchronous JK Flip Flop in VHDL, the code is the following: ...
2
votes
2answers
40 views

Metastability error propagation with flip flop

I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain ...
-4
votes
0answers
30 views

Flip Flop project R - S both 1 ??

I have a project which requires to show 1-3-5-7-9-0-8-6-4-2 in order with 7 seg display.I can use any type flipflops.We did a prototype : In program, it's working but I have doubts(in U2:A,R and S ...
0
votes
1answer
35 views

Design 5 bit counter with two control inputs (direction and stop)

I am designing a 5-bit counter with two control inputs including direction (up/down) D and stop S. Here is how counter works: DS = 00: down (or decrease) DS = 01: don't care DS = 10: stop DS = ...
0
votes
1answer
50 views

What will the output of filp-flop if its input is metastable?

I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt. Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. ...
0
votes
1answer
25 views

SR latch and level sensitive SR latch

So what is the difference between sr latch and level sensitive sr latch?? For sr latch, When 00, they just store the previous bit and when they are 01, the output q becomes 0, which they reset and ...
0
votes
0answers
60 views

On-off switch from PC's serial port

I am trying to make a circuit that can increase the number of loads I can turn on and off using a PC's serial port, since they are limited i thought of using a logic circuit based on th binary to do ...
0
votes
0answers
25 views

Synchronous mod 9 down counter

I'm having difficulties symulating counter mentioned above; to be specific, I don't know how to make it start at 1000 value - I know I should use ie. AND gate to check if most significant byte is high ...
-4
votes
0answers
22 views

A pulse triggered bistable switch circuit

I'm designing an IC but need a simple circuit to turn ON/OFF by a pulse and stay in its state until another pulse comes to switch it to the other state, I found several things like those on the ...
2
votes
1answer
19 views

Updating of a memory cell / synchronization with a clock

I'm wondering how computers actually work on a gate-level. I can see how a storage mechanism could be built from logic gates (e.g. SR NOR latch). What I'm wondering: how do values in memory cells get ...
0
votes
2answers
37 views

Source synchronous vs Common clock methodology in Physical design

I understand common clock and source synchronous clock. From this link http://referencedesigner.com/books/si/common-vs-source-sync.php. What i do not understand 1) How is maximum frequency attained ...
0
votes
1answer
48 views

Confusion about S-R and J-K FF

I've designed S-R and J-K Flip Flops, their truth tables as I searched on the web, examined all of results on it and wrote as in the picture. Because of designing alternatives, I am confused and not ...
1
vote
2answers
66 views

LTSpice D flip-flop not working

I'm an absolute beginner with LTSpice; my first test circuit uses a few D flip-flops: four of them as clock dividers (to divide the clock frequency by 16), and then 3 as delay blocks (to delay the ...
0
votes
2answers
41 views

Soft Toggle Circuit with T-Flip Flop not working

I'm trying to design an electronically toggled switch(one single switch turning an LED on and off) using a T-Flip Flop(a 74HC73, to be precise). I believe I've connected all the inputs and outputs ...
0
votes
0answers
33 views

Stick Diagram for D Flip Flop

I am new to Cadence and I am trying to design a D Flip Flop with asynchronous reset. However, I am having trouble with drawing the Stick Diagram from Euler's trail. My flip flop is designed this ...
0
votes
2answers
69 views

SR Flip-flop with 2 npn transistors - initial state

I built a SR flip-flop circuit according to this schematic with two NPN transistors: I read that the initial state of such a flip-flop is undefined. I observed that in my test circuit it's always ...
0
votes
0answers
22 views

0's and 1's catching in JK master-slave flip-flop

I'm learning about flip-flops from Givone's Digital Principles and Design and I've encountered a section on 0's and 1's catching in JK master-slave flip-flops which is described as: "If the slave ...
0
votes
1answer
38 views

What does grey dots represent in Proteus and why I am getting those

I am using a 5 by 32 decoder to implement a certain sequential circuit. However I am getting strange results. Here is the Snapshot: I don't understand why doesn't the decoder change its output when ...
-3
votes
1answer
46 views

How to flash different patterns of LED with Flip Flops [closed]

I need to blink same LED's in different patterns using flip flops. I have figured out the logic of individual patterns but I don't see a way to map them with inputs in order to differentiate the ...
0
votes
1answer
50 views

Use of D flip-flop in Serial Adder

In the circuit of a serial adder (below), what exactly is the function of the D flip-flop? Since its characteristic equation is \$Q^+ = D\$, couldn't it be simply removed (replaced with the wire) ...
0
votes
2answers
76 views

D Flip-Flop as pulse detector

Background For a while now I've been trying to come up with a simple module to handle modulated light detection for part of a laser trip sensor. Initial attempts I wanted to use a dual op-amp as an ...
1
vote
1answer
61 views

Asynchronous Down Counter using D Flip Flops

After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops. Here's the D Flip Flop code (which was tested and works): ...
0
votes
0answers
7 views

Combinational textability equations of inverted D flip flop?

These are the equations of Clock - Reset D flip flop, for Q output: ...
0
votes
1answer
49 views

Difference between D-Type Flip-Flop and Edge-Triggered D-Type Flip-Flop

I need to create a JK Flip-Flop using a D Flip-Flop, a 2-to-1 line MUX and an inverter. I wasn't really familiar with latches and Flip-Flops, but I understand the difference and how Flip-Flops are ...
0
votes
1answer
61 views

D flip flop in verilog

When i tried to code the below flip flop, the program failed. I'm using altera . ...
0
votes
0answers
12 views

Hold Conditions with CLK skew

simulate this circuit – Schematic created using CircuitLab I cant understand why the equation for the tHold from Reg1-> Reg2 is: tskew + Thold = tcd(reg1) + tcd((AND1)) Why we added the ...
1
vote
1answer
71 views

Is my understanding of D-Flip Flop wrong?

So I am working on: http://www.nand2tetris.org/ and I am having a hard time understanding the D-Flip Flop, or maybe I should say, how Logism represents it. I have this circuit and this is the current ...
0
votes
1answer
76 views

maximum clock frequency for a sequential circuit

This is the all question. I thought that because Tcq>Th we will only count Tcq. If we need to know the minimum clock period, we should calculate the duration from the beginning to the output of ...
2
votes
1answer
38 views

Trying to optimize simple PLL phase discriminator - Isn't there an off-the-shelf equivalent?

What I'm after is the "number 3" phase discriminator from the venerable 4046 PLL. That is, an edge-detected SR latch, effectively. A rising edge on input 1 makes the output go high. A rising edge on ...
-1
votes
1answer
224 views

Minimum No. of JK FlipFlops needed to design a user defined counter

We want to design a synchronous counter that counts the sequence 0−1−0−2−0−3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is : My doubt: We can design ...
0
votes
2answers
224 views

8 bit counter from T Flip Flops

I'm trying to build an 8bit counter in Verilog. I specifically need to create a module that I instantiate 8 times. I have followed the diagram below (and assumed that I can just build on it to make it ...
0
votes
1answer
80 views

Quartus: Error (12004): Port z does not exist in primitive x of instance y

I cannot find any source for this error, any help much appreciated! Error: Error (12004): Port "a" does not exist in primitive "tff" of instance "t1" ...
1
vote
2answers
77 views

Floating value when connecting to IC input

I'm currently having a strange issue with what I think is a 'floating' signal. The setup: I have a bank of inputs (which are connected to a resistor and LED acting as a pull-down) connected to inputs ...
0
votes
1answer
20 views

Is decoder 2-4 a complete system?

Is decoder 2-4 a complete system? My opinion: You can create OR, AND with D0-D3(For example D3 = X * Y). but you can't create NOT, because you do not have zero. for example {Dec 2-4,0} IS a complete ...
0
votes
0answers
70 views

Asynchronous Down Counter Using D Flip Flops Simulation Not Working As Expected

I'm a bit new to this, but I just want to have some insight as to why my circuit simulation doesn't work as planned (I'm using Quartus 2, qsim). Here I have designed an asynchronous down counter ...
0
votes
1answer
62 views

Flip Flop D Sequence

I want to create a game like "pimball" using 4 leds to state the game. One exit to define if the game is still running. And 2 inputs that are switches. 1) To begin with, the first is to assemble 4 ...
0
votes
1answer
75 views

Number of logic gates for counter with each type of flip flop

I am designing two synchronous counters one mod 21 and the other one mod 30. Is there a way to know which kind of flip flop (D, SR, JK, T) will use the smallest number of logic gates? I know we can ...
1
vote
1answer
62 views

frequency divider for two output frequencies

I want to make a frequency divider from flip flops that can generate two frequencies. For example, if the input frequency is fin then the output frequencies will be fin/30 or fin/35 depending on the ...
0
votes
2answers
71 views

D type flip flop feedback

The D type flip flop needs feedback from its inverted Q output to divide frequency by two. Is there an intuitive explanation for this?
0
votes
1answer
70 views

frequency divider by 42 with 50% duty cycle

I want to design a clock divider by 42 from flip flops. Is there a way to do that while still gets 50% duty cycle?
0
votes
1answer
42 views

Are these flip flop conversions correct

Hi I am from computer science background and hence lack any solid foundation in electronics. I am trying to learn some flip flop conversions. Most of them are their online, however I did not found ...
1
vote
1answer
56 views

transition speed causing issue with jk flip flop

i'm using jk flip flop to latch on a state given by 2 switches to either stay ON or stay OFF, knowing that one of them could stuck on ON which is why i use one of them as the clock input for the 4027B ...
-1
votes
0answers
24 views

Counter with 4 flip flops jk synchronous from 3 to 13 [duplicate]

I have to create a counter with 4 flip flops jk synchronous. The counter shall count in this order: 3 to 13 and then to 3 to 13 and so on.. I have to use logisim simulator. Until now what i´ve ...
-5
votes
5answers
315 views

Counter with 4 flip flops jk synchronous from 3 to 13!

I have to create a counter with 4 flip flops jk synchronous. The counter shall count in this order: 3 to 13 and then to 3 to 13 and so on.. I have to use logisim simulator. Ok. So i think its ...
1
vote
1answer
39 views

multilevel storage elements

I've been experimenting with three-valued logic (yeah, I know) and have had quite a bit of success by using voltage comparators to implement the combinatorial logic. All 27 1-input gates and many ...
4
votes
1answer
92 views

Why is D Flip Flop Positive Edge Trigger instead of a Level Trigger

So i'm trying to understand this D type Positive Edge Flip Flop: simulate this circuit – Schematic created using CircuitLab I'm having problem understanding why it's a Positive Edge ...
0
votes
2answers
141 views

Beginner trying to understand flip flops

I'm trying to understand how JK and D flip flops work. I am generally very airy when it comes to these topics and was hoping someone could explain in layman's terms how these two circuits work. It is ...