a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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37 views

24 Hour Counter

I'm implementing a 24 hour clock using jk flip flops and for the tens in the hours section, the ones cycles twice (0-9 twice) before the tens sections begins to count (0-2). What would be the cause ...
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28 views

24 Hour Counter JK Flip Flop

I'm trying to implement a 24 hour clock circuit using JK Flip Flops. I've gotten the minute part but I am having trouble designing the hours part, specifically the ones section. If it should count ...
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1answer
38 views

Mealy machine to detect sequence of 2 inputs

I have the following assignment for a project at college and I have a few questions regarding it. You are to design a Mealy state diagram for a digital lock. Assume that two debounced push-buttons, A ...
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2answers
35 views

Building circuit for n-relays using flip flops, is this the best solution?

I'm trying to build a circuit for n relays, each relay should hold it's state (ie latched). My first Idea was to use decoders, but clearly this was a bad option, since the state of the relays won't ...
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0answers
27 views

Output pad has illegal load on a d flip flop [closed]

I keep getting an error that says: NgdBuild:809 - output pad net 'out0' has an illegal load: and I don't know why. Can someone help me?
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42 views

VHDL code of johnson counter [closed]

For every 11th clock pulse the output goes high , so design it using a johnson counter . Also write the VHDL code ?
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0answers
33 views

Implementing a sequential logic circuit [closed]

I'm interested in implementing such a project, the text sounds like this : A sequential logic circuit has one input line X and one output line Z. Implement a finite-state Moore machine for which ...
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1answer
74 views

How would you make a 3-bit binary adder that adds two instead of 1?

I am trying to make an asynchronous adder that holds three bits and adds two to the number. Can someone help? A Google search shows nothing and I'm having a hard time visualizing how to make the ...
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0answers
33 views

Kmap Implementation in Electronics Workbench

I'm working in Electronics Workbench and after simplifying two of the Kmaps, I got values : Jd=1 & Kd=1 How would I implement that in the circuit? I know it looks confusing at the moment.
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68 views

LFSR Using D Flip Flops

I am fairly new to the VHDL language and I will admit that I primarily use it for educational purposes. I have been attempting to design a data encryption circuit using D flip flops. Obviously, an ...
0
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1answer
36 views

Help designing a serial adder [closed]

I need to build a circuit that adds two n-bit 2's complement numbers. the two numbers have to be stored in shift registers. The circuit should start with the least significant bits of each number and ...
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1answer
42 views

FSM for predesignated process (How to draw the state diagram)

let me start by saying this involves some homework problems so if you could help guide me a bit I would greatly appreciate it. I have been working with finite state machines for a bit in my course ...
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40 views

Parallel-in, parallel-out, universal shift register

I am trying build circuit of parallel-in/parallel-out universal shift register. I have found circuit in the Internet. Here it is I have tried to do this using MicroCap , but it doesn't work as ...
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40 views

Continuous Wave with flip-flops

What I'm going for is imagine 6 LED outputs, every other one on. (Off first) What I need to have happen is after I toggle on the 1 input to 1, it sets off a chain reaction, like a wave, where every ...
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1answer
48 views

Truth Table for JK flip-flop circuit?

Given a JK flip-flop circuit (using a D flip flop with a 2 by 1 MUX) how can I derive a truth table from this circuit? D = JQ' + K'Q Note: This is NOT a homework question. I just simply want to ...
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1answer
41 views

Does the output of JK Flip Flop toggle continously?

As given in most of the texts and online resources, the JK flip-flop requires a clock signal with an edge detector circuit so that the flip flop will be sensitive to the inputs only when the clock ...
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0answers
62 views

flip flop transfer function

Can same one explain me, if possible, how to get the equation of the transfer function for flip flop like the one below and hence get a plot like this
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1answer
65 views

Can someone explain to me what the 1s catching problem is in the Master Slave Flip Flop?

I have read the explanation in my textbook but I feel that they are too complex and no matter how much I try to understand it I don't seem to get what the difference is when the 1s complement occurs. ...
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1answer
45 views

How to toggle a reset in a counter made up of JK flip flops

I have been playing around with a small circuit which at the moment consists only of a counter made up of 3 JK flip flops. Like so: What I want to add is a reset input pin that will set the 3 LEDs ...
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1answer
27 views

connected d flip flop, propagation time = hold time?

When we connect two d flip flops, the propagation time and hold time have to be the same? or the propagation time have to be bigger than the hold time? I'm really confused please help!!
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2answers
225 views

Toggle two different LEDs with one T Flip flop

Imagine we have one green LED, one blue LED, power supply and resistors and grounds. We also have a switch. Can we toggle between the two different LEDs when the switch is pushed? If the blue LED is ...
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1answer
58 views

Purpose of T flip-flop in this circuit (LED)

In this circuit I try to toggle a LED on and off when a switch is pressed. Given the nature of the T flip-flop, when the switch is triggered, it toggles the clock and since T=1 always, it ...
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1answer
59 views

T-flip-flop without using a clock [closed]

Is it possible to create a T flip-flop without using a clock? I really need one, but I can't use one with a clock because it requires a signal shortener.
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46 views

Relay is not isolating properly its sorrounding circuit blocks

It turns out I've been building up an elevator for a project (at College). In general terms, everything appeared to be correct, regardless that I hadn't simulated each part. I decided to begin with ...
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3answers
436 views

Where does the power supply go in an SR Latch?

I understand how an SR Latch works: is S is 1, it will set Q to 1. If R is 1 it will set Q to 0. If both S and R are 0, the value of Q should remain unchanged (right?). So the circuit has these ...
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1answer
98 views

What is reset, preset and clear in a counter circuit?

I know this is a basic question. But I want to know the use of Reset, Preset and Clear in a Counter circuit. How do I use them? An example would be appreciated.
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4answers
240 views

ICs Powering On With Random Values

I've been prototyping a circuit for a first year university engineering project and I've been running into some problems with one section of the circuit that has really stumped me. Basically the flip ...
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1answer
60 views

Microcontrollers [closed]

Is there any other way of interfacing a push button with a LED but not directly with the micro controller? I would like to operate the LED in both method(push button as well as micro controller ...
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2answers
299 views

Setup Time, Hold Time - What is the underlying principle for having them?

I'm learning about setup time and hold time of a FF connected to a bus. But the textbook fails to explain exactly why are those needed in an operation. Isn't a FF always powered on and attentive to ...
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1answer
43 views

Is a D Type Edge triggered Master Slave flip flop considered a 1bit memory cell?

So in class we talked about how a D-type edge triggered flip flop is considered a 1bit memory cell. I think this is the same for a D-type latch. My question is, since a D-type edge triggered master ...
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1answer
84 views

D flip flop simulation: which simulation output is right?

I have always wondered, what is the right solution to the D flip flop when the input changes right at the rising edge of the clock? I have found two solutions of these online but have no clue which is ...
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0answers
116 views

How to create JK flip flop in proteus 8

I want to create a JK flip flop in Proteus 8.0 ISIS simulation tool. This is what I tried, but the problem with this is that the outputs Q and Q' are always zero regardless of what I set J or K. ...
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1answer
61 views

3 State Shift Register with 2-to-1 multiplexers

For a homework assignment I need to Redesign the right-shift register circuit of Figure 12-10 using four D flip-flops with clock enable, four 2-to-1 MUXes, and a single OR gate. The figure ...
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1answer
48 views

Different Vcc and input voltage into flip flop

I am building an LED matrix using flip-flops. I will have 128 rows in the matrix, so I am using 16 octal flip-flops, where all inputs to are shared and come from a microcontroller, which uses 5V ...
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2answers
84 views

Signal-driven 3 output logic gate decoder or switch?

I need to build a simple logic gate circuit such that when a single input signal or switch goes low it alternately activates one of three outputs as high. That is, every time it goes low the currently ...
2
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1answer
74 views

Combinational logic delay is greater than clock period

Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the ...
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1answer
32 views

Initial state of SN74AUP2G80 dual FF

My understanding is that a basic FF will in general power-up into a meta-stable state that then resolves to either H or L (more or less quickly). My question is, does this apply to current ...
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2answers
580 views

What is the difference between registers, flip flops and latches?

I want the answer to the very basic level. I know what they mean individually, but what I am looking for is connection between them.
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0answers
51 views

Trouble analyzing this JK-Flip-Flop (negative edge triggered) timing diagram

Can someone check to see if this timing diagram for a negative-edge-triggered flip-flop looks correct? I see that as it's negative-edge triggered (bubble at clock input), and thus action occurs at ...
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54 views

what is the approach to design edge triggered d flip flop? [closed]

i know the circuit. I implement it using verilog and it giving result correct. like when we have to design any digital circuit we draw truth table. Optimize circuit using K-map and then implement. In ...
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2answers
60 views

Can we declare output as “inout” to design a flip flop in VHDL?

I want to design a JK flip flop in VHDL. In this output depends on previous state. One method to implement this condition is by declaring a state as a signal inside the architecture. Another method ...
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2answers
53 views

Expression and gate not gate output

The expression I came up with this circuit is A'B + A'CD + C, would the output change to AB' + AC'D' + C' since it is inverted? I'm assuming the D input compliments and cancels out? What would the ...
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4answers
715 views

In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, ...
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2answers
130 views

Setup and hold for positive edge flip flop cascaded with negative edge flip flop

I know the following for two positive edge triggered flip flops in cascade. ...
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3answers
147 views

Electron flow at the immediate start of this flip-flop circuit?

I am attaching the following image of a flip-flop circuit. I find myself constantly trying to visualise what is occurring at the exact moment the circuit is closed, and the current starts (electron ...
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1answer
113 views

How to design new flip flop using JK flip flop

I have an excitation table that called MN flip flop like below. Q Q' M N 0 0 0 X 0 1 1 X 1 0 X 0 1 1 X 1 I try to design a counter that count 0-7-2-3 in ...
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1answer
63 views

The proper way to store bits in JK flip flops [closed]

Currently I'm working on a contraption where when a button is pushed, it briefly creates a 4 bit binary sequence. I want to have this binary sequence, 0000 all the way up to 1111, stored properly in ...
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1answer
600 views

D flip flop using transmission gates

In this circuit when D=0 and Clk=0 the value passes from w-x-y-z and z= 1. So at z= not D So this path constitutes what is called setup time of the flip flop. But at the same time the value at D ...
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1answer
321 views

JK Flip Flop , Counter Sequence?

Three edge-triggered JK flip-flops in a synchronous circuit have the following input conditions. JA = QB KA = 1 JB = 'QA KB = 1 JC = QB KC = 1 Assume ...
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2answers
93 views

Timing Diagram question

Can anyone check my timing diagram for me? I have my exam tomorrow and just want to make sure I am understanding these correctly: Any feedback is appreciated. Thanks in advance