a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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Implementing a FSM using JK flip flops in VHDL

This is yet another semester project I'm stuck on. I need to implement a state machine starting from the following diagram: What I've managed to do so far is write this state table, although I'm ...
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23 views

drawing flipflop after statement table and kmap simplification

I try to make counter using flipflop. 15-0-1-2-8-7-5-13-6-9-15 synchronous counter using D flipflop Here is table: Kmap simplifications: After the steps, I don't know (what I do) how to draw ...
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179 views

Using just one output of a J-K flip-flop

If I am using a J-K flip-flop, but only need one of the outputs, what should I do with the other? Leave it disconnected, or tie it high/low (via a resistor?) Why?
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71 views

Designing a State Machine

Question: Design a state machine that would output the sequence 0 1 7 1 and then 1 7 1 1 7 1 and so on. A reset will make the machine go to the which outputs 0? What I've managed to do so far: Since ...
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54 views

Component selection - difference between 4027 and 4027N flip flops

I am building a simple circuit that will use a J-K flip flop to enable me to use a momentary switch as a toggle. The circuit diagram states that a 4027N should be used. My local supplier has a ...
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56 views

How to design, build and test synchronous sequential circuits using D-Flip Flops?

I want to design, build and test synchronous sequential circuits by using D-Flip Flops. I know how to analyze state diagrams but I don't now how to obtain a state diagram using just outputs. P.S. : ...
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27 views

SR Latch/Racing?

Following truth table resulted from the circuit below. SR(NOR) latch is used. I have tried several times to trace through the circuit to see how truth table values are produced but its not working. ...
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42 views

Saving the state of the LED on illuminated momentary button

I have three illuminated momentary buttons with a separate anode and cathode for the led. (source of image) I want a circuit that illuminates the LED of the button that was most recently ...
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19 views

ltspice with large transistor array takes long time to solve

I have been working on a project to create several of the same T Flip-Flops with different components in LTSpice. The first uses the built in dflop object from LTSpice and the xor. I then moved to ...
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78 views

Resetting a counter when it reaches 6, without logic gates

I have a 3 bit ripple counter (using t flip flops) and I want the counter to reset to one when it reaches 7 i.e. the counter counts from 1 to 6. My idea was that I could hook the three outputs from ...
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how to Make Mealy machine output synchronous?

I have seen in slide below (and of course with some thought ) that the output of a Mealy machine is not synchronous . (you can find the whole slide in here). to make it synchronous the slide note ...
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56 views

JK Flip Flop Circuit Output

I have a group project that requires us to use three flip flops with the following requirements. If x = 0 and y = 0, the counter remains the same. If x = 0 and y = 1, the circuit through the state ...
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73 views

Who triggers transistors to become H/L?

Admittedly that's quite a beginner question: When I learned that transistors work like relays and produce the digital values 0 and 1 what I always asked myself was: they have to be triggered by ...
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67 views

How to design a Design a 64 x 8 memory using two 16 x 4 RAM chip? [closed]

Can someone suggest how I would start this project? I want to design a Design a 32 x 4 memory using two 16 x 4 RAM chip.
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59 views

VHDL JK Flip-Flop with logic gates

I am trying to make a JK flip-flop in ActiveHDL environment. I want to make it with logic gates. It should look like this: This is my code: ...
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42 views

How can the flip flop neglect clear when given output is given as feedback?

Here is how the circuet looks. Initally the output the D flip flop is HIGH, when the there is HIGH to LOW input across the multivirator, it create a pulse of 200ms, which is connected to the Clear ...
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28 views

What does splitter do in logisim?

I have just started learning logisim, so i have a very simple question. My question is what does splitter do. Whats its function and how can we actually implement it(like on breadboard or trainer ...
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199 views

How to create a frequency doubler circuit using only flipflops/ Digital elements?

First things first, is it even possible to scale up the frequency using only digital elements, atleast approximately? Though a frequency divider circuit can be designed very easily with flipflops. In ...
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92 views

JK Flip Flop Counter

I am designing a counter circuit that will perform the following function: A sequential circuit with three flip-flips A, B and C and two inputs X and Y. If X=0 and Y=0, the counter remains in the ...
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42 views

Significance of negative setup and hold time

What do you mean by negative setup and hold time i.e what happens if hold time is negative or setup time is negative. Does -ve setup or hold have any advantage ?
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58 views

Rising edge pulse detector from logic gates

The circuits I describe are entirely made of 7400 series logic gates (7402, 7404 and 7408 ic). I'm trying to build a rising (positive) edge pulse detector using logic gates. The following circuit ...
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72 views

is flip flop a synchronous or an asynchronous sequential circuit?

i have read in my text book that : " A flip-flop is the simplest synchronous sequential circuit. " but it is not convincing at all since we cannot analyze or build a flip flop like a synchronous ...
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28 views

SR Flip-flop builded from 2 SR-Latch

I just study about flip-flop in my class and this is the picture from the slide my teacher used that explain the construction of SR Flip-flop However, I find something was wrong with this figure. ...
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41 views

Using a block diagram for the RS flipflop, add appropriate gates for a D-flipflop

I have been given the problem "Using a block diagram for the RS flipflop, add appropriate gates for a D-flipflop". Now, I can create the gate diagram for both RS flipflop and D flipflop ...
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148 views

**Solved** D Flip Flop Frequency Divider - Simulates but doesn't work on protoboard *Pics/Simulation Data Included*

I'm having a problem that is probably trivial, but I can't seem to make any progress. Just a disclaimer, I'm an analog EE and digital design isn't my strong suite. That being said, I'm trying to build ...
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55 views

How to convert this NOT/AND/OR counter to an all NAND counter?

Sequence: 000,010,111,001,100... Have to build it using a JK Flip Flop for Q0 and 2 D flip flops for Q1 and Q2 and all NAND gates. Basically I have no problem building this counter with just the ...
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501 views

SR Flip Flop: NOR or NAND?

I started studying flip flips recently and I am stuck at this point: At some video tutorials, people explain the SR Flip Flop like this: So they use NAND gates, producing a transition table like ...
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31 views

number of bits of information for n stable states?

my text book says "An element with N stable states conveys log2N bits of information" i don't understand it since i expect if we have n stable states we would have n/2 bits since one of them is ...
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79 views

Design serial adder for 16 bit register using on full FA

I wrote a serial bit adder for a 15 bit width shift register and a full adder (positive edge trigger, asynchronous reset) I don't know where the error in this code is. This is the code: ...
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75 views

Can I use an AND gate before a clock input?

Can I use an AND gate with a clock input? For example, in the picture below, I have a positive-edge D flip-flop. I'm using an AND gate with the Select_chip input and the Clock input but I'm not sure ...
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89 views

Constructing a Sequential Circuit with two D Flip Flops

A sequential circuit with two D flip flops (A and B), two inputs (x and y), and one output (z) is specified by the following next-state and output equations: A(t+1) = xy' + xB B(t+1) = xA + xB' z = ...
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1/6 Clock Frequency Divider

How would I design a circuit made of rising edge triggered flip flops and inverters to make its output 1/6 of the clock frequency. Cheers
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84 views

Quiz Buzzer circuit using IC 74LS373. Not resetting after cutting off supply

I am confronted with a buzzer circuit using a 74LS373 which is a 3 state octal D type transparent latch and edge triggered flip flop. This is my first ever attempt to use this type of IC. My search ...
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48 views

How could I set up a circuit that keeps track of strikes in a baseball game using D flip flops in Multisim?

What I want is two LED lights and a push button. When the push button is pressed the first time, the first light lights up. When it's pressed a second time, the second light lights up. When it's ...
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57 views

Why is it when I set up a Johnson counter, the number sequence rotates fine, but I can't get a ring counter right (explanation below)?

With a Johnson counter, I hook up every flip flop's Q output to the following flip flop's D input, for D flip flops. And then the final Q' output is hooked into the first flip flop's D input. When I ...
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73 views

Verilog inital value for flip flop

I am trying to write verilog code that will set the initial value of the output of a positive-edge triggered flip-flop to 0. The behaviour of the flip-flop circuit is exactly what I want AFTER the ...
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173 views

Reduced clock speed with flip flop

My question is if there is a way to reduce a clock to two thirds of its speed using flip flops because i know a flip flop cuts its speed in half.
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47 views

What would be the truth table for the following inputs with a positive edge triggered D flip flop?

This is what I got, but I'm guessing I did something wrong: ...
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36 views

How is this method of addressing memory scalable?

I've been watching Computerphile videos about memory. I'm currently watching this one In it he goes over using some logic gates to address flip flops. He explains that is is cumbersome to add a wire ...
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111 views

OP-AMP Flip Flop start up predictability

A customer had asked for a circuit design which I felt would be fun to implement using a couple of OP amps. (Its always fun to see if you can do something with op amps instead of a small MCU ). Anyway ...
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85 views

S-R latch / flip- flop question

First I want to ask, why are S and R inverted when comparing an S-R latch with NAND and NOR gate. It just seems odd to me that they're being inverted. Secondly, why is a multi-transition behaviour a ...
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40 views

JK flip-flop and sequence network

State diagram of the sequence network S looks like the following for a jk flip-flop: Is this the right truth table for it? ...
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161 views

Logisim: “Oscillation apparent”

I am trying to simulate an RS master slave flip-flop in Logisim, and I have encountered the "Oscillation apparent" error. What does this error mean and how is it resolved? I am required to use two nor ...
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124 views

Help me understand Mealy machine with D flip flops vs JK flip flops

So, the task is to implement a synchronous sequential circuit which detects the input sequence "1101" using D flip flops and standard logic gates (represent with Mealy machine with finite number of ...
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1k views

What is race around condition in flip-flops?

I've gone through two of my text books and consulted my teacher but nothing seems to clarify my doubts. The two versions of race-around which I've been taught are - When the S and R inputs of an ...
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113 views

D flip flop with asynchronous level triggered reset

Ref : Is making a D flip flop with asynchronous level triggered reset possible? My code : ...
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861 views

Clock divider circuit with flip D flip flop

I am using D flip flops in my clock divider circuit. I have started with one FF and moving up with the number of divisions I want to have in my clock. This is how I want my D ffs to work. Now I ...
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97 views

What is the inverted output for on a D flip flop?

I was asked to find the answer for this, it is a pretty vague question: On a D Flip Flop, what is the Q' output? Look this up and write your answer in your pre-lab report. I am trying to understand ...
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132 views

A simple clarification on latches and flip-flops

Here are two representations of a gated SR latch (first one from my book and the second one from Wikipedia): The part I don't understand are the S and R inputs, why are they reversed in these two ...
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29 views

Modeling Rocker Switch with Block Xilinx System Generator

I am working on a project for the detection of QRS complex. I would make it with Xilinx system generator. I need to detect the thresholds at the output of the block and to detect from the TRIGGER ...