a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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A pulse triggered bistable switch circuit

I'm designing an IC but need a simple circuit to turn ON/OFF by a pulse and stay in its state until another pulse comes to switch it to the other state, I found several things like those on the ...
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1answer
18 views

Updating of a memory cell / synchronization with a clock

I'm wondering how computers actually work on a gate-level. I can see how a storage mechanism could be built from logic gates (e.g. SR NOR latch). What I'm wondering: how do values in memory cells get ...
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2answers
25 views

Source synchronous vs Common clock methodology in Physical design

I understand common clock and source synchronous clock. From this link http://referencedesigner.com/books/si/common-vs-source-sync.php. What i do not understand 1) How is maximum frequency attained ...
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1answer
44 views

Confusion about S-R and J-K FF

I've designed S-R and J-K Flip Flops, their truth tables as I searched on the web, examined all of results on it and wrote as in the picture. Because of designing alternatives, I am confused and not ...
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19 views

Asynchronous down modulo counter

I'm trying to design asynchronous down modulo 11 counter. I tried to use NAND gate to check if signal is 1011 on the output an then send reset to all flip-flops, but my counter was starting with 1111 ...
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2answers
49 views

LTSpice D flip-flop not working

I'm an absolute beginner with LTSpice; my first test circuit uses a few D flip-flops: four of them as clock dividers (to divide the clock frequency by 16), and then 3 as delay blocks (to delay the ...
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2answers
36 views

Soft Toggle Circuit with T-Flip Flop not working

I'm trying to design an electronically toggled switch(one single switch turning an LED on and off) using a T-Flip Flop(a 74HC73, to be precise). I believe I've connected all the inputs and outputs ...
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28 views

Stick Diagram for D Flip Flop

I am new to Cadence and I am trying to design a D Flip Flop with asynchronous reset. However, I am having trouble with drawing the Stick Diagram from Euler's trail. My flip flop is designed this ...
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2answers
57 views

SR Flip-flop with 2 npn transistors - initial state

I built a SR flip-flop circuit according to this schematic with two NPN transistors: I read that the initial state of such a flip-flop is undefined. I observed that in my test circuit it's always ...
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21 views

0's and 1's catching in JK master-slave flip-flop

I'm learning about flip-flops from Givone's Digital Principles and Design and I've encountered a section on 0's and 1's catching in JK master-slave flip-flops which is described as: "If the slave ...
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1answer
22 views

What does grey dots represent in Proteus and why I am getting those

I am using a 5 by 32 decoder to implement a certain sequential circuit. However I am getting strange results. Here is the Snapshot: I don't understand why doesn't the decoder change its output when ...
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1answer
42 views

How to flash different patterns of LED with Flip Flops [closed]

I need to blink same LED's in different patterns using flip flops. I have figured out the logic of individual patterns but I don't see a way to map them with inputs in order to differentiate the ...
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1answer
37 views

Use of D flip-flop in Serial Adder

In the circuit of a serial adder (below), what exactly is the function of the D flip-flop? Since its characteristic equation is \$Q^+ = D\$, couldn't it be simply removed (replaced with the wire) ...
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2answers
72 views

D Flip-Flop as pulse detector

Background For a while now I've been trying to come up with a simple module to handle modulated light detection for part of a laser trip sensor. Initial attempts I wanted to use a dual op-amp as an ...
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22 views

Construct flip-flop timing diagram given frequencies

I am to draw the first 200 ms a JK flip flop with a 50 Hz clock with an input signal J toggles frequency of 10 Hz and K toggles with frequency of 25 Hz. I am trying to understand how to use the ...
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1answer
57 views

Asynchronous Down Counter using D Flip Flops

After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops. Here's the D Flip Flop code (which was tested and works): ...
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61 views

Asynchronous 4-bit Up Counter using D Flip Flops

I'm trying to write structural verilog code for an Asynchronous 4-bit Up Counter using D Flip Flops. Here is my D Flip Flop Code made from this image: ...
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7 views

Combinational textability equations of inverted D flip flop?

These are the equations of Clock - Reset D flip flop, for Q output: ...
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1answer
35 views

Difference between D-Type Flip-Flop and Edge-Triggered D-Type Flip-Flop

I need to create a JK Flip-Flop using a D Flip-Flop, a 2-to-1 line MUX and an inverter. I wasn't really familiar with latches and Flip-Flops, but I understand the difference and how Flip-Flops are ...
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1answer
58 views

D flip flop in verilog

When i tried to code the below flip flop, the program failed. I'm using altera . ...
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11 views

Hold Conditions with CLK skew

simulate this circuit – Schematic created using CircuitLab I cant understand why the equation for the tHold from Reg1-> Reg2 is: tskew + Thold = tcd(reg1) + tcd((AND1)) Why we added the ...
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1answer
68 views

Is my understanding of D-Flip Flop wrong?

So I am working on: http://www.nand2tetris.org/ and I am having a hard time understanding the D-Flip Flop, or maybe I should say, how Logism represents it. I have this circuit and this is the current ...
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1answer
53 views

maximum clock frequency for a sequential circuit

This is the all question. I thought that because Tcq>Th we will only count Tcq. If we need to know the minimum clock period, we should calculate the duration from the beginning to the output of ...
2
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1answer
36 views

Trying to optimize simple PLL phase discriminator - Isn't there an off-the-shelf equivalent?

What I'm after is the "number 3" phase discriminator from the venerable 4046 PLL. That is, an edge-detected SR latch, effectively. A rising edge on input 1 makes the output go high. A rising edge on ...
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1answer
196 views

Minimum No. of JK FlipFlops needed to design a user defined counter

We want to design a synchronous counter that counts the sequence 0−1−0−2−0−3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is : My doubt: We can design ...
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2answers
157 views

8 bit counter from T Flip Flops

I'm trying to build an 8bit counter in Verilog. I specifically need to create a module that I instantiate 8 times. I have followed the diagram below (and assumed that I can just build on it to make it ...
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88 views

48-bit memory in flat/matrix organization

I have received an assignment for a computer systems course to design a 48 bit memory with 3-bit words, 16 words, 4 address bits in flat design and 2 in matrix design) with the use of D-flip flops. ...
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1answer
67 views

Quartus: Error (12004): Port z does not exist in primitive x of instance y

I cannot find any source for this error, any help much appreciated! Error: Error (12004): Port "a" does not exist in primitive "tff" of instance "t1" ...
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2answers
71 views

Floating value when connecting to IC input

I'm currently having a strange issue with what I think is a 'floating' signal. The setup: I have a bank of inputs (which are connected to a resistor and LED acting as a pull-down) connected to inputs ...
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1answer
19 views

Is decoder 2-4 a complete system?

Is decoder 2-4 a complete system? My opinion: You can create OR, AND with D0-D3(For example D3 = X * Y). but you can't create NOT, because you do not have zero. for example {Dec 2-4,0} IS a complete ...
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67 views

T Flip Flop Verilog

I don't quite understand flip flops that well so I just wanted to see if this verilog code I wrote makes sense and if the outputs are what are expected from a T Flip Flop verilog code: ...
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60 views

Asynchronous Down Counter Using D Flip Flops Simulation Not Working As Expected

I'm a bit new to this, but I just want to have some insight as to why my circuit simulation doesn't work as planned (I'm using Quartus 2, qsim). Here I have designed an asynchronous down counter ...
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1answer
60 views

Flip Flop D Sequence

I want to create a game like "pimball" using 4 leds to state the game. One exit to define if the game is still running. And 2 inputs that are switches. 1) To begin with, the first is to assemble 4 ...
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1answer
69 views

Number of logic gates for counter with each type of flip flop

I am designing two synchronous counters one mod 21 and the other one mod 30. Is there a way to know which kind of flip flop (D, SR, JK, T) will use the smallest number of logic gates? I know we can ...
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1answer
62 views

frequency divider for two output frequencies

I want to make a frequency divider from flip flops that can generate two frequencies. For example, if the input frequency is fin then the output frequencies will be fin/30 or fin/35 depending on the ...
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2answers
64 views

D type flip flop feedback

The D type flip flop needs feedback from its inverted Q output to divide frequency by two. Is there an intuitive explanation for this?
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68 views

frequency divider by 42 with 50% duty cycle

I want to design a clock divider by 42 from flip flops. Is there a way to do that while still gets 50% duty cycle?
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1answer
42 views

Are these flip flop conversions correct

Hi I am from computer science background and hence lack any solid foundation in electronics. I am trying to learn some flip flop conversions. Most of them are their online, however I did not found ...
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1answer
53 views

transition speed causing issue with jk flip flop

i'm using jk flip flop to latch on a state given by 2 switches to either stay ON or stay OFF, knowing that one of them could stuck on ON which is why i use one of them as the clock input for the 4027B ...
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24 views

Counter with 4 flip flops jk synchronous from 3 to 13 [duplicate]

I have to create a counter with 4 flip flops jk synchronous. The counter shall count in this order: 3 to 13 and then to 3 to 13 and so on.. I have to use logisim simulator. Until now what i´ve ...
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5answers
274 views

Counter with 4 flip flops jk synchronous from 3 to 13!

I have to create a counter with 4 flip flops jk synchronous. The counter shall count in this order: 3 to 13 and then to 3 to 13 and so on.. I have to use logisim simulator. Ok. So i think its ...
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1answer
39 views

multilevel storage elements

I've been experimenting with three-valued logic (yeah, I know) and have had quite a bit of success by using voltage comparators to implement the combinatorial logic. All 27 1-input gates and many ...
4
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1answer
84 views

Why is D Flip Flop Positive Edge Trigger instead of a Level Trigger

So i'm trying to understand this D type Positive Edge Flip Flop: simulate this circuit – Schematic created using CircuitLab I'm having problem understanding why it's a Positive Edge ...
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2answers
121 views

Beginner trying to understand flip flops

I'm trying to understand how JK and D flip flops work. I am generally very airy when it comes to these topics and was hoping someone could explain in layman's terms how these two circuits work. It is ...
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2answers
84 views

Why is this a Moore and not a Mealy FSM?

Can someone please explain how I can tell which FSM type I have? In my textbook I read that output in a Mealy FSM is based on both the input and the present state, but in a Moore FSM it is based only ...
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1answer
441 views

Modulo 10 Counter using T flip flops?

so I have been tasked with making a counter that counts from 0-9 continuously and pauses when the input is 0. Of course this has to be done with T flip flops, but for the life of me I cannot figure ...
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3answers
38 views

Is there a latch / flip-flop with this behaviour?

I've looked at the most popular flip-flop types, and none of them seem to have this desired behaviour: It would have two inputs: A set signal, S, and a data signal, D. If the set signal is true, it ...
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48 views

Algorithmic State Machine using D flip Flops - how to deal with don't care conditions

I have the following state transition table: where, A, B - current states of two D flip flops A+, B+ - next states of the two D flip flops X1, X2, X3 - inputs to the current states There are ...
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52 views

How to terminate binary counting using a logic gate

So I am designing a 3-bit asynchronous binary counter which counts up to 11 then repeats using D flip-flops. That much I have done, however I am stuck when it comes to decoding the outputs to stop the ...