a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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In digital electronics, when does clock transition happen, say from 0 to 1, or 1 to 0?

I am a student learning flip-flops on digital electronics. Here is my question: While using 2 or more flip flops, in +/- edge triggering / level triggering, when does the clock change its state. Is ...
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40 views

Why does this dual monstable not function as such?

I have wired up a simple circuit here to test the cmos one-shot multivibrator. The top half of the chip seems to work but the bottom half does not. I even replaced the chip with a new one and I get ...
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1answer
38 views

Does a signal need to be in a clocked process to be registered (VHDL)?

I understand that it is best practice to register the outputs of all modules; so, I want to do that. However, I'm unsure what exactly it means to register an output signal. I.e. Do I have to include ...
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57 views

Violating the minimum clock pulse width of a D-type flip flop

Any D-type flip flop has a specification for a minimum clock pulse width. For example, the 74LVC374 has a typical time of 1.5ns for Vcc=3V. But what can happen to the flip flop if a shorter pulse is ...
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54 views

Dual edge triggered D flip flip CMOS implementation. Less than 20 transistor

I need to implement a dual edge triggered D flip flop (DET) in a CMOS IC using 0.35u technology. The best design which I could fine is this one http://ieeexplore.ieee.org/xpl/login.jsp?tp=&...
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18 views

SR Latch settles on equilibrium state with lower voltage supply

I need to use SR latch for my design and it was working fine. Until I started it with lower voltages. CON8 and O4 are the inputs. CON9 is the output. When I use 15V supply, it works very fine: ...
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46 views

What does the diode in this D flip-flop “One-shot” do?

Does this diode help discharge the capacitor once the flip-flop is reset? Thanks in advanced. (Image was taken from http://educypedia.karadimov.info/library/oneshots.pdf)
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48 views

Connect combinantional block to JK Flip Flop

How can i connect combinantional block to JK flip flop in scheme like this: Function i want implement is 3rd column from first image. That is truth table but i think it's wrong how i get values for ...
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1answer
51 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
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37 views
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104 views

How to drive 315 coills in flip-disc display

Recently I've bought 9 surplus electromagnetic flip-disc displays on Ebay. Each display has 5x7 dot matrix. Every dot is controlled by separate pin. See below: As far as I understand to flip one ...
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68 views

Question regarding 74HC574 (question very difficult to word)

Basically, I have a question regarding the timing of the 74HC574 octal latch. According to the timing diagram, the data pins must be set for so many nanoseconds before the latch pin (rising edge ...
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1answer
34 views

What does this sentence mean in this question (simulator can handle X inputs)?

In my book, one question requires me to find the verification sequence for a circuit. From what I understand, verification sequence must be such that every path is traversed. Then the book ...
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21 views

How do I draw the k-map in case of one-hot encoding state assignment?

In one hot encoding, I have to assign bits according to the number of states. But I'm unable to figure out how to draw the kmap for such a thing. The exact question I'm solving is this one: There ...
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1answer
63 views

Transistor level design of flip flops - Is the complementary clock necessary?

Below is one of many different ways to design a Master Slave D Flip Flop. simulate this circuit – Schematic created using CircuitLab Of course a lot of details are glossed over, ...
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40 views

Single touch On/Off auto off after 30 minutes

I've been looking for a circuit to turn on a strip of LEDS (12volts 5amps) with a momentary capacitive touch breakout board . I'm looking to have the lights stay on for 30 minutes or use the touch ...
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1answer
49 views

difference between circuits

I have 2 circuits as seen below. However, I am unsure of the difference(s) between these 2 circuits. Is anyone able to help me along? Thanks in advance!
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58 views

555 timer bistable circuit problem: default flip-flop state is 'ON' on power reset

The following circuit is a controller for a water pump. It turns the pump on when the reservoir water level drops below the 'L' probe and turns it off when the level reaches the 'H' probe. This ...
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178 views

register with enable signal, problem of understanding simulation results

I simulated a 32-bit register with an enable input in Vivado. The following things are unclear to me: I don't understand why 0xFFFFFFFF is latched at 5 ns and not the previous value 0x0abcdeff. ...
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1answer
40 views

Delays of logical flip-flops

I have two flips flops as so. The clocks are connected, even though it is not shown in the picture. Given this image, I am trying to figure whether the contamination delay or the propagation delay of ...
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1answer
65 views

Asynchronous JK Flip-Flop in VHDL

and thanks for your help. I wrote the code for an Asynchronous JK Flip Flop in VHDL, the code is the following: ...
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2answers
55 views

Metastability error propagation with flip flop

I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain ...
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1answer
45 views

Design 5 bit counter with two control inputs (direction and stop)

I am designing a 5-bit counter with two control inputs including direction (up/down) D and stop S. Here is how counter works: DS = 00: down (or decrease) DS = 01: don't care DS = 10: stop DS = ...
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1answer
57 views

What will the output of filp-flop if its input is metastable?

I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt. Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. ...
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1answer
29 views

SR latch and level sensitive SR latch

So what is the difference between sr latch and level sensitive sr latch?? For sr latch, When 00, they just store the previous bit and when they are 01, the output q becomes 0, which they reset and ...
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68 views

On-off switch from PC's serial port

I am trying to make a circuit that can increase the number of loads I can turn on and off using a PC's serial port, since they are limited i thought of using a logic circuit based on th binary to do ...
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35 views

Synchronous mod 9 down counter

I'm having difficulties symulating counter mentioned above; to be specific, I don't know how to make it start at 1000 value - I know I should use ie. AND gate to check if most significant byte is high ...
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1answer
19 views

Updating of a memory cell / synchronization with a clock

I'm wondering how computers actually work on a gate-level. I can see how a storage mechanism could be built from logic gates (e.g. SR NOR latch). What I'm wondering: how do values in memory cells get ...
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56 views

Source synchronous vs Common clock methodology in Physical design

I understand common clock and source synchronous clock. From this link http://referencedesigner.com/books/si/common-vs-source-sync.php. What i do not understand 1) How is maximum frequency attained ...
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1answer
50 views

Confusion about S-R and J-K FF

I've designed S-R and J-K Flip Flops, their truth tables as I searched on the web, examined all of results on it and wrote as in the picture. Because of designing alternatives, I am confused and not ...
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183 views

LTSpice D flip-flop not working

I'm an absolute beginner with LTSpice; my first test circuit uses a few D flip-flops: four of them as clock dividers (to divide the clock frequency by 16), and then 3 as delay blocks (to delay the f/...
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2answers
50 views

Soft Toggle Circuit with T-Flip Flop not working

I'm trying to design an electronically toggled switch(one single switch turning an LED on and off) using a T-Flip Flop(a 74HC73, to be precise). I believe I've connected all the inputs and outputs ...
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37 views

Stick Diagram for D Flip Flop

I am new to Cadence and I am trying to design a D Flip Flop with asynchronous reset. However, I am having trouble with drawing the Stick Diagram from Euler's trail. My flip flop is designed this ...
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98 views

SR Flip-flop with 2 npn transistors - initial state

I built a SR flip-flop circuit according to this schematic with two NPN transistors: I read that the initial state of such a flip-flop is undefined. I observed that in my test circuit it's always ...
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1answer
63 views

What does grey dots represent in Proteus and why I am getting those

I am using a 5 by 32 decoder to implement a certain sequential circuit. However I am getting strange results. Here is the Snapshot: I don't understand why doesn't the decoder change its output when ...
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1answer
51 views

How to flash different patterns of LED with Flip Flops [closed]

I need to blink same LED's in different patterns using flip flops. I have figured out the logic of individual patterns but I don't see a way to map them with inputs in order to differentiate the ...
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1answer
76 views

Use of D flip-flop in Serial Adder

In the circuit of a serial adder (below), what exactly is the function of the D flip-flop? Since its characteristic equation is \$Q^+ = D\$, couldn't it be simply removed (replaced with the wire) ...
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80 views

D Flip-Flop as pulse detector

Background For a while now I've been trying to come up with a simple module to handle modulated light detection for part of a laser trip sensor. Initial attempts I wanted to use a dual op-amp as an ...
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1answer
84 views

Asynchronous Down Counter using D Flip Flops

After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops. Here's the D Flip Flop code (which was tested and works): <...
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1answer
70 views

Difference between D-Type Flip-Flop and Edge-Triggered D-Type Flip-Flop

I need to create a JK Flip-Flop using a D Flip-Flop, a 2-to-1 line MUX and an inverter. I wasn't really familiar with latches and Flip-Flops, but I understand the difference and how Flip-Flops are ...
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1answer
67 views

D flip flop in verilog

When i tried to code the below flip flop, the program failed. I'm using altera . ...
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77 views

Is my understanding of D-Flip Flop wrong?

So I am working on: http://www.nand2tetris.org/ and I am having a hard time understanding the D-Flip Flop, or maybe I should say, how Logism represents it. I have this circuit and this is the current ...
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1answer
88 views

maximum clock frequency for a sequential circuit

This is the all question. I thought that because Tcq>Th we will only count Tcq. If we need to know the minimum clock period, we should calculate the duration from the beginning to the output of ...
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1answer
39 views

Trying to optimize simple PLL phase discriminator - Isn't there an off-the-shelf equivalent?

What I'm after is the "number 3" phase discriminator from the venerable 4046 PLL. That is, an edge-detected SR latch, effectively. A rising edge on input 1 makes the output go high. A rising edge on ...
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295 views

Minimum No. of JK FlipFlops needed to design a user defined counter

We want to design a synchronous counter that counts the sequence 0−1−0−2−0−3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is : My doubt: We can design ...
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2answers
391 views

8 bit counter from T Flip Flops

I'm trying to build an 8bit counter in Verilog. I specifically need to create a module that I instantiate 8 times. I have followed the diagram below (and assumed that I can just build on it to make it ...
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1answer
93 views

Quartus: Error (12004): Port z does not exist in primitive x of instance y

I cannot find any source for this error, any help much appreciated! Error: Error (12004): Port "a" does not exist in primitive "tff" of instance "t1" ...
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83 views

Floating value when connecting to IC input

I'm currently having a strange issue with what I think is a 'floating' signal. The setup: I have a bank of inputs (which are connected to a resistor and LED acting as a pull-down) connected to inputs ...
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1answer
23 views

Is decoder 2-4 a complete system?

Is decoder 2-4 a complete system? My opinion: You can create OR, AND with D0-D3(For example D3 = X * Y). but you can't create NOT, because you do not have zero. for example {Dec 2-4,0} IS a complete ...