a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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D flip flop - “no change” state [closed]

For a D flip-flop, I know the types are set, reset, and no change. I can identify which is which, but my professor said just because Q does not change does not mean the action type was no change, and ...
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Cross-coupled logic gates and timing

I had a hard time getting a right title for this question since I'm a software guy trying to get the basics of my hardware down. Since all computers basically start with logic gates and go from there ...
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1answer
35 views

Eliminating Signal Race Hazard in an IC dynamic latch/register!

I work in MAGIC Integrated Circuit software at layout-level. I got an 8bit dynamic register made of 1bit dynamic flipflops that write input on the positive edge of the signal: (Note: I used ...
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78 views

Can we reduced the below circuit by one gate?

The below circuit is simple clocked D flip flop. Currently it uses 5 nand gate .Can we further reduce it?
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63 views

Integrated Circuit Layout Design - Dynamic Flip Flop?

I need to create a dynamic flip flop like this: In integrated circuit technology, at mask layout level. I then want to create an 8bit register, using 8 of these flip flops, with a common CLK ...
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1answer
31 views

Design 2 JK Flip Flops without Switch Input to K

I have a lab for my Intro to Hardware Course due today. We use TTL. (True= 5v, False= 0v) ...
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480 views

why in some circuit there is use of bubble followed by bar?

It is a circuit of ring counter. The clock here is negative triggered. but for set and clear it use bubble with bar.What is the need of bubble followed by bar. why it can not use a PRE and CLR ...
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109 views

How to design a left shift register

I want a circuit in which I get the following sequence: 0001, 0010, 0100, 1000, 0001 I know that it's 4-bit shift register. But what is my approach to design ...
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3answers
95 views

Why does my book's D flip flop differ from others?

My understanding of a D flip flop is that when the clock is high and D=1, it sets Q to 1. If D=0, Q is set to 0. So it is like a set to 1 if D=1 and reset to 0 otherwise. The table repeatedly given ...
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38 views

Need for edge triggered versions other than master slave

I am studying synchronous digital circuits and I have come to the conclusion that master slave flip flops are edge triggered? Is my study correct? If master slave versions ARE edge triggered, why do ...
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37 views

Using capacitive coupling to implement pulse transition

I was reading about master-slave flip flops, used to implement edge triggering and I read that instead of using master slave configurations, using RC coupling to clock inputs could also enable pulse ...
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44 views

Use of Toggle flip-flops and JK flip flops

I was studying digital electronics, especially latches and flip-flops and the like and I came to understand that flip-flops are basically memory storage elements, in that case why would I need ...
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42 views

Understanding max and min propagation delay in flip-flops

I've been working my way through Digital Design and Computer Architecture, but am very confused by the equations for time delay - what each of the variables are, and how to conceptualize these ...
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1answer
57 views

Clock Deskewing and flip flops

I have a question in my text book that I do not quite understand. I was wondering if someone could please explain what the question means? Such as, what is a deskewed flip flop. How would one find the ...
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55 views

Stable states of RS latch

I am a novice when it comes to electrical engineering and I have a very basic question concerning the operation of RS latches: I am currently working my way through Roth/Kinney's Fundamentals of ...
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2answers
66 views

How to connect an AND gate with a shift register

I'm new to using flip-flops, and making them into shift registers, but what I'm trying to do is turn on a logical AND gate based off the input of two flip-flops. The scenario is: first, a room light ...
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1answer
52 views

detector circuit sequence [duplicate]

How can I solve this exercise? Design a circuit with 2 input X,Y and 1 output Z, that be able to identify the following sequence of inputs: 00,10,00,10. The output Z must assume the logical value 1 ...
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1answer
48 views

Flip Flop circuit - what is high in relation to? [duplicate]

I am reading about "flip flop" circuits (and I've bought one as an integrated circuit to mess with). When it says that when the SET goes high, then Q (output) will be high, what is "high" in relation ...
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149 views

D flip-flops, but no feedback loops: impossible?

Using JK or T flip-flops, it's easy to create a synchronous N-bit counter by cascading them as depicted here: The above circuit has no feedback loops in it. I have run into a situation where I ...
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1answer
63 views

sequential circuit chaser light

I am trying to implement a sequential circuit in logisim that has LED chaser lights (http://www.youtube.com/watch?v=Mo8Qls0HnWo) like on this car. I have tried using D flip flops with a clock and ...
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76 views

Is D flip flop can be combination circuit?

I read that circuits are two type combinational and sequential. In combinational circuit the output depends on present state/input i.e the previous state do not effect the present output. but D flip ...
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53 views

Sporadic Clock Signals from Momentary Switch

I'm having trouble using a NO momentary switch to send clock edges to a J-Kbar flip flop, specifically the TI CD74AC109E(datasheet). I have a switch between +5V and the clock pin, and also added a ...
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160 views

how to draw a timing diagram for a logic circuit

Hello does anybody have a guide to drawing timelines for logic circuits? For flip flops like this Basically I want to draw corresponding timeline for any circuit like this:
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1answer
41 views

A question about how RS latches work and the time an input needs to stay high after it has been supplied!

I have a RS latch constructed of 2 NOR gates, without enable input. Lets say that the in the beginning the output is set to Q=1, Q'=0. (pic1) In a given moment R is pulsed high, and Q is ...
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51 views

Implement a flip flop using an existing flip-flop (JK/SR) and a gate

I'm trying to understand this material better, and I faced the following question: The MU Flip-Flop works according to the following table: Which of the following statements is true, if the ...
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198 views

what is frequency divider and how does it work with d type flip flop circuit?

I am trying to learn about these things but I have very hard time to understand frequency divider and the leading edge and trailing edge of voltage. Please, help is needed if someone explain it in ...
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114 views

Create a simple flip flop circuit

I am just taking a electronics course, and i am trying to understand how to build a flip flop circuit. I would like to build a circuit that has one push button, and one led. Each time the push ...
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1answer
115 views

Circuit to enable (inverted) clock glitch free

This is a follow-up question to http://electronics.stackexchange.com/a/95195/13354, in which I was asking about a specific solution to the more general problem described here. I'd like to create a ...
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69 views

Is it safe to self-reset a flip-flop based on its output state

I'd like to create a logic function that toggles with the (inverted) clock when enabled and stays low when disabled, like so: ...
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1answer
143 views

Capacitor negative voltage in flip flop circuit

I'm trying to understand the basic flip/flop circuit as explained here : http://www.electronics-tutorials.ws/waveforms/astable.html I'm having some trouble understanding how the capacitors work in ...
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1answer
105 views

In digital electronics, is the essence of “on/off” states driven solely by chemically-doped silicon? [closed]

I believe that in digital electronics, such as those measured in binary, we use semiconductor-doped amplifiers to switch electrical signals around. In the simplest sense we could split one analog ...
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3answers
124 views

Clocked edge-triggered timing (contamination delay)

I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
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35 views

What is the difference between level triggering and edge triggering? [duplicate]

I am a student who has just stepped into synchronous sequential logic circuits. The books says latches operates with signal levels and clock controls flipflops. But it doesn't make clear what the ...
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93 views

Building a toggle with a flipflop?

I'm trying to build a toggle that turns a 4 bit counter on or off. Here's where I'm at so far: As you can see, I'm using a single D flip flop. Ideally I want one switch to disable the chip, and ...
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100 views

How does the basic RS Flip-Flop (also known as latch) works?

Ok this is a basic question but i am not able to figure out how does this work 1: This is the representation of the RS Flip-Flop with the truth table given in my book I am not able to connect the ...
3
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1answer
177 views

Flip flop with load/set, reset, clk, and input

I'm not looking for a hardware language description of the flip flop, but the logic gate level to implement. In verilog, the equivalent I'm looking for is ...
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2answers
87 views

How to cycle through bits of information for a hex display?

I am doing some work with a Hex Seven Segment Digital Display with a built in decoder that takes in 4 bits of information. Controlling it I have 4 cascading T-FlipFlops whose outputs are inverted so I ...
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3answers
126 views

Unclocked, edge-triggered version of RS flip-flop?

Is there such a thing as an edge-triggered RS flip-flop? That is, one input would, on rising edge, set the output to 1, and the other input would, on rising edge, set the output to 0. Falling edges ...
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1answer
127 views

Sequential Circuit Diagram: D Flip-Flop

Sequential Circuit Diagram: D Flip-Flop Answer Key ...
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1answer
69 views

What do I do when I have an empty row/column when making a Karnaugh map?

I am working on an assignment for my Architecture and Assembly course and I am tasked with making a circuit using JK Flip Flops to analyze a bistream for when 10110 occurs with overlap. I am ...
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86 views

Do solar flares affect the software when the hardware is turned off?

Do solar flares affect the software when the device is turned off? Like for example, would the windows os got corrupted even when the hard drive is off?
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1answer
317 views

Digital Circuit with Toggle Switch using Logisim

I'm supposed to design a small digital circuit (with Logisim) using basic logic gates, so that when this circuit is used with the chosen switch (which has to be a button), it will make the circuit ...
2
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2answers
151 views

J-K Flip Flop Output

For a J-K Flip Flop, once we have J&K=1, now when the CLK Goes high, so Output goes high on the falling edge, but when does the OUTPUT Goes back to LOW?
3
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1answer
84 views

Creating a simple toggle

I have a signal that goes high at random intervals, and I would like to have each rising edge toggle an output. Something like this: I've looked into flip-flops, but they all seem more complicated ...
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3answers
139 views

How to choose flip flop type for implementation?

How to choose flip flop type for implementation in moore or mealy state diagram? I can't understand this thing. Could someone help me? There are t-type, d-type, s-r type, j-k type. How to choose one ...
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927 views

What is the meaning of JK flip flop's J and K ?

In D flip flop, D means DATA. In SR flip flop S means SET and R means RESET. What is the meaning of JK flip flop's J and K ?
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2answers
184 views

SR Latch Understanding

this is my first post here as I am just getting into this electronic engineering stuff. My question concerns the SR flip-flop or latch, the NOR gate version. I have been reading a copy of ...
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67 views

Finding state diagram of circuit with two T flip flops

I want to find the state diagram of this circuit, there is no input and output. I need to use Excitation table? I would like to get some suggestions. Thanks!
2
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1answer
491 views

How does the D Flip Flop work and WHY does it hold its value?

I'm trying to grasp and understanding of electronics hopefully to work my way up to building an 8 bit computer. I'm currently digging deeper into Flip Flops, and rather than taking them that they ...
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D Flip Flops using logic gates

I am trying to create this D Flip Flop using only logic gates: So far I have this: Am I missing anything here? There should only be one input of c and an output of B1, so would this be correct ...