a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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Trouble analyzing this JK-Flip-Flop (negative edge triggered) timing diagram

Can someone check to see if this timing diagram for a negative-edge-triggered flip-flop looks correct? I see that as it's negative-edge triggered (bubble at clock input), and thus action occurs at ...
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what is the approach to design edge triggered d flip flop? [on hold]

i know the circuit. I implement it using verilog and it giving result correct. like when we have to design any digital circuit we draw truth table. Optimize circuit using K-map and then implement. In ...
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43 views

Can we declare output as “inout” to design a flip flop in VHDL?

I want to design a JK flip flop in VHDL. In this output depends on previous state. One method to implement this condition is by declaring a state as a signal inside the architecture. Another method ...
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42 views

Expression and gate not gate output

The expression I came up with this circuit is A'B + A'CD + C, would the output change to AB' + AC'D' + C' since it is inverted? I'm assuming the D input compliments and cancels out? What would the ...
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271 views

In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, ...
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65 views

Setup and hold for positive edge flip flop cascaded with negative edge flip flop

I know the following for two positive edge triggered flip flops in cascade. ...
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3answers
122 views

Electron flow at the immediate start of this flip-flop circuit?

I am attaching the following image of a flip-flop circuit. I find myself constantly trying to visualise what is occurring at the exact moment the circuit is closed, and the current starts (electron ...
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82 views

How to design new flip flop using JK flip flop

I have an excitation table that called MN flip flop like below. Q Q' M N 0 0 0 X 0 1 1 X 1 0 X 0 1 1 X 1 I try to design a counter that count 0-7-2-3 in ...
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58 views

The proper way to store bits in JK flip flops [closed]

Currently I'm working on a contraption where when a button is pushed, it briefly creates a 4 bit binary sequence. I want to have this binary sequence, 0000 all the way up to 1111, stored properly in ...
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81 views

D flip flop using transmission gates

In this circuit when D=0 and Clk=0 the value passes from w-x-y-z and z= 1. So at z= not D So this path constitutes what is called setup time of the flip flop. But at the same time the value at D ...
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114 views

JK Flip Flop , Counter Sequence?

Three edge-triggered JK flip-flops in a synchronous circuit have the following input conditions. JA = QB KA = 1 JB = 'QA KB = 1 JC = QB KC = 1 Assume ...
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71 views

Timing Diagram question

Can anyone check my timing diagram for me? I have my exam tomorrow and just want to make sure I am understanding these correctly: Any feedback is appreciated. Thanks in advance
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2answers
52 views

Latching circuit that delays the on state for different outputs

First, I'm very inexperienced in designing circuits like this, so I apologize if this seems trivial. I'm basically trying to create a startup sequence effect, where LEDs turn on in a delayed order. ...
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1answer
101 views

Difference between rising edge falling edge D flip flop (asynchronous reset)?

I am answering a question about a D Flip-Flop with Asynchronous Reset with the reset output '0', that is set to be rising edge triggered. What i don't know is the difference between a rising edge ...
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222 views

Cross-coupled logic gates and timing

I had a hard time getting a right title for this question since I'm a software guy trying to get the basics of my hardware down. Since all computers basically start with logic gates and go from there ...
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1answer
56 views

Eliminating Signal Race Hazard in an IC dynamic latch/register!

I work in MAGIC Integrated Circuit software at layout-level. I got an 8bit dynamic register made of 1bit dynamic flipflops that write input on the positive edge of the signal: (Note: I used ...
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1answer
110 views

Integrated Circuit Layout Design - Dynamic Flip Flop?

I need to create a dynamic flip flop like this: In integrated circuit technology, at mask layout level. I then want to create an 8bit register, using 8 of these flip flops, with a common CLK ...
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1answer
50 views

Design 2 JK Flip Flops without Switch Input to K

I have a lab for my Intro to Hardware Course due today. We use TTL. (True= 5v, False= 0v) ...
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501 views

why in some circuit there is use of bubble followed by bar?

It is a circuit of ring counter. The clock here is negative triggered. but for set and clear it use bubble with bar.What is the need of bubble followed by bar. why it can not use a PRE and CLR ...
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2answers
141 views

How to design a left shift register

I want a circuit in which I get the following sequence: 0001, 0010, 0100, 1000, 0001 I know that it's 4-bit shift register. But what is my approach to design ...
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3answers
105 views

Why does my book's D flip flop differ from others?

My understanding of a D flip flop is that when the clock is high and D=1, it sets Q to 1. If D=0, Q is set to 0. So it is like a set to 1 if D=1 and reset to 0 otherwise. The table repeatedly given ...
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44 views

Need for edge triggered versions other than master slave

I am studying synchronous digital circuits and I have come to the conclusion that master slave flip flops are edge triggered? Is my study correct? If master slave versions ARE edge triggered, why do ...
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44 views

Using capacitive coupling to implement pulse transition

I was reading about master-slave flip flops, used to implement edge triggering and I read that instead of using master slave configurations, using RC coupling to clock inputs could also enable pulse ...
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63 views

Use of Toggle flip-flops and JK flip flops

I was studying digital electronics, especially latches and flip-flops and the like and I came to understand that flip-flops are basically memory storage elements, in that case why would I need ...
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1answer
88 views

Understanding max and min propagation delay in flip-flops

I've been working my way through Digital Design and Computer Architecture, but am very confused by the equations for time delay - what each of the variables are, and how to conceptualize these ...
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111 views

Clock Deskewing and flip flops

I have a question in my text book that I do not quite understand. I was wondering if someone could please explain what the question means? Such as, what is a deskewed flip flop. How would one find the ...
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78 views

Stable states of RS latch

I am a novice when it comes to electrical engineering and I have a very basic question concerning the operation of RS latches: I am currently working my way through Roth/Kinney's Fundamentals of ...
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87 views

How to connect an AND gate with a shift register

I'm new to using flip-flops, and making them into shift registers, but what I'm trying to do is turn on a logical AND gate based off the input of two flip-flops. The scenario is: first, a room light ...
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1answer
59 views

detector circuit sequence [duplicate]

How can I solve this exercise? Design a circuit with 2 input X,Y and 1 output Z, that be able to identify the following sequence of inputs: 00,10,00,10. The output Z must assume the logical value 1 ...
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1answer
48 views

Flip Flop circuit - what is high in relation to? [duplicate]

I am reading about "flip flop" circuits (and I've bought one as an integrated circuit to mess with). When it says that when the SET goes high, then Q (output) will be high, what is "high" in relation ...
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244 views

D flip-flops, but no feedback loops: impossible?

Using JK or T flip-flops, it's easy to create a synchronous N-bit counter by cascading them as depicted here: The above circuit has no feedback loops in it. I have run into a situation where I ...
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1answer
89 views

sequential circuit chaser light

I am trying to implement a sequential circuit in logisim that has LED chaser lights (http://www.youtube.com/watch?v=Mo8Qls0HnWo) like on this car. I have tried using D flip flops with a clock and ...
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85 views

Is D flip flop can be combination circuit?

I read that circuits are two type combinational and sequential. In combinational circuit the output depends on present state/input i.e the previous state do not effect the present output. but D flip ...
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57 views

Sporadic Clock Signals from Momentary Switch

I'm having trouble using a NO momentary switch to send clock edges to a J-Kbar flip flop, specifically the TI CD74AC109E(datasheet). I have a switch between +5V and the clock pin, and also added a ...
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433 views

how to draw a timing diagram for a logic circuit

Hello does anybody have a guide to drawing timelines for logic circuits? For flip flops like this Basically I want to draw corresponding timeline for any circuit like this:
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1answer
42 views

A question about how RS latches work and the time an input needs to stay high after it has been supplied!

I have a RS latch constructed of 2 NOR gates, without enable input. Lets say that the in the beginning the output is set to Q=1, Q'=0. (pic1) In a given moment R is pulsed high, and Q is ...
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64 views

Implement a flip flop using an existing flip-flop (JK/SR) and a gate

I'm trying to understand this material better, and I faced the following question: The MU Flip-Flop works according to the following table: Which of the following statements is true, if the ...
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2answers
426 views

what is frequency divider and how does it work with d type flip flop circuit?

I am trying to learn about these things but I have very hard time to understand frequency divider and the leading edge and trailing edge of voltage. Please, help is needed if someone explain it in ...
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1answer
164 views

Create a simple flip flop circuit

I am just taking a electronics course, and i am trying to understand how to build a flip flop circuit. I would like to build a circuit that has one push button, and one led. Each time the push ...
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1answer
193 views

Circuit to enable (inverted) clock glitch free

This is a follow-up question to http://electronics.stackexchange.com/a/95195/13354, in which I was asking about a specific solution to the more general problem described here. I'd like to create a ...
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2answers
82 views

Is it safe to self-reset a flip-flop based on its output state

I'd like to create a logic function that toggles with the (inverted) clock when enabled and stays low when disabled, like so: ...
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2answers
228 views

Capacitor negative voltage in flip flop circuit

I'm trying to understand the basic flip/flop circuit as explained here : http://www.electronics-tutorials.ws/waveforms/astable.html I'm having some trouble understanding how the capacitors work in ...
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1answer
108 views

In digital electronics, is the essence of “on/off” states driven solely by chemically-doped silicon? [closed]

I believe that in digital electronics, such as those measured in binary, we use semiconductor-doped amplifiers to switch electrical signals around. In the simplest sense we could split one analog ...
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3answers
184 views

Clocked edge-triggered timing (contamination delay)

I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
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37 views

What is the difference between level triggering and edge triggering? [duplicate]

I am a student who has just stepped into synchronous sequential logic circuits. The books says latches operates with signal levels and clock controls flipflops. But it doesn't make clear what the ...
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3answers
101 views

Building a toggle with a flipflop?

I'm trying to build a toggle that turns a 4 bit counter on or off. Here's where I'm at so far: As you can see, I'm using a single D flip flop. Ideally I want one switch to disable the chip, and ...
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113 views

How does the basic RS Flip-Flop (also known as latch) works?

Ok this is a basic question but i am not able to figure out how does this work 1: This is the representation of the RS Flip-Flop with the truth table given in my book I am not able to connect the ...
3
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1answer
246 views

Flip flop with load/set, reset, clk, and input

I'm not looking for a hardware language description of the flip flop, but the logic gate level to implement. In verilog, the equivalent I'm looking for is ...
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2answers
89 views

How to cycle through bits of information for a hex display?

I am doing some work with a Hex Seven Segment Digital Display with a built in decoder that takes in 4 bits of information. Controlling it I have 4 cascading T-FlipFlops whose outputs are inverted so I ...
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3answers
166 views

Unclocked, edge-triggered version of RS flip-flop?

Is there such a thing as an edge-triggered RS flip-flop? That is, one input would, on rising edge, set the output to 1, and the other input would, on rising edge, set the output to 0. Falling edges ...