Tagged Questions

a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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1answer
29 views

Does the output of JK Flip Flop toggle continously?

As given in most of the texts and online resources, the JK flip-flop requires a clock signal with an edge detector circuit so that the flip flop will be sensitive to the inputs only when the clock ...
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0answers
41 views

flip flop transfer function

Can same one explain me, if possible, how to get the equation of the transfer function for flip flop like the one below and hence get a plot like this
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1answer
39 views

Can someone explain to me what the 1s catching problem is in the Master Slave Flip Flop?

I have read the explanation in my textbook but I feel that they are too complex and no matter how much I try to understand it I don't seem to get what the difference is when the 1s complement occurs. ...
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1answer
36 views

How to toggle a reset in a counter made up of JK flip flops

I have been playing around with a small circuit which at the moment consists only of a counter made up of 3 JK flip flops. Like so: What I want to add is a reset input pin that will set the 3 LEDs ...
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1answer
25 views

connected d flip flop, propagation time = hold time?

When we connect two d flip flops, the propagation time and hold time have to be the same? or the propagation time have to be bigger than the hold time? I'm really confused please help!!
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2answers
210 views

Toggle two different LEDs with one T Flip flop

Imagine we have one green LED, one blue LED, power supply and resistors and grounds. We also have a switch. Can we toggle between the two different LEDs when the switch is pushed? If the blue LED is ...
1
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1answer
56 views

Purpose of T flip-flop in this circuit (LED)

In this circuit I try to toggle a LED on and off when a switch is pressed. Given the nature of the T flip-flop, when the switch is triggered, it toggles the clock and since T=1 always, it ...
0
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1answer
55 views

T-flip-flop without using a clock [closed]

Is it possible to create a T flip-flop without using a clock? I really need one, but I can't use one with a clock because it requires a signal shortener.
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0answers
42 views

Relay is not isolating properly its sorrounding circuit blocks

It turns out I've been building up an elevator for a project (at College). In general terms, everything appeared to be correct, regardless that I hadn't simulated each part. I decided to begin with ...
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0answers
46 views

How SR - Flip Flop can increase processing speed?

I am working on a project which related to high speed modulation (radio waves with frequency about 400 MHz and propagation delay time in nanosecond range) but I am not sure can I increase speed grade ...
2
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3answers
417 views

Where does the power supply go in an SR Latch?

I understand how an SR Latch works: is S is 1, it will set Q to 1. If R is 1 it will set Q to 0. If both S and R are 0, the value of Q should remain unchanged (right?). So the circuit has these ...
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1answer
63 views

What is reset, preset and clear in a counter circuit?

I know this is a basic question. But I want to know the use of Reset, Preset and Clear in a Counter circuit. How do I use them? An example would be appreciated.
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4answers
227 views

ICs Powering On With Random Values

I've been prototyping a circuit for a first year university engineering project and I've been running into some problems with one section of the circuit that has really stumped me. Basically the flip ...
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1answer
59 views

Microcontrollers [closed]

Is there any other way of interfacing a push button with a LED but not directly with the micro controller? I would like to operate the LED in both method(push button as well as micro controller ...
2
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2answers
227 views

Setup Time, Hold Time - What is the underlying principle for having them?

I'm learning about setup time and hold time of a FF connected to a bus. But the textbook fails to explain exactly why are those needed in an operation. Isn't a FF always powered on and attentive to ...
0
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1answer
38 views

Is a D Type Edge triggered Master Slave flip flop considered a 1bit memory cell?

So in class we talked about how a D-type edge triggered flip flop is considered a 1bit memory cell. I think this is the same for a D-type latch. My question is, since a D-type edge triggered master ...
0
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1answer
70 views

D flip flop simulation: which simulation output is right?

I have always wondered, what is the right solution to the D flip flop when the input changes right at the rising edge of the clock? I have found two solutions of these online but have no clue which is ...
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0answers
73 views

How to create JK flip flop in proteus 8

I want to create a JK flip flop in Proteus 8.0 ISIS simulation tool. This is what I tried, but the problem with this is that the outputs Q and Q' are always zero regardless of what I set J or K. ...
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1answer
52 views

3 State Shift Register with 2-to-1 multiplexers

For a homework assignment I need to Redesign the right-shift register circuit of Figure 12-10 using four D flip-flops with clock enable, four 2-to-1 MUXes, and a single OR gate. The figure ...
0
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1answer
43 views

Different Vcc and input voltage into flip flop

I am building an LED matrix using flip-flops. I will have 128 rows in the matrix, so I am using 16 octal flip-flops, where all inputs to are shared and come from a microcontroller, which uses 5V ...
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2answers
71 views

Signal-driven 3 output logic gate decoder or switch?

I need to build a simple logic gate circuit such that when a single input signal or switch goes low it alternately activates one of three outputs as high. That is, every time it goes low the currently ...
2
votes
1answer
68 views

Combinational logic delay is greater than clock period

Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the ...
0
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1answer
32 views

Initial state of SN74AUP2G80 dual FF

My understanding is that a basic FF will in general power-up into a meta-stable state that then resolves to either H or L (more or less quickly). My question is, does this apply to current ...
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2answers
348 views

What is the difference between registers, flip flops and latches?

I want the answer to the very basic level. I know what they mean individually, but what I am looking for is connection between them.
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0answers
45 views

Trouble analyzing this JK-Flip-Flop (negative edge triggered) timing diagram

Can someone check to see if this timing diagram for a negative-edge-triggered flip-flop looks correct? I see that as it's negative-edge triggered (bubble at clock input), and thus action occurs at ...
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0answers
49 views

what is the approach to design edge triggered d flip flop? [closed]

i know the circuit. I implement it using verilog and it giving result correct. like when we have to design any digital circuit we draw truth table. Optimize circuit using K-map and then implement. In ...
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2answers
57 views

Can we declare output as “inout” to design a flip flop in VHDL?

I want to design a JK flip flop in VHDL. In this output depends on previous state. One method to implement this condition is by declaring a state as a signal inside the architecture. Another method ...
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2answers
51 views

Expression and gate not gate output

The expression I came up with this circuit is A'B + A'CD + C, would the output change to AB' + AC'D' + C' since it is inverted? I'm assuming the D input compliments and cancels out? What would the ...
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4answers
524 views

In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, ...
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2answers
109 views

Setup and hold for positive edge flip flop cascaded with negative edge flip flop

I know the following for two positive edge triggered flip flops in cascade. ...
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3answers
142 views

Electron flow at the immediate start of this flip-flop circuit?

I am attaching the following image of a flip-flop circuit. I find myself constantly trying to visualise what is occurring at the exact moment the circuit is closed, and the current starts (electron ...
0
votes
1answer
101 views

How to design new flip flop using JK flip flop

I have an excitation table that called MN flip flop like below. Q Q' M N 0 0 0 X 0 1 1 X 1 0 X 0 1 1 X 1 I try to design a counter that count 0-7-2-3 in ...
1
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1answer
62 views

The proper way to store bits in JK flip flops [closed]

Currently I'm working on a contraption where when a button is pushed, it briefly creates a 4 bit binary sequence. I want to have this binary sequence, 0000 all the way up to 1111, stored properly in ...
0
votes
1answer
370 views

D flip flop using transmission gates

In this circuit when D=0 and Clk=0 the value passes from w-x-y-z and z= 1. So at z= not D So this path constitutes what is called setup time of the flip flop. But at the same time the value at D ...
0
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1answer
244 views

JK Flip Flop , Counter Sequence?

Three edge-triggered JK flip-flops in a synchronous circuit have the following input conditions. JA = QB KA = 1 JB = 'QA KB = 1 JC = QB KC = 1 Assume ...
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2answers
88 views

Timing Diagram question

Can anyone check my timing diagram for me? I have my exam tomorrow and just want to make sure I am understanding these correctly: Any feedback is appreciated. Thanks in advance
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2answers
68 views

Latching circuit that delays the on state for different outputs

First, I'm very inexperienced in designing circuits like this, so I apologize if this seems trivial. I'm basically trying to create a startup sequence effect, where LEDs turn on in a delayed order. ...
1
vote
1answer
166 views

Difference between rising edge falling edge D flip flop (asynchronous reset)?

I am answering a question about a D Flip-Flop with Asynchronous Reset with the reset output '0', that is set to be rising edge triggered. What i don't know is the difference between a rising edge ...
6
votes
2answers
266 views

Cross-coupled logic gates and timing

I had a hard time getting a right title for this question since I'm a software guy trying to get the basics of my hardware down. Since all computers basically start with logic gates and go from there ...
2
votes
1answer
75 views

Eliminating Signal Race Hazard in an IC dynamic latch/register!

I work in MAGIC Integrated Circuit software at layout-level. I got an 8bit dynamic register made of 1bit dynamic flipflops that write input on the positive edge of the signal: (Note: I used ...
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1answer
145 views

Integrated Circuit Layout Design - Dynamic Flip Flop?

I need to create a dynamic flip flop like this: In integrated circuit technology, at mask layout level. I then want to create an 8bit register, using 8 of these flip flops, with a common CLK ...
3
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1answer
60 views

Design 2 JK Flip Flops without Switch Input to K

I have a lab for my Intro to Hardware Course due today. We use TTL. (True= 5v, False= 0v) ...
6
votes
2answers
538 views

why in some circuit there is use of bubble followed by bar?

It is a circuit of ring counter. The clock here is negative triggered. but for set and clear it use bubble with bar.What is the need of bubble followed by bar. why it can not use a PRE and CLR ...
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2answers
185 views

How to design a left shift register

I want a circuit in which I get the following sequence: 0001, 0010, 0100, 1000, 0001 I know that it's 4-bit shift register. But what is my approach to design ...
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3answers
114 views

Why does my book's D flip flop differ from others?

My understanding of a D flip flop is that when the clock is high and D=1, it sets Q to 1. If D=0, Q is set to 0. So it is like a set to 1 if D=1 and reset to 0 otherwise. The table repeatedly given ...
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2answers
49 views

Need for edge triggered versions other than master slave

I am studying synchronous digital circuits and I have come to the conclusion that master slave flip flops are edge triggered? Is my study correct? If master slave versions ARE edge triggered, why do ...
0
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1answer
54 views

Using capacitive coupling to implement pulse transition

I was reading about master-slave flip flops, used to implement edge triggering and I read that instead of using master slave configurations, using RC coupling to clock inputs could also enable pulse ...
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2answers
93 views

Use of Toggle flip-flops and JK flip flops

I was studying digital electronics, especially latches and flip-flops and the like and I came to understand that flip-flops are basically memory storage elements, in that case why would I need ...
2
votes
1answer
158 views

Understanding max and min propagation delay in flip-flops

I've been working my way through Digital Design and Computer Architecture, but am very confused by the equations for time delay - what each of the variables are, and how to conceptualize these ...
3
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2answers
129 views

Clock Deskewing and flip flops

I have a question in my text book that I do not quite understand. I was wondering if someone could please explain what the question means? Such as, what is a deskewed flip flop. How would one find the ...