a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
2
votes
1answer
48 views
How to escape redundant stated when using J-K Flip Flops?
I've designed a counter using three J-K flip flops, but I have two redundant states. How can I ensure that the system has a way to escape these states if they occur?
I've tried searching for help on ...
0
votes
0answers
60 views
Which gate should be considered when writing the characteristic table of a filp flop?
Background
I have this problem for like two weeks, I tried search in the web, but i did not get anything useful. I don't know it is because my question is stupid, But my friend also had this same ...
2
votes
2answers
47 views
Easy resource to learn solving counter problems?
Could anybody please point me some direction on where I can learn to solve simple counter problems like counting in a given sequence using a given flip-flop? For example:
Create a counter counting ...
-6
votes
0answers
51 views
3 bit counter using d flip flops [closed]
i need to design a 3 bit counter that will increment and decrement a stored value by a 3 bit value depending on the positive edges of a signal C. Must use 3 D flip-flops. any help would be appreciated ...
0
votes
0answers
52 views
Using D-Flip Flop for MSB and JK-FF for LSB
I have the above question as an exercise. I know how to do all of the operations. However, I didn't get the point where it says "You are required to use a D-FF for the
MSB, (A) and a JK-FF for the ...
1
vote
3answers
96 views
Can someone help me complete this Verilog code for this sequential circuit?
I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have ...
5
votes
4answers
261 views
Why do we clock Flip Flops?
I am trying to understand Flip Flops & Latches. I am reading from Digital Logic book by Morris Mano. One thing I am not able to understand is why do we clock flip-flops ?
I understand why do we ...
1
vote
2answers
104 views
What makes these simple circuit diagrams different?
I'm kind of confused with the behavior changes of these 3 differences of a flip flop.
I made an image to easily show what I'm asking about. I circled the differences in red.. Heres the image:
For ...
0
votes
1answer
189 views
Can someone help check my solution for this timing diagram?
I've been working on some timing diagrams and I keep mixing up the behaviors for the different flip flops.
EDIT:
I think I have the logic correct. If someone could please let me know if I'm ...
2
votes
1answer
90 views
Why does my D Flip Flop Circuit have an X output?
I'm working on one of my projects and I'm having trouble with my flip flops. The project is to design the circuit for a gas pump that has a handle and a sensor. When the handle is down, the pump ...
0
votes
3answers
87 views
How can an SR Flip Flop be made using a D Flip Flop and other Gates?
An SR flip flop is a flip flop that has set and reset inputs like a gated SR latch. How can an SR Flip Flop be made from using a D Flip Flop and other logic gates?
I've done several searches online ...
1
vote
2answers
90 views
How do I use T-Flip Flops to derive circuits - given the clock signal speed?
I've been trying to do my EE homework for several hours and cannot figure out how to do this stuff.. I've read through the chapter multiple times, searched YouTube and Google, and nothing seems to ...
1
vote
1answer
48 views
Invalid inputs in a SR Latch & Enabled SR Latch
Lets consider a SR Latch built with NOR gates. The invalid inputs are S=1, R=1. With enabled latch [gated latch], the invalid inputs are same, S=1, R=1.
Now, lets consider, NAND gates, in SR Latch, ...
6
votes
3answers
278 views
Why is S=1, R=1 state forbidden in RS flip flop?
I have come across the RS flip flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the unstable or the ...
6
votes
5answers
236 views
How to understand the SR Latch
I can't wrap my head around how the SR Latch works. Seemingly, you plug an input line from R, and another from S, and you are supposed to get results in Q and Q′.
However, both R and S require input ...
0
votes
1answer
460 views
3 bit synchronous counter design d flip flop
Any idea how I would go about designing a 3 bit synchronous counter in regards to having the following states
...
1
vote
4answers
117 views
9-Bit State Machine
I am working on a state machine that will drive a state bus for a personal project. The state machine will have an output pattern like the following:
...
3
votes
2answers
128 views
What values / components do I need in this flip-flop circuit?
I need a circuit to make a relay toggle when pushing a push button. I found this circuit here:
It looks good for me - please tell me if it won't work.
I intend to work with a push button to Vcc ...
-1
votes
1answer
82 views
What happens to a 32-bit input when a gate will only output 1 bit?
For example, suppose I have a combinational circuit that takes 32 bits as input and outputs 1 bit that is equal to 1 if the 32-bits are equal to 0, and outputs 0 if the 32 bits are anything else. How ...
2
votes
1answer
551 views
What are carry-lookahead adders and ripple-carry adders?
I see carry-lookahead adders and ripple-carry adders terms being used often. I have no idea what either means (nor the type of architecture they describe).
Can someone please explain what each one ...
-3
votes
2answers
146 views
Drawing circuit activity through a D flip-flop while ignoring propagation delay
Can someone explain how would would draw the Y and Z activity in the following problem (if we ignore propagation delay and assume Y and Z start at 0)? How do the clock and X help in this problem? ...
1
vote
2answers
144 views
What is the function of resistors in this flip-flop circuit?
Here's the link to the circuit:
http://rustamaji.net/resource/images/flip-flop2.swf
From the simulation, when the 22k resistors are removed the LEDs stop blinking because the current flowing only ...
5
votes
5answers
471 views
Can someone explain the following flip-flop circuit?
I'm having trouble understand what's going on in this circuit. The question asks "what is the value of Q if \$\bar{R} = 1\$ and \$\bar{S} = 0\$" (as shown).
In this case, how can I determine ...
4
votes
2answers
168 views
SR Latch (Flip Flop) beginning Inputs?
Ok this is probably a basic question, but I understand how SR latches work except one thing.
In the R input and S input you can make them 0 or 1.....but what about the input lines next to them (That ...
-4
votes
2answers
294 views
How do I build a 4-bit synchronous direct counter using only D Flip-Flops? [closed]
I have to build a counter using only D Flip-Flops and wires. What's the approach?
3
votes
2answers
154 views
Finite State Machines
I want to design a finite state machine that is similar to a 3 bit counter. There are 3 bits of state (i.e. a 3 bit unsigned number) and the counter must count by 3's. More specifically, the sequence ...
3
votes
2answers
165 views
sequential circuits; clocked SR flip-flop
I'm learning about sequential logic and am wondering about the behavior of a clocked SR flip-flop.
If R=S=0, then the AND gates evaluate to 0. In that case, and if the recurrent inputs to the NOR ...
1
vote
2answers
267 views
Flip Flops and Propagation Delay
I'm working on designing an 8 bit home brewed CPU and in this process I'm using Octal D Flip Flops as registers to store data. One of the issues that I've ran into is the need to execute multiple ...
0
votes
1answer
125 views
7475 IC strange behavior
So I'm trying to make a shift register with the 7475 IC /4-BIT BISTABLE LATCHES/.
The problem is that the single latches doesn't seem to switch their states properly.
I'm using this schematic:
...
18
votes
7answers
391 views
Why is the output of stateful elements often named Q?
In logic circuit diagrams, I've seen various conventions for naming inputs and outputs of logic gates and combinatorial circuits. However, stateful elements like latches and flip-flops often have ...
0
votes
1answer
38 views
Need Help With A Component(Octal D Flip Flop)
I'm analyzing the following component:
http://www.futurlec.com/74HC/74HC574.shtml
It says that this flip-flop has a high impedance state when the output control bit is raised high. Does this allow ...
2
votes
3answers
309 views
Understanding Flip Flops/Registers in Low Level
So I'm reading "Elements of Computing Systems" trying to really understand how everything works underneath (Any other book/article suggestions that would help would be amazing) Since eventually I want ...
1
vote
1answer
261 views
How do I implement a simple finite state machine with 2 T flip-flops?
The following Finite State Machine (FSM #1)
can be implemented with 2 T flip-flops like so:
This makes sense because you have 4 different states {00,01,10,11} and flip-flip TA handles the left ...
3
votes
2answers
204 views
Asynchronous inputs to timing diagram
I'm very new to hardware logic (and this site) but I'm trying to understand the exact use and duration of the asynchronous inputs clear (CLR) and preset (PRE) on flip-flop timing diagrams. They seem ...
0
votes
2answers
237 views
Multiplexer + flipflop all in one?
As you know if you have a 4 bits multiplexer, if you input 0101 the output 5 goes high, but right when you input another thing like 0001, output 5 goes low and output 1 goes high.
I need the ...
0
votes
1answer
68 views
Data transfer between FFs in a CPU
I was in computer organization lecture and when we wrote what the CPU does during an add instruction (like micro instructions) something got me thinking.
I didn't understand how we let one of the FFs ...
3
votes
3answers
774 views
When should I use SR, D, JK, or T Flip flops?
In class I've learned about SR, D, JK, and T flip flops. From what I understand, you can construct any design by using any of them. So my question is when making a design, how does one choose which to ...
0
votes
1answer
116 views
set and reset of D flip-flops : always physically present?
On various technology (discrete, ASIC, FPGA), I'd like to know if the asynchronous signals set and reset are always present on D (edge-triggered) flip-flops. If not how the reset process can be ...
-1
votes
1answer
119 views
Toggling of D flip flop
To divide the frequency of green signal into half, I use D flip flop to generate the blue signal. I need to generate blue signal which is aligned with yellow signal. However, since the green and ...
1
vote
2answers
961 views
Design a 4-bit synchronous counter using D filp-flops and 16 x 4 ROM that can generated any arbitrary counting sequence
What are the restrictions on the counting sequence? Give the ROM contents for the following sequences: a) 12, 13, 14, 15, 5, 6, 7, 0, 1, 2, 3, 4, 11, 10, 9, 8, 12, 13, etc...
b)8, 9, 0, 1, 8, 9, ...
-6
votes
1answer
127 views
Toggling problem of D flip flop [closed]
how to do frequency divider by 2 without having the toggling issue ? Since I just want to divide the frequency by half and align that signal with single pulse signal.
0
votes
2answers
144 views
How to build SIPO from RS
can anybody help me how to build a SIPO (Serial In Parallel Out) register just from the RS or RS edge triggered flip flop circuit?
I have tried to build this, but I think its not working. I ...
4
votes
2answers
674 views
What is wrong with my D flip-flop toggle switch?
Until a few weeks ago, I had never drawn a circuit diagram in my life, so bear with me. I am currently trying to design (in Logisim) a circuit that acts like a toggle switch, using only basic logic ...
5
votes
1answer
355 views
Turning a microcontroller on with a flip flop
I'm working on debugging a circuit that I've built and am trying to wrap my head around an issue.
I have the following circuit (74LCV is an inverting flip flop and the NCP1400 is a boost converter):
...
3
votes
1answer
84 views
Synchronising GPIO transitions to an external clock
Currently, I am using an ADC with an external trigger with the caveat that the edge of the trigger must be within +/- 25ns of the ADC's clock (See Figure 3 of the datasheet). The ADC's clock is ...
4
votes
2answers
221 views
How to design system for n bits?
Say I want to design an n-bit system e.g. 256 bits. Can I generalize a 4-bit ALU which I think I know to 256 bits? These are my diagrams.
4
votes
3answers
238 views
Are D-latches and D-type flipflops volatile?
If there is a power cut to the CPU, will be registers clear or keep their memory?
3
votes
2answers
235 views
Flip flop/latch with isolated differential input and differential output
I am looking to make something that takes a pulse of floating voltage (say from a feedback coil of on a transformer), and maintain a differential output voltage depending on the sign of the amplitude ...
1
vote
4answers
280 views
What is a fan-in of a flip flop?
What is a fan-in of a flip flop?
It is mentioned in the following context: "...primary inputs that are in the fan-in of each flip flop."
4
votes
3answers
2k views
What is hold time violation?
I am currently reading about Pulsed Latch Circuit. And there is a frequent mention of "hold time violation". Like:
For latch, "...data must be held for a longer period of time,
increasing the ...
