a flip-flop or latch is a circuit that has two stable states and can be used to store state information.

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Asynchronous Down Counter Using D Flip Flops Simulation Not Working As Expected

I'm a bit new to this, but I just want to have some insight as to why my circuit simulation doesn't work as planned (I'm using Quartus 2, qsim). Here I have designed an asynchronous down counter ...
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36 views

How does a shift register work [on hold]

I would like to understand better how a shift register (SIPO) works. I understand it's a series of flip-flop wired together, but I have been unable to find information on exactly how a flip-flop ...
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55 views

Flip Flop D Sequence

I want to create a game like "pimball" using 4 leds to state the game. One exit to define if the game is still running. And 2 inputs that are switches. 1) To begin with, the first is to assemble 4 ...
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46 views

Number of logic gates for counter with each type of flip flop

I am designing two synchronous counters one mod 21 and the other one mod 30. Is there a way to know which kind of flip flop (D, SR, JK, T) will use the smallest number of logic gates? I know we can ...
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58 views

frequency divider for two output frequencies

I want to make a frequency divider from flip flops that can generate two frequencies. For example, if the input frequency is fin then the output frequencies will be fin/30 or fin/35 depending on the ...
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43 views

D type flip flop feedback

The D type flip flop needs feedback from its inverted Q output to divide frequency by two. Is there an intuitive explanation for this?
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60 views

frequency divider by 42 with 50% duty cycle

I want to design a clock divider by 42 from flip flops. Is there a way to do that while still gets 50% duty cycle?
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42 views

Are these flip flop conversions correct

Hi I am from computer science background and hence lack any solid foundation in electronics. I am trying to learn some flip flop conversions. Most of them are their online, however I did not found ...
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48 views

transition speed causing issue with jk flip flop

i'm using jk flip flop to latch on a state given by 2 switches to either stay ON or stay OFF, knowing that one of them could stuck on ON which is why i use one of them as the clock input for the 4027B ...
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Counter with 4 flip flops jk synchronous from 3 to 13 [duplicate]

I have to create a counter with 4 flip flops jk synchronous. The counter shall count in this order: 3 to 13 and then to 3 to 13 and so on.. I have to use logisim simulator. Until now what i´ve ...
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38 views

Create Moore machine with logicly

I try to implement a Moore machine with http://logic.ly. I don't know if I do something wrong or whether it's a application limitation but I'm not able to get a working connection from the d-flipfop ...
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210 views

Counter with 4 flip flops jk synchronous from 3 to 13!

I have to create a counter with 4 flip flops jk synchronous. The counter shall count in this order: 3 to 13 and then to 3 to 13 and so on.. I have to use logisim simulator. Ok. So i think its ...
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36 views

multilevel storage elements

I've been experimenting with three-valued logic (yeah, I know) and have had quite a bit of success by using voltage comparators to implement the combinatorial logic. All 27 1-input gates and many ...
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60 views

Why is D Flip Flop Positive Edge Trigger instead of a Level Trigger

So i'm trying to understand this D type Positive Edge Flip Flop: simulate this circuit – Schematic created using CircuitLab I'm having problem understanding why it's a Positive Edge ...
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2answers
76 views

Beginner trying to understand flip flops

I'm trying to understand how JK and D flip flops work. I am generally very airy when it comes to these topics and was hoping someone could explain in layman's terms how these two circuits work. It is ...
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2answers
73 views

Why is this a Moore and not a Mealy FSM?

Can someone please explain how I can tell which FSM type I have? In my textbook I read that output in a Mealy FSM is based on both the input and the present state, but in a Moore FSM it is based only ...
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1answer
92 views

Modulo 10 Counter using T flip flops?

so I have been tasked with making a counter that counts from 0-9 continuously and pauses when the input is 0. Of course this has to be done with T flip flops, but for the life of me I cannot figure ...
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3answers
37 views

Is there a latch / flip-flop with this behaviour?

I've looked at the most popular flip-flop types, and none of them seem to have this desired behaviour: It would have two inputs: A set signal, S, and a data signal, D. If the set signal is true, it ...
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40 views

Algorithmic State Machine using D flip Flops - how to deal with don't care conditions

I have the following state transition table: where, A, B - current states of two D flip flops A+, B+ - next states of the two D flip flops X1, X2, X3 - inputs to the current states There are ...
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39 views

How to terminate binary counting using a logic gate

So I am designing a 3-bit asynchronous binary counter which counts up to 11 then repeats using D flip-flops. That much I have done, however I am stuck when it comes to decoding the outputs to stop the ...
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54 views

Flip flop unused states

in one of my project i have 5 states , to which corresponds 3 flip flops . But 3 flip flops encode 8 states. My question is: the 3 unused states, when I create the Next State equation, are considered ...
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149 views

Modeling the elevator as a finite state machine

This is my first post here. Nice to meet you all! I've read a related question here and am still having issues. The task: There is a building consisting of 7 storeys (indexed 0-6). Design a system ...
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61 views

Need help in understanding flip flop

I have problem with understanding the feedback part in flip flop. Consider a flip-flop circuit containing just two NAND gates as shown in the picture below: Problem 1) Let A & S' be the inputs ...
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53 views

How does a flip-flop circuit keep it state?

When reading about the difference between SDRAM and SRAM (electronically), I understand that SDRAM requires the dynamically charging of the capacitors to maintain their states. I do not get how SRAM ...
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35 views

Finite State Machine not initializing in planned initial state

I have an assignment where where I have to design a FSM which outputs the following Hex number in binary, one digit at a time: 12498A3B. The FSM must use a clock signal and D flip-flops to do so. I ...
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36 views

Question on JK Flip flop Output waveforms

I'm fairly new to the world of Flip Flops, and this type of material. I'm hoping to gain some clarification on how to correctly create output waveforms based on different implementation. I'm not ...
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99 views

4-bit Finite State Machine with 6 states and synchronous reset using D Flip-Flops

I have recently began studying Digital Electronics and have hit a wall trying to figure out how to design FSMs. At the moment, I am attempting to desing the FSM in the title which generates the ...
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38 views

Reconize JK Flip-Flop operating edge: rising or falling?

This is a JK Flip-Flop image. Using this image is there a way to know if the output changes on raising or falling clock? In other words, is input data transferred to the outputs on the HIGH-to-LOW ...
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38 views

Are all T flip flops master-slave JK flip flops?

I'm busy learning about flip flops. It's my understanding that JK flip flops toggle when JK are both 1. However without a master slave arrangement this will lead to a race condition, so the master ...
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51 views

Mealy FSM using T flip flops

So I am to design a mealy state machine which detects the sequence 101. The state diagram was given, and from there I obtained the flip-flop excitation equations. I am supposed to use 2-1 multiplexers ...
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59 views

JK flip-flop: What is the difference between clear and J=0, K=1, rising clock?

I'm trying to create a Program Counter using some JK flip-flops. I have two different way to do that: Use some 74LS73 (dual ...
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1answer
67 views

Output of a D flipflop upon power up?

I guess the output state of a D-flipflop is unknown upon power up. But what are the chances that it is neither 0 nor 1 but an intermediate state such as VDD/2? The D-flipflop in this question has an ...
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159 views

JK Flip-Flop as a frequency divider by 3 with a Duty cycle of 50%

I've been doing a little research into this but I cannot find anywhere on how to divide a frequency 3 by 3 using JK flip flops, only this: http://www.falstad.com/circuit/e-divideby3.html But it is a ...
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63 views

What's wrong with this ring counter made using D Flip Flop?

I have created this ring counter using D Flip Flop in multisim(I am learning counters). It's not working maybe due to the switch provided on the top left for the preset pin of D Flip Flop. I have no ...
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78 views

Design an ALU that only adds

I need some help designing a simple ALU that only can add (4-bit) numbers. For the design I can only use 4-bit full adders and 4-bit edge-triggered flip-flops. I am stuck as I do not even know where ...
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138 views

Tic Tac Toe Game - Player Indicator

I am creating a circuit in Logisim which allows two players to play a game of Tic Tac Toe. The game begins when the "Begin Game" button is pressed. When it is pressed, a random player is selected to ...
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108 views

Do registers have a multiplexer?

We are learning about general purpose shift registers. My professor draws them with like multiplexers connected to the D's of each flip flop. So in an example of a register with a 4 bit input and ...
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1answer
99 views

Asynchronous Cascaded Counters Problem!

What is the Frequency and Duty cycle and of the waveform at Z (say if input clock frequency is 1.5Khz) My Understanding: Two negative edge triggered MOD 12 counters cascaded and reset when the ...
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1answer
97 views

How does this SRAM work?

I have to simulate a SRAM and I already replicated the circuit in Proteus. Still, I'm unsure where to start. I haven't found any table to see how to assign data and then how to read it. Could anyone ...
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22 views

T-setup and T-hold in ETDFF with long pulse

I try to understand why if I use ETDFF with long pulse the T-setup and T-hold are negligible. How I could understand T-SetUp effect doesn't depend on how long my pulse was "up".If my input wasn't ...
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40 views

Why is the output in a Moore Machine determined by the current state?

It makes sense to me that the output in a Mealy machine should be determined by the input and the current state because it gives me the feeling that it is really an output. But the outputs in a Moore ...
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245 views

Large Frequency Divsion

I am currently trying to design a circuit that needs a large frequency division, 25353 to be exact. I'm aware that I could do a large complex flip flop arrangement to achieve close to the desired ...
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120 views

Master Slave Flip Flop Issue

I am trying to implement JK Master Slave circuit in Proteus ISIS. As the Master Slave circuit of JK Flip Flop overcomes the racing effect so this circuit should work. But it is giving the following ...
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87 views

Parallel binary counter using T flip-flops

Can someone explain me how this parallel binary counter works: For example, if the state in the beginning is 0000, what happens when Pt goes high?
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1answer
41 views

Cyclical output counts from a D Flip Flop, what is this effect called?

While working on a frequency divider/counter (in this case a frequency subtractor) using flip-flops, I discovered a strange effect in a D flip-flop when I left the clock at a constant frequency, but ...
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40 views

Do any flip-flops use separate clock levels for “sample” and “propagate” events

Many kinds of sequential logic require that the output of one register be fed into the input of another register which is strobed by the same clock. In such logic, it's necessary to ensure that a ...
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57 views

This flip flop does not work properly

I'm trying to make a "Toggle Latch" or toggle flip flop. The S-R latch works properly (The two NOR gates). when I add the two AND gates, the output led turns off and it does not respond to the inputs ...
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104 views

Can you calculate clock to output delay from setup time, hold time and the propagation delay of wires?

"minimum tCO = <shortest clock to source register delay> + <micro clock to output delay> + <shortest register to pin delay>" is what I found on this ...
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158 views

What happen when input changes the same time clock pulse changes in edge triggered flip flop?

For example take positive edge triggered D flip flop.If input (D) changes from 1 to 0 at the same time when clock pulse goes from 0 to 1(positive edge of clock pulse), what will be the output (Q).Will ...
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208 views

What is the simplest way to make an AND gate using PNP transistors

I only have 5 PNP transistors and I want to build two AND gates. (for a T Flip-Flop) What would be the simplest way to make an AND gate using PNP transistors? (It can't use more than 2 transistors) ...