A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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How to use UART port for sending status in verilog

I am developing various verilog modules with state machine for a fpga board. When i have done simulation of the modules i have used "$display" to get what is happening in the module or otherwise the ...
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36 views

BPSK modulator with DDS on FPGA

I was developing a BPSK modulator with an AD9852. Since AD doesn't seem to offer any way to functionally simulate their DDS ICs, suddenly i see myself in the need to change for a FPGA architecture. I ...
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1answer
42 views

How do i connect my Nexys 4 Artix-7 Digilent FPGA board to my PN532 NFC/RFID Controller Shield for Arduino?

I am currently working on a FPGA project which i know nothing about. Truth to be told, I am learning how the FPGA and the Verilog language works from scratch and I am indeed experiencing lots of ...
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2answers
49 views

Access NEON coprocessor from programmable logic in Zynq

For the past few days I've been thinking about the neon coprocessor in the Zynq SoC and I have a question, is it possible to send instructions to the neon from the PL side of the SoC? Imagine I have ...
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27 views

Any resources for understanding FIFO structure in FPGAs?

I'm writing a state machine (in verilog) for FIFOs which interface with external SRAM with different clocks for read and write, and couldn't find a reference to calculate the relation between read and ...
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2answers
44 views

What arguments to use to switch from graphical design entry (HDL)? [closed]

I am an experienced FPGA designer with background in Information Technology and therefore used to GIT and Test Driven development for FPGA designs. Of course flow was automated by Make scripts, so ...
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25 views

How would you implement a System like this easily using Altera Tools and the DE1-SOC

I want to implement a system as follows: Four cores (Processing Elements) to read a black and white image of 240x240 pixels = 57.600 pixels in total (each pixel with a intensity integer value of 0 to ...
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1answer
54 views

Input/output for buck-boost converter controller implemented with FPGA

I am trying to implement a voltage controller for a buck-boost converter using FPGA. The control method I'm trying to use is in this paper: www.engr.iupui.edu/~aizadian/index_files/Papers/C-28.pdf ...
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1answer
95 views

I2C camera not working 100% of the time

This is my stereoscopic system: I'm using a zedboard to pilot two i2c-camera MT9D111: http://www.dragonwake.com/download/camera/MT9D111/mt9d111_rev5.pdf Camera PCB Information: ...
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4answers
94 views

Are FPGAs more intuitive to learn than microprocessors for doing DSP

I want to learn to make DSP hardware I have never done any DSP and only a little bit of programming, but I have been making analog circuits for 15 years. I like the idea of learning FPGAs because it ...
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1answer
66 views

How to properly describe a Math Equation in Verilog to be synthesizable?

I have not been able to find a book or information in internet, about the correct way to describe a Math Equation in Verilog. With the correct way I mean for example, how to analyze the equation and ...
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2answers
64 views

74LSxxx Logic IC library for FPGA

I need to try different 74lsxxx logic ICs over a FPGA. As examples 4 bit adders, counters, etc which are more complex than primitive logic ICs. And it is time consuming and error prone to code in ...
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40 views

Testing eMMC host controller on a development board having SD connector

I have xilinx's ZC702 evaluation board. The board has SD connector. I want to test my eMMC host controller. I have found out some SD/eMMC adapter (http://www.kingston.com/en/flash/emmc). This adapter ...
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2answers
116 views

Interfacing a FPGA to an Intel processor

So I gave my laptop a long overdue processor upgrade and it left me with a spare Intel Core Duo T2300E processor in perfectly working condition. So I am thinking maybe I can forgo the standard Intel ...
3
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1answer
58 views

Why is my VHDL clock signal so far off from what I thought it would be?

I'm new to FPGA and VHDL. The following code was supposed to be 5MHz but I'm getting 4.167MHz on my scope. The FPGA board I ...
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1answer
52 views

FPGA design rules - Using a Module Output Register Value Internaly

I'm trying to optimize a verilog code and I found something that I don't feel it's correct. I found a module that has an output and it's using that output value as a condition in a case statement. ...
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26 views

Timing Requirements - Worst case Removal Slack

I have a critical warning for Worstcase Negative removal slack of -2.461. From node: - altera_reserved_tck To node: pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967 I am not sure if I ...
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2answers
24 views

How to make an .sof upload to an Altera Max10 stick

I have a Max10 dev board with a 10m08 chip on it. I made a simple counter to blink the LED's. My counters have asynchronous resets, and my asynchronous reset has a circuit to keep it low for two clock ...
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1answer
84 views

Separating Two High Speed Digital ICs

Previously, I've designed a PCB incorporating this ADC chip. It has a digital bus of 10 signals some of which are 40MHz. Right now we have a four layer PCB and the ADC is connected directly to a ...
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84 views

FPGA ft232h/ft2232h communication problem

I am trying to output an image from a Kintex 7 fpga using the ft232h chip. What's supposed to happen in this process is: the fpga must wait until some input pin txe# goes down, then the fpga should: ...
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1answer
51 views

Some question about RTL Design and VHDL

I have some question almost uncorrelated, so I'll enureamted it, hope you can help me: 1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand ...
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46 views

FPGA: need a stepper motor controller with smooth acceleration [closed]

I want to connect a stepper motor to my Cyclone V FPGA via a STEP/DIR-interfaced driver. But I don't want to simply give N pulses with F frequency. I want to set its max acceleration and deceleration. ...
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1answer
251 views

Vivado is removing registers which will be used

I am working on a verilog program that I want to have display some sort of audio waveform (captured from my microphone) over a VGA. I use the following module to shift in new audio samples, and swap ...
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35 views

Generated clock constraints in vivado

I created my own clock since I need a 2Mhz clock and the clock generator IP wont let me go bellow 6Mhz. I created a clock divider module. ...
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1answer
42 views

Is $realtobits synthsizeiable?

I have been trying to figure out why my verilog program is not working for hours. To test it I just added some constants as inputs to my module and I am using the integrated logic analyser to check ...
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1answer
45 views

IP simulation with Vivado

I have just used an IP in the IP catalog called Multiply accumulate. This IP is supposed to multiply 2 inputs and accumulate the result. I made a control module for it(mac_control) where I instantiate ...
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46 views

Cycles lost on clock domain crossing

I have a MAC (VHDL) connected to the PHY through RGMII (so the clock for this communication is 125 MHz). The MAC outputs every byte at a rate of 200 MHz, so there is some clock domain crossing here. ...
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1answer
45 views

How to design a suitable low pass filter for different waveform

I want to realize a DDS signal generator based on FPGA,which is composed of FPGA,DAC and low pass filter,and the FPGA control a DAC to output different kind of signal. Here are the system performance ...
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26 views

Using on board SPI of Basys 3 to store custom data

I have a Basys 3 board which has an on board SPI flash memory. Configuration bitstream of the implemented logic can be written to this memory through vivado. Reference manual of the board says that ...
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1answer
54 views

Why SATA ALIGN primitive is shifted or swapped on 7-Series GTXE2 transceiver RXDATA output?

I am using a Xilinx 7-Series GTXE2 Transceiver configured as SATA host PHY. This transceiver is interfacing with an SATA Host controller and an SATA Gen1 device. During initialization, I am able to ...
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2answers
62 views

How FPGA firmware writes in flash?

In some boards, like Papilio, spi flash connected only to fpga. As I can understand the firmware writes to flash through fpga. How does it works? Doesnt fpga need firmware first to work? If so, how it ...
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88 views

How long to program a FPGA - seconds, microseconds, less?

How long does it take to load a new configuration on a FPGA? can a FPGA be re-programmed on the fly while a computer program with offloads to the FPGA is running?
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57 views

Vivado IP is locked due to license

I just got the nexys video from diligent. I want to get the HDMI output working. I went to use the HDMI 1.4/2.0 Transmitter Subsystem IP. When I try to generate the output products I get the ...
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1answer
48 views

How can I constrain an imported netlist in Vivado?

I have a pre-compiled netlist (created by Xilinx ISE 14.7), which is imported into Vivado 2015.4 and used in synthesis to assemble my complete design. Vivado reports unconstrained paths for the ...
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55 views

Where to find maximum current for FPGAs? [duplicate]

I am designing a project using te EP4CE6 FPGA. The problem is i cannot find the maximum current it can draw from each rail anywhere. There is the excel tool for calculating consumption that I cannot ...
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1answer
38 views

I want to know when the AD9235BRUZ-65 outputs data? I cant make sense of the datasheet or find a way to simulate it

I need to know when data is output from the AD9235BRUZ-65 digital pins. I need this to create a type of handshake with a FPGA. Would appreciate any help, thanks. DATASHEET : ...
2
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1answer
49 views

Configuring multiple FPGA using JTAG

I have 2 devices, a Spartan 3 and a Spartan 6. I am trying to configure both of them through JTAG. One way to do this is to daisy chain the devices and use boundary scan. However , one thing I still ...
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40 views

Index in block ram is offset by one from position of write

I am having an issue with block ram I am using to create a table to powers of a 64 bit floating point number. I store powers between x^1600 and x^-1600. For some reason when I try to read the table ...
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2answers
80 views

How to convert data before sending it to FIFO [Xillybus - VHDL]

I connected my own FIFO to xillydemo. More precisely, xillydemo receives some data, it has to convert the data and the forward the data to FIFO. in turn the FIFO should send data back to xillydemo. ...
2
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2answers
80 views

When should I use negedge on a clock signal?

I was reading about block ram and I came across the following post. I notice here that whoever wrote the code is using negedge on the clock signal. Thus far almost all the examples I have seen of ...
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2answers
45 views

Xilinx IP for delaying data

I am working on a block design to compute the coordinate in the complex set represented by a pixel. Given an x and y pixel value, the step size, and starting x and starting y I need to compute a ...
5
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1answer
85 views

Disadvantages of Schmitt Trigger Inputs

I'm familiar with the utilization of Schmitt Triggers when interfacing with low slew rate signals / sinusoidal waveforms. In a recent design, I've been scrubbing our FPGA I/O configurations and ...
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0answers
54 views

What Transfer Protocol for “Streaming over USB”

I'm programming the FPGA on the Red Pitaya and I'm using it for gathering datas and generating images with those datas. Then, I need to transfer the images to an Android device. I so need to use the ...
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34 views

I get error in vivado when I try to use source clock of generated one

I want to have two clocks in my project. One that sends output to a VGA and runs at 25 Mhz and another which runs my mandelbrot set calculation at a higher frequency. Here is the code I have. ...
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1answer
35 views

FPGA: what is the input of Timing and RTL simulation?

For FPGA design, compilation of the design produces a bitstream. What is the input of the simulation (Timing and RTL)? Is it the bitstream itself? Another file? For Altera specifically, what are ...
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38 views

Do I have to create generated clocks in the top level module?

I have been working on a module to send VGA output from my fpga. I want to generate the 25 MHz clock inside of the vga module. vga_clk_gen is from the clocking wizzard IP in vivado. I get the ...
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1answer
56 views

FPGA: Bitstream vs. SRAM Object File

What is the difference between bitstream and SRAM Object File? I understand that both are outputs of the FPGA design compilation. It seems to me that the SRAM Object File is what is loaded onto the ...
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2answers
51 views

FPGA Simulation - does it need FPGA hardware?

Reading through Altera documentation on FPGA programming, I can see that the design flow is made of Design -> Compilation -> Simulation -> Programmation -> HW Verification The design consists of ...
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1answer
45 views

FPGA VGA driver not working

I am not really sure what is wrong with my code bellow for a vga. All I want the program to do is display a solid color on the monitor. I want to use the switches on my card to change the color ...
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2answers
60 views

Reading image, sound, binary file from nonvolatile memory for FPGA

For applications that require design on FPGA which shall make use of several image files, sound files or other forms of files, can they be simply included in the FPGA design configuration file? In any ...