A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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28 views
How to simulate an external piece of hardware during the development of a LabView FPGA project
I am working on a PXI system from National Instruments. It has an FPGA card that I have connected externally to a sensor.
I would like to know how to perform a "cycle accurate" simulation that ...
1
vote
3answers
151 views
What components can an FPGA replace/emulate?
I've been under the impression that FPGAs were merely, well, field-programmable gate arrays, but I've seen some example schematics with resistors, capacitors, and such in them. As such, can an FPGA ...
3
votes
4answers
89 views
fpga clock strategy
I have a current design where the input clock is 54MHz, but for some part of the design, I can do with a much slower clock.
Is it better design to clock all the "slow" logic (state-machines ect.) ...
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0answers
48 views
IIR filterbank using fpga? [closed]
how to design IIR filterbank using FPGA but by using specifications of IEEE 802.11 wireless LAN systems standard ??
3
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1answer
58 views
Free linting tool for Verilog
Is there an opensource linting tool for Verilog. I've seen HDL companion and other but they all come with a price tag.
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3answers
70 views
Xilinx Virtex 6 - assigning pins FPGA [closed]
I am writing a basic logic program to a Virtex 6. It is a simple half adder with two inputs (A,B) and two outputs (Signal, Carryout). I would like to assign A, B to two switches and Signal, Carryout ...
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0answers
44 views
OFDM system design [closed]
I am master student from Iraq.I ask about how write program in VHDL to design FIR and IIR filterbank in ofdm system. I try to understand but I cannot,can any one help me in my thesis (FPGA based OFDM ...
2
votes
1answer
56 views
ZPUino soft processor
I was going through http://papilio.cc/index.php?n=Papilio.Hardware and realized that they mention ZPUino Soft Processor but I am unsure of what this is exactly. I ...
0
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1answer
55 views
Xilinx Virtex 6 FPGA - how to read memory
I am new to FPGAs. I would like to learn how I should go about reading the memory (DDR3) of the Xilinx Virtex-6 FPGA ML605 kit.
I would also like to learn how to write simple schematics to the FPGA. ...
1
vote
0answers
19 views
Creating a vivado_hls project with systemc sources
I just started using Vivado HLS. When creating a project, I have to specify a top function, but the top module of my project doesn't have functions, just the constructor. I've tried setting different ...
-2
votes
0answers
47 views
How would one make a USB 3.0 Camera work with an FPGA, what is required? [closed]
How can a USB 3.0 camera be made to work with an Altera FPGA? What are all the ingridients and possible routes that one can take to make such a camera work with an FPGA so that the FPGA can read the ...
2
votes
2answers
79 views
FIFO wrfull asserted when FIFO is not full
I have an issue with Altera FIFOs. It seems that the full signal wrfull gets asserted even when the FIFO is not full. My FIFOs are of size 8. The SignalTap traces ...
1
vote
1answer
62 views
FPGA Internal timing/ timing constraint
When I connect several vhdl components to create one design, how do I ensure that the fpga's internal (ex. register to register) setup and hold timing is not violated?
Ex. Data bus between components ...
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votes
1answer
83 views
Generate sine wave in VHDL, with the use of 10-bits DAC [closed]
I want to generate a sine wave with 20Mhz frequency, using a FPGA (Cyclone 3 EP3C10E) and an external 10bit DAC converter (http://www.analog.com/static/imported-files/data_sheets/AD7533.pdf).
I have ...
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votes
0answers
108 views
What are all the chip-chip protocols that exist? [closed]
Ok, so we have SPI and I2C that can be used for low data rates. What if someone has lets say FPGAs with transceivers and wants to achieve high rate chip-chip data transmission? I know SerialLite and ...
0
votes
2answers
93 views
How DDR2 SDRAM works?
I have the Xilinx Spartan-3AN Starter Kit and I need to use the on board DDR2 SDRAM (MT47H32M16CC-XX). Until now I only used Static RAM and this type of memory is new for me. Can someone explain me ...
0
votes
2answers
104 views
Interfacing a MCP23S17 (SPI) with a FPGA
I am working with a MCP23S17 SPI I/O expander chip in a VHDL project on my Basys 2.
At first glance I thought this was just a simple SPI interface where I put the chip select low and it will give me ...
2
votes
1answer
39 views
ModelSim Altera: simulating the “lpm_add_sub” module?
I'm trying to simulate a verilog module that uses the "lpm_add_sub" module to provide an adder with a separate carry in (for some reason Quartus II doesn't recognise that ...
5
votes
2answers
185 views
Why are multipliers 18x18 Bit in FPGAs?
I'm looking at different FPGAs for my dissertation project and I keep seeing that the multiplier blocks are 18x18 bit, why is this? Why are they not 16-bit?
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votes
1answer
104 views
What is a “santa cruz interface”, who created it? [closed]
There is HSMC that I have seen, but Santa Cruz just looks like regular pin header. What is so special about it? And why is the word Santa part of the name?
0
votes
1answer
161 views
VHDL - Convert from binary/integer to BCD and display it on the 7-segment display
As part of my project for the Digital System Design course I have to use a component to display on the 7-segment display a INTEGER range 0 to 9999 (or a std_logic_vector(13 downto 0)). I used the ...
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0answers
58 views
Recommendations for an FPGA that meet the listed criteria [closed]
I am looking for an FPGA + dev board that will meet the following specifications.
As I know too little of the market, I am seeking your advice for a system meet the following specifications.
Must be ...
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0answers
45 views
Can someone give me a DDR3 RAM for Dummy(ies) FPGA designers type of resource? [closed]
I want to understand how DDR3 RAM is used with a FPGA. Basically I want to know what ALL the signals on the interface do and what is required to read/write the data.
4
votes
8answers
436 views
Likely places to look to find cheap sources of FPGA? Which devices should I open first?
I have a large group of new and old devices and I would like to find a FPGA to start poking around on. What products or types will be likely to have FPGAs in them?
I recently asked this question on ...
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0answers
58 views
FPGA Board : Indirect SPI not working
I was able to make my own custom FPGA shield for an ARM Cortex M3 board (arduino footprint ofcourse!). I used the PapilioOne as reference for basic board design. There is no FT2232 on the board.
I ...
3
votes
3answers
270 views
ASIC vs ? — Performance & Cost
I'm interested in creating a custom linux based solution that will crunch sha256 cryptographic algorithms at insane levels of speed. I'm also on a limited budget... I have no background in EE but I ...
1
vote
2answers
55 views
Parameterized net width in Verilog
Is something like this possible ?
parameter width;
wire[width-1] a_net = (width)'b0;
I basically need a variable to control the width of the right hand side. I ...
2
votes
3answers
120 views
Fix Conflicting IO Standards
I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD.
You can find all of the IOSTANDARD's available for Spartan-3E in this ...
4
votes
3answers
101 views
FPGA Logic Gate Count
I found an FPGA board that I liked. It uses a Xilinx Spartan 6 LX45. When I went to the datasheet for the Spartan 6 series, it only said that there were 43,661 logic cells. How many gates does that ...
2
votes
3answers
98 views
How can I figure out an unknown UART's speed?
So I have a piece of hardware I'm reverse engineering. I believe I've found a UART on the board. I have an FPGA connected to it that just does:
...
1
vote
2answers
68 views
what is a transceiver reconfiguration controller on FPGA
I have come across this on an (Altera) FPGAs that make use of high speed protocols but don't know what it does.
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votes
0answers
34 views
Does anyone know of a good starting point for learning about Spartan 6 LX45 boards? [closed]
I have no idea how or what I can do with this FPGA, but I want to learn. I have a background on some digital logic and I'm working on Verilog now, but I was wondering if anyone had knew of a good ...
0
votes
3answers
91 views
Synchronizing SPI ports for higher data rate
I am designing a new board which uses the NXP LPC4330 (Cortex M4 microcontroller) with a XESS Xula2 FPGA development board. In this design, the Xula 2 has limited I/O pins since it is designed to fit ...
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votes
0answers
67 views
Applications with kernels that can be accelerated in hardware [closed]
Could you give me a list of applications with kernels that can be accelerated in hardware?
Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others.
To ...
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votes
0answers
85 views
Microcontroller, ARM, and FPGA [closed]
I'm going to study Wireless Sensor Network. I'm looking for a good way for understanding micro-controller, ARM and FPGA: i mean books, free technical materials available on the web, like university ...
2
votes
1answer
150 views
How exactly do all FPGAs work together on this board to carry out high speed calculations
The board I am referring to is called "Merrick 3" from "Enterpoint (ltd)". The web page can be found here: http://enterpoint.co.uk/products/asic-development-high-performance-computing/merrick-3/
I ...
3
votes
1answer
200 views
Working with FTDI library for accessing FPGA memory
I asked a related question here.
The board is Lattice MACHX02 1200 ZE.
I am using FTDI Library FTCSPI to access Lattice FPGA UFM through FTDI chip FT2232H. I configured the FPGA in SPI slave by using ...
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votes
1answer
26 views
PCI with EP2C8Q208 testbench? [closed]
Does anyone of you have experience on testbench for PCI on Quartus ?
Any links or knowledges will be very appreciated,
thank you
0
votes
0answers
27 views
Error in Diamond 2.0: Device#1 LCMXO2-1200ZE: Failed to verify the ID (Expected: 0x012B2043 Read: 0x012B2040)
I followed the instructions for running Blinking LED VHDL code on MACHX02 1200-ZE.
Every thing goes fine without any error till I got tools->programer and then click "program" tab to dump .xcf file ...
2
votes
2answers
170 views
RTL vs HDL? Whats the difference
What is the main difference between RTL and HDL? To be honest I searched / googled it yet people are divided in their opinions. I remember one saying that HDL is the computer language used to describe ...
2
votes
1answer
79 views
How do I buffer a high Frequency clock on a Spartan 6?
I am trying to create a high speed clock on my Spartan 6 Atlys Board. The onboard clonck is 100MHz. I am trying to use an on chip PLL to get a faster clock. I am using a the clocking wizard IP to ...
2
votes
1answer
79 views
JTAG Design for altera cyclone 3
I am designing the JTAG for a Altera Cyclone 3 (EP3C5E144C8N). I was only aiming at normal JTAG, and do not need Active Serial. I have attached the schematic and board in the *.zip file ...
0
votes
0answers
103 views
SPI interfacing between FTDI and Lattice FPGA
I am trying to establish SPI interface between FTDI FT2232H and Lattice MachX02-1200ZE.
The following code for this purpose compiles successfully and the last SPI_ReadHiSpeedDevice() function returns ...
6
votes
1answer
126 views
Does an SD card in SPI mode respect chip select/slave select? Seems to be resetting in my application
I have an application where I have a microcontroller (NXP LPC1343) which is connected to an FPGA via 16-bit SPI. There is also an SD card using the same SPI port (MISO/MOSI) but with a different CS/SS ...
0
votes
0answers
60 views
OpenCL for Altera FPGAs
Recently I have been quite interested in OpenCL of the Khronos Group, and already gained some experiences with the language. I'm excited to know that OpenCL now works with Altera FPGA.
...
2
votes
4answers
144 views
Most efficient way to select between 10 large buses?
I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so?
Currently I have the following SystemVerilog implementation
...
0
votes
2answers
50 views
Power supply from PCI connector pin B25 or B5
Can I use pin B25 on PCI connector on my motherboard as a power supply or
I need to use pin B5 and B6 (5V) from PCI connector on motherboard and regulate it with AM1117 3.3V for my PCI board ?
I need ...
4
votes
3answers
277 views
Minimizing Logic in a Spartan-6 for a Game of Life Cell
While trying to learn FPGA programming, I've decided to implement a massively parallel game of life. Here's my first attempt:
...
2
votes
1answer
66 views
In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?
I'm writing some verilog and simulating it using modelsim. I have a block that looks like this:
...
-7
votes
1answer
55 views
3-phase lock loop in verilog
I want to implement a phase lock loop in verilog hdl. The input is the source voltage (which is a sine wave) and the output is theta(in terms of sin and cos).
