A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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What is bit-true implementation

What is bit-true implementation (with an example if possible)? I was reading a paper and it was stated "a bit-true implementation of the algorithm on a FPGA was performed." So what exactly is ...
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22 views

Clock source for Xilinx ML605 and ADC

I have modified a reference design (xapp1071) by Xilinx to interface an ADC (ADS6424 eval board) with an ML605 over an FMC connector. My question relates to how the design and the ADC evaluation board ...
4
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2answers
268 views

Reading the program off a FPGA

Suppose I have some sensitive proprietary software (VHDL/Verilog) on an FPGA connected to my server so I can control it by SSH. Now suppose an attacker compromises my server and can communicate with ...
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1answer
37 views

fpga verilog dual access

I need to write to a register from 2 sources.. in this case, a pci host and a microcontroller. The 2 will never access the register at the same time (basically once the PCI is done , it hands it ...
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0answers
64 views

Selfbuilt USB-JTAG programmer for FPGA's [on hold]

I want to program an FPGA (XILINX Spartan III), with USB port of my laptop, and I want to design the programming circuit myself (not using the XILINX's cable). So, I want to build a USB-JTAG ...
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6answers
1k views

How does a non-FPGA (ie a PC with a CPU, RAM, hard drive) mimic logic gates?

I know that an FPGA uses look-up tables (LUTs) to synthesize logic gates. A LUT is a block of RAM that is indexed by a number of inputs. The output is the value stored at that memory address. The ...
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1answer
26 views

Generating a desired pulse train in Xilinx ISE software

Need some help with VHDL and FPGA since I am new to it. I have a Virtex-4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will ...
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1answer
117 views

Is 'IF' statement necessary for the clock process?

I'm used to writing the following process that will react on the rising edge of the CLK (script 1): ...
3
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1answer
218 views

having distorted image in VGA with FPGA board

I'm using spartan 3E-100 CP132 fpga board to display a basic plus image on a monitor. I have tried using 800x600 72 hz and 640x480 60 Hz but I always get a distorted vertical lines. Is it because the ...
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1answer
29 views

Problem simulating FSM in Quartus II Simulator

I am trying to simulate a FSM using vector simulator... the state machine variable is called "Tstep_Q", I added it to waveform editor... however, when I start the functional simulation all signals are ...
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1answer
28 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
2
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1answer
41 views

USB mouse with a PS/2 adapter for FPGA PS/2 interface

I'm designing a PS/2 mouse interface for BASYS 2 FPGA board. As you might know to communicate with a PS/2 mouse you need a protocol, so if I write my VHDL program for the PS/2 protocol and then ...
0
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1answer
113 views

generating 40 mhz clock from 50 MHz

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
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1answer
33 views

generating 40 MHz clock from 50 MHz in VHDL [duplicate]

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
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0answers
44 views

Read and write FPGA registers via USB or Ethernet

I'm working on an FPGA project on an Atlys Spartan 6 board. I'm programming it in VHDL. I have two 32 bit registers, one for output, the other for input. I need to be able to, respectively, read and ...
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4answers
154 views

High speed memory interface between 2 FPGAs (Virtex 6)

I have a board with 2 Virtex 6 FPGAs, which are connected to each other through 64 parallel IO lines that can operate up to 400 MHz. One FPGA, let's call it B, also has 2 GB of DDR3 memory connected ...
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1answer
96 views

What is the easiest way to transmit data from a computer to an FPGA?

I have never programmed for a physical interface before. This is the board I am currently using, although I do have access to most of the DE boards on the list. I need to continuously transmit 3 ...
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0answers
44 views

Routing errors when trying to implement PLL onto Spartan-6 FPGA board

I am attempting to synthesize and implement the reference design that is linked to in the 'Reference Design Additional Information' section of the following document. I get the following error ...
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1answer
58 views

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA. ...
1
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1answer
64 views

What is format of output data of a webcam?

I'm in the situation of turning a Spatran3 FPGA into a classic USB webcam (Yes it's weird I know). I have a thermal analog camera which is connected to a SAA7113H ADC. I need to interface USB port of ...
0
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0answers
39 views

windows can't recognize my lattice machxo2 board

I purchased a MACHXO2 - 1200ze evaluation board a few days ago. I started with designing and programming simple projects as blinking leds, which worked perfectly. After that at the same day I tried ...
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2answers
59 views

Serialize bits from input/output pin with VHDL

The code below reads 40 bits of data sent in serial from a DHT-11 temperature/humidity sensor and stores the data in a 5 byte array of RAM. The code is: ...
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2answers
52 views

What is the jitter of an asynchronous FIFO?

I have an asynchronous FIFO (in a Stratix V FPGA) with two asynchronous read and write clocks of the same frequency of 100 MHz. As I understand, asynchronous FIFOs have a two-register ...
3
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1answer
111 views

What are retimers?

I am working with a low latency 10G MAC IP core for a Stratix V FPGA. One of the parameters is "High performance mode". The documentation states When enabled, high performance mode enables all ...
5
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2answers
526 views

How to minimize the size a microcontroller implemented on an FPGA?

I have 1500 lines of 16-bit data that need processing. I designed a microcontroller to execute some data processing algorithm on the dataset. It does well when the number of lines is small (< 100), ...
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2answers
82 views

Short ISE FPGA Workflow Tutorial

I'd be much obliged if somebody could point me to a short ISE workflow tutorial that shows how to implement a simple circuit using VHDL. As indicated, the tutorial should be short as I'm not ...
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3answers
68 views

To Remove Debounce from MicroJoystick installed on LogicStart MegaWing (FPGA) and read input correctly

I am working on an FPGA board and coding in Verilog. I am trying to use the MicroJoystick installed on LogicStartMegaWing, the shield with Papilio-One 500k (my FPGA board). I have to do simple tasks ...
5
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4answers
548 views

What is a ripple clock?

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1 Volume 1: Design and Synthesis which states (p. 8): Ripple counters use cascaded registers, in which ...
9
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2answers
372 views

PIC programming through FPGA

I would like to know if there is a way to program a PIC for the first time (write in Flash) through an FPGA card. The PIC is already soldered to the FPGA and I can't remove it. No bootloader exists ...
2
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0answers
45 views

Troubleshooting audio output on Nexys 2 (FPGA)

I've recently purchased the PMOD AMP1 module from digilent for use with my Nexys 2. When I program the demo project and plug headphones or speakers on the headphone output I can hear a barely ...
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1answer
161 views

3D Rotation Using Fixed Point Arithmetic - Rotating Object is Deforming (and Shrinking)

I have an FPGA board (Virtex 5) for which I have created a Wireframe GPU with the ability to rotate a sample object using a 3 Axis Trackball. Additionally, I have connected the board to a PC Monitor. ...
2
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2answers
109 views

How to obtain the (estimate) equivalent gate count for a FPGA design?

I understand that gate count is not a measure for FPGA designs as it is in ASIC world. However, I have to compare the structural efficiency of two designs, one in FPGA and the other one in ASIC, by ...
2
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2answers
218 views

Create breakout for small FPGA in BGA package

I'm going to buy a MachXO3 FPGA by Lattice, famous for the low cost, in order to create a bridge between an HDMI input and a MIPI DSI output for low cost/high res display. Lattice lets you buy only ...
2
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2answers
85 views

problem while simulating a 12 bit counter using 3x 4bit counters ic:74163

I have attached a circuit which includes 3 counters which are the ic 74163. This specific ic is a 4 bit counter. I want to make a bigger counter which will be able to count 752 steps with an input ...
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2answers
72 views

Access to Quartus II beta

My FPGA card (a BittWare card, datasheet available here) comes with example designs which require Quartus II 14 (beta). I cannot find where the beta versions of Quartus II can be downloaded from the ...
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1answer
62 views

Field programmable analog array

I know and use FPGAs quite a lot between my microcontroller and external interfaces and learned to value the flexibility of this setup. Now I am wondering whether such a thing exists for the analogue ...
2
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1answer
77 views

Computational complexity of current netlist matching algorithms

I understand that the problem of matching two netlists could be reduced to the graph isomorphism problem which is NP-intermediate. Apart from that what are the complexity results of some of the ...
0
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2answers
147 views

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

I am writing a VGA driver program in Verilog on a Spartan 3E (FPGA board Papilio one- 500k bundled with LogicStart MegaWIng). The frequency of the internal clock of Spartan 3E is 32MHz. But I need to ...
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0answers
40 views

using the clock of FPGA in system generator

I have designed a circuit in system generator. I am using a FIFO at the output. I want to connect the we pin of FIFO to the clock of FPGA, but I do not know how should I do it in System Generator. In ...
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1answer
52 views

An error in using FIFO block in system generator

I have designed a circuit in System Generator. I want to put a FIFO at the output before out gateway as shown in the below picture When I run it I face to the following error I should connect ...
1
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0answers
96 views

Input pins in top module unconnected

I have a problem connecting different modules in a top module. I want to do a very simple PWM using a counter and a comparator. Counter: ...
0
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1answer
51 views

Adding trigger functionality in for FPGA in ADC capture board

I'm using the LM97600RB board from Texas Instruments to capture data signals and this board contains an ADC as well as a Virtex-5 FPGA. I'm trying to add a trigger functionality to the board using an ...
5
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2answers
48 views

FPGA able to send data, but unable to receive data. (UART - RS232)

I have a DE0-nano FPGA board and I am trying to establish a serial connection with my PC. I am using the RS232 implementation from here: http://www.fpga4fun.com/SerialInterface.html I have tested ...
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0answers
53 views

Learning FPGA Design (Books, Resources, VHDL/Verilog) [closed]

I used to use FPGA's back in college and I really enjoyed it. Years have passed though and I haven't had much time to play with it since then. I have realized I have forgotten some stuff (quite a bit ...
2
votes
2answers
63 views

VHDL: Looping through a module asynchronously

I have a VHDL module that applies a shuffle algorithm to a 64 bit input and outputs the 64bit result. I need to loop this output back through the module exactly 4 times, i was wondering if there was ...
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0answers
24 views

Eagle: IC package variant, different pins bonded out

I'm trying to create an Eagle component for the Altera EP4CE22, which comes in BGA and SMD packages, where different pins are actually available on the outside of the package. Is it possible to reuse ...
2
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1answer
67 views

Eagle: Pins on FPGA exchangeable, depending on configuration

I'm trying to do the PCB design, using Eagle, for a small board with an FPGA that basically just routes the I/O lines to the outside. So, for the purpose of routing this board, the pins are basically ...
6
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4answers
1k views

How to double my clock's frequency using digital design

I am trying to double my clock's frequency using only gates, flip flops or whatever but unfortunately I get a signal of which the duty cycle is far from 50%. Unfortunately I have to develop my system ...
0
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1answer
96 views

Put a DAC at the output of FPGA

I have designed a circuit by System Generator to implement on FPGA. The output signal is a sinusoidal with changeable frequency. I need to read the output signal by oscilloscope. I should put a DAC at ...
0
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0answers
68 views

Where is the pixel data in xilinx AXI_video DMA IP ? to apply a sobel filter on that data

I want to read/write some data in streaming mode from/to memory using AXI video DMA. It has two signals M_MM2S and S_S2MM (memory to axi stream and axi stream to memory) which probably contains the ...