A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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Where is the variable stored?

I at the moment programming on a Zybo board, which has a Zynq chip on it, which tightly integrates a dual arm processore with an FPGA. I an on the Arm implemented a game which stores the game image ...
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76 views

Executing an long equation in one clock cycle

I am using DE2-115 Board for doing traversal in a forest data structure in 50 MHz frequency. Multiple trees have been stored in on-chip ROM, now I need to set the address which can point to a certain ...
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0answers
23 views

QPSK modulation circuit? [on hold]

Does anyone know how to implement a QPSK modulation ? there is a schematic or a FPGA code , or something like that? please help.
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4answers
94 views

Interfacing Analog signal to FPGA?

Okey, let's try this again. The board I am working with is the Smartfusion2 (M2S010-FG484 package) Starter Kit. Link-> here. My main question is If I can interface an analog signal to a pin of the ...
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1answer
27 views

How to save data in Spartan 3E? [on hold]

I did convert an audio file to hex file now i need to store this on board.please help me in this case.
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0answers
45 views

FPGA/CPLD with internal A/D converters [on hold]

Do any programmable logic devices exist that have ADC's on them? I know this can be done through an external device, but micro controllers ADC's on them, so do any programmable logic devices? Note: ...
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32 views

Sequential power circuit for 18 servos

I'm trying to design a servo control board to be a daughter card for DE0-NANO, but run into a problem where all the servos (18 for hexapod) get to the end position on power up. The initial idea was to ...
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2answers
25 views

Altera Cyclone IV FPGA and jtag debugging

G'day All, Is there a method comparable to jtag debugging on a microcontroller (ATMEGA32) for the Cyclone IV family of FPGA? I am trying to debug my Verilog code so ideally I just want to be able to ...
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0answers
28 views

How to determine the maximum current draw from an FPGA? [closed]

I'm thinking of using an Enclustra Mars module which contains a Xilinx Artix-7 FPGA. I'm not sure how to determine the power requirements for the SO-DIMM socket this device will plug into (when ...
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0answers
32 views

High pass filter in verilog [closed]

I need to implement a high pass filter for FPGA. Lets say pass 10Khz. Clock sample 40mhz How can i implement this?
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1answer
26 views

Altera Quartus. Technology Map Viewer looks different from expected

Recently, I've installed Altera Quartus 15.1 and now follow the "getting started" instructions, you can read it here. At the step: to see the resulting circuit go to Tools →Netlist Viewers →Technology ...
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54 views

Why does the 2-digit counter count the wrong number?

I am quite new to fpga and quartus II and I am working with the schematic design. I have designed a 2-digit counter with the circuit shown in the picture and I am testing it in an Altera development ...
2
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2answers
48 views

How do you design a bare-metal Zynq PS-PL system with an accelerator/coprocessor in the PL?

I am new to FPGA development and am trying to build a simple system using the Zynq SoC (on the Zedboard). It will consist of an IP block generated using Vivado HLS which will accept arrays of data, ...
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1answer
35 views

operand isolation in RTL

I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
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3answers
51 views

Linear Rise exponential fall pulse generator

For a neutrino detector related experiment, I need to design a circuit which generates the pulse similar to the detector. This is required to test the front end electronics. Here are my final goals: ...
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0answers
24 views

How to assign pins of Altera Cyclone II to 7 segment?

I am quite new to FPGA and I want to design a 1-digit counter on a 7-segment on an Altera development board. What I have done so far was to schematically design a bcd to 7-segment decoder in Quartus ...
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0answers
17 views

Using TCL (or other Script) file in Quartus to automate circuit creation

I have various simple modules (Verilog) written and included in my Quartus project file. Lets say each such module receives a 8 bit input, increments the value and outputs the new value. Depending ...
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45 views

Xilinx FPGA editor + Relate to Design

I am trying to learn a little more in depth about Xilinx place and route and how everything works. I have made a very simple schematic design and am looking at the result on the board using the FPGA ...
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3answers
96 views

Are there any standard FPGA internal buses?

Are there any standard FPGA internal buses? I've always used some sort of bidirectional bus between my internal blocks, but is there a standard way of doing this?
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33 views

Interfacing a TM4C123 with a Basys3?

I'm trying to build a shell-based real-time OS on a TM4C123 LAUNCHPAD. I already have the kernel and file system done, and I was hoping to add interactivity to this implementation. I was hoping to ...
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1answer
30 views

HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7

I'm working on XAPP495 on Digilent Atlys board with ISE 14.7 I want to run and test "vct_demo" coming with the XAP 495. I tried to compile it (with ISE 14.7) and failed because of the following ...
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1answer
16 views

Is there support XC5VLX110 list in ISE Project setting?

I'm just trying to setup ISE envirmonent. But There's not XC5VLX110 in Device list at the Project Settings in ISE as below picture. What should I do for solving in this situation?
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1answer
69 views

How to establish a communication between FPGA and CPU, in real-time? [closed]

I am working on a project that involves FPGA and CPU communication(in real-time - i.e, CPU and FPGA should function together). I have already designed and tested the UART communication protocol on ...
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0answers
69 views

Lattice MachXO3L: MIPI CSI2 bridge

I would like to design a MIPI CSI2 bridge with a MachXO3L. I leverage the LVDS25 input/output of this FPGA family with the adequate resistors for HS traffic. (I think) I don't care about LP as the ...
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1answer
62 views

Problem with implementation XAPP495 [closed]

I'm working on XAPP495 to show a signal which is throughput of a HDMI signal from my Laptop I do this steps: created a new ISE project added all of the .v files from XAPP495 added dvi_demo.ucf set ...
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1answer
47 views

Why the output signal from the counter seems to be not driven?

I've written a memory module for an application. In order to address each memory location a simple 6-bit counter is used. I have tested most of the components (including the counter) and they seem to ...
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2answers
75 views

Designing a open drain LED driver

Will this open drain LED driver circuit work ? The open drain IO is governed by the following equation 0.5 <= V_LED_OUT <= 3.6 V (abs_max) V_LED_OUT is the voltage from open drain IO pin to ...
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1answer
17 views

Detecting a signal to meet criteria

Not sure if this belongs here. Using FPGA: Lets say I get a trigger input to my system. I want to declare that an edge is part of my signal if I get it every X \$ \mu \$s time. (lets say 1\$ \mu ...
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2answers
169 views

Is anything besides rx and tx actually used in rs232 nowadays?

Whenever I come across a PIC or even a FPGA project that is communicating over the serial port with a PC; only Rx, Tx and power are connected on the 9 pin connector and the other pins/signals are ...
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0answers
19 views

Flashing NIOS II with SPI at boot

I have a Altera FPGA, which is configured (programmed/flashed) at startup by SPI from a processor runing embedded linux. If I put a NIOS processor in the fpga, is it possible to flash the NIOS ...
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2answers
78 views

What the FPGA dev board to choose: Xilinx or Altera? [closed]

I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
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1answer
72 views

VHDL - 10% Duty Cycle

I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%? Thank you. ...
4
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1answer
81 views

Should I use an FPGA output for an MCU Clock?

We are laying out a board that was designed ages ago, the main purpose of the update is for part obsolescence. The board has several PIC uC's on it as well as an FPGA. Each of the PIC's needs a ...
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1answer
26 views

Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
3
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1answer
59 views

Max number of logic units / gates per logic-unit-output wire: FPGA

I couldn't find any info about this. Is there a general rule or does it change for all vendors(altera or xilinx)? Lets assume I have a flip flop and I want to wire 10 flip-flops to its output. ...
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1answer
25 views

Vivado: Block Design sub module

I'm working on a Video processing project with Vivado 2015.2 on a Zynq device. My block design starts to get huge and hard to read. As I have several times the same pipline implemented, I would like ...
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29 views

How to implement a 3D converter software into an external main PCB board as a module?

I am working on a project which requires 2D - 3D conversion directly to screen. So in the system, input is 2D video coming in DisplayPort format and we need to convert it to 3-D(for a given depth ...
0
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1answer
58 views

An overall PWM system by using FPGA [closed]

I need to combine this 3 coding to form one whole PWM system by using FPGA. I tried it, there is no error, but the process is not synthesizable. Please help me. Thank you. This is code for ...
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0answers
44 views

Matlab filter to vhdl

I want to filter a sine wave signal using Altera FPGA(cyclone IV). The sine wave is first converted by an ADC with Fs= 20Mhz, then stored into a register inside the FPGA. The frequency of my signal is ...
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60 views

Memory Interface with a Multiplexed Address/Data Bus

I want to implement a memory interface in VHDL between an FPGA and a processor. The address/data bus is a 16-bit multiplexed bus with an ALE, write protect and BusWait. According to the NVIDIA Tegra 3 ...
4
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3answers
59 views

Where do the mux select lines come from in a CLB?

I am trying to understand the inner workings of a CLB in an FPGA but I can't seem to find out exactly how the routing multiplexers WITHIN the CLB work. Well, I understand how they work and what they ...
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0answers
35 views

lwIP initialization hangs when configuring TEMAC

I am working on a my master thesis, designing an FPGA solution, and have run into a very resilient problem. I will try to provide as much information as possible, in the hopes that someone might have ...
1
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3answers
239 views

Why would you want to write to a file when writing VHDL? [closed]

I have never so far been in the need to write to a file when making a testbench in vhdl. Seeing the signals being plotted has always been enough so far. Could someone please give me a case or the ...
0
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0answers
36 views

CFI flash interface in verilog

I am working on an Intel’s CFI - Flash (28F640J3) interface in verilog. I have written a code and tested it for many commands; read, write, erase. But I am facing problem with 'Write Buffer’ and read ...
0
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2answers
69 views

Simple LED FPGA Circuit

I am new to digital design, and have recently purchased a Bemicro MAX10 FPGA development board to help get my feet wet. I am trying to learn VHDL, and have downloaded a few PDFs to get me started. The ...
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42 views

use of ISD4002 SPI with FPGA

I am trying to build a circuit that would be some kind of INTERCOM and will be controlled by FPGA (cyclon 2 by altera ) . Because I need to have multi voice channels I choose ISD4002 because in my ...
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0answers
19 views

How to view Nios 2 assembly code?

I use the Altera DE2 FPGA that can run my C program. If I want to view the generated assembly, how can I do it? It's usually some flag for gcc and I use Nios 2 IDE ...
3
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1answer
73 views

AM335x FPGA Memory Integration

I'm currently designing a digital mixing console. We have a somewhat large number of ADCs and DACs (more than the multi channel audio serial port on the processor can handle). We decided the solution ...
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2answers
58 views

How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?

How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110? It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
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0answers
16 views

Hardware Co-Simulation using ml605 with ISIM simulator …?

I am trying to do RTL(verilog HDL) and Firmware(System C) Co-Simulation with ISIM Simulator using VIRTEX-6 ML605 FPGA board. I am unable to run co-simulation. I have reffered the document " Hardware ...