A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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TCL command in Libero SOC [Microsemi] to generate the IP cores

Does anybody knows the TCL command to generate the IP cores in a design for the Libero Soc tool of Microsemi (v11.4 SP1)? So the IP core (e.g. a FIFO) is configured and in the design. However, the ...
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2answers
46 views

FPGA power input isolation

I am working on a design that has at least a dozen FPGA's. In the past I have had an FPGA get damaged by a faulty voltage regulator and short out the supply input to ground.Chasing down which FPGA ...
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2answers
60 views

Read decimal value of a 4-bit binary input

I am quite a rookie in the VHDL world, but I seem to have hold of the basics. Atm I am working on a project, which involves me to take a 4-bit binary input (switches), read this value and convert it ...
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3answers
62 views

Spartan 6 DCM unstable clock output

Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a 8x clock based on an input ...
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2answers
69 views

The easiest way to transmit data with clock using an MCU

Assume you have an MCU running at 80Mhz (Currently working with TI M4) This MCU has 128kB of memory allocating some data. What would be the proper way to transmit this data in its raw form (bits ...
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1answer
29 views

Why the port type of this module default to 'var'?

In "IEEE Std 1800-2012 SystemVerilog", p. 668, I find this: module mh11(output integer x); // output var integer x I wonder why it is default to 'var' but not ...
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2answers
34 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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1answer
90 views

Generating pseudo-random numbers with restricted hardware

I have a need to generate a 448-bit value that appears random, for use in a test circuit. The "randomness" of the values is not overly important; the size of the generator hardware is. I am using an ...
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1answer
31 views

reuse Cyclone IV fpga Pasive serial configuration pin for SPI

Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ? This are the dual purpose pin options: if i set "use as Regular I/O" , i ...
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1answer
94 views

Is it technically feasible to design a microchip that won't fail foreign characters? [closed]

I used to work as web developer and did the same part of the project for several decades: Making sure that our Scandinavian characters åäöÅÄÖ... will work. It was feasible and it did work, basically ...
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1answer
49 views

I can't get a meaningful output from a circuit in Thomas & Moorby's exercise 2.7

I'm working out the exercises in "The Verilog Hardware Description Language" to learn Verilog. I'm currently stuck in exercise 2.7, and since I couldn't find anything on the web about it I thought I'd ...
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2answers
88 views

VHDL Plus operator `+` and Downto syntax

Considering variable a and b as STD_LOGIC_VECTOR (31 DOWNTO 0) we have ...
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2answers
56 views

Oscilator with Limited oscillation count

I did implement below oscillator using cascaded not gates. I want to know how can I change such circuit to oscillate only for limited number of oscillations? e.g. I want designed circuit oscillate ...
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5answers
1k views

What are the differences and similarities between FPGA, ASIC and General Microcontrollers?

I have read this post and it does not answer my question in its entirety: I think of a microcontroller as anything that has some memory, registers, and can process a set of instructions such as LOAD, ...
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0answers
27 views

Designing ieee 1394b network guide [closed]

I want to design and implement a firewire network. As I am new to firewire I googled about design guides an manuals but I couldn't find a comprehensive guide. I actually need a practical guide about ...
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1answer
29 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...
2
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1answer
83 views

How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector. If it is on, show Y = SW[15:8], if it is off, ...
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1answer
33 views

Xilinx Virtex 6 Board - ISE gives error [Design Contains no instances]

I'm receiving a "design contains no instances" error but I'm unable to find out the cause of the error despite Googling a lot and trying out the solutions suggested on forums. Below is a report ...
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2answers
146 views

Designing PCB for fast data

I'm trying to connect multiple components (same components) to an FPGA output. The FPGA runs at 30Mhz and transmitting both a clock and data on lines connected to these similar components. Each ...
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1answer
55 views

VHDL process causes errors

I'm new to VHDL so I just have a question to ask about why this produces an error. I have an ALU defined in VHDL: ...
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2answers
57 views

Simulated Annealing Algorithm [closed]

What is the the Simulated Annealing Algorithm used for placement in FPGAs, complete description and in simple words.
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2answers
87 views

What tasks does Graphics hardware perform and what steps does it follow to do so

I am not intending to go into high end GPUs here. That is too advanced. What tasks does a basic graphics hardward perform? By basic perhaps we can go back in time and see what it did in the early days ...
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6answers
2k views

Why implement microcontroller in FPGA?

I am currently "investigating" FPGAs, what they can do, how they do it etc. In more than one place (for example here) I have seen projects that implement a simple microcontroller with FPGA. So my ...
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1answer
84 views

How to use IO Buffer with defined location in VHDL?

I am tring to program the ADF4158 PLL Synthesizer with SPARTAN 6 FPGA using Microboard LX9. I studied VHDL for a semster 4 years earlier, and no practical use after that. So I need some experts ...
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2answers
78 views

Altera DE1-SoC Diagram

In this link is a description of the Altera DE1-SoC kit, and the bottom of the page shows the diagram of the SoC-FPGA chip. It shows some peripherals are connected to the FPGA and other are connected ...
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23 views

Tyring to write data from a Spartan-6 FPGA to an AD5791 20-bit DAC

For some reason my sync pin of the AD5791 on my EVAL-AD5791SDZ board is always high no matter what I do in the FPGA's VHDL code. In fact even when I disconnect the sync pin from the fpga there is ...
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1answer
42 views

xilinx create schematic of top modul with lower level moduls

I have a top modul VHDL source file, which has a few instances of lower-level modules (VHDL) and signals which connects these lower-level modules. How can I generate a schematic for this? I mean, I ...
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2answers
85 views

ADC sampling problem using FPGA

I am trying to sample sinusoid signals using AD7928, which is a 1 MSPS ADC. It is connected to an Altera Cyclone V FPGA, and runs at 20 MHz master clock. Data rate is 1.25 MHz and that's due to the ...
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1answer
77 views

cannot fix: warning signal clk IBUF has no load please help!

I have been trying to design a simple Hardware design to controll another board that powers a set of LEDs for a stage drum lighting system. I cannot for the life of me figure out why I am recieving ...
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1answer
36 views

What is “Configurable clipping rectangles”?

I was going through the features of one Graphics accelerator-IP core. And one important feature of this graphics accelerator is "configurable clipping rectangle". Can any one help me to under stand ...
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1answer
47 views

clk prescaler with possible glitches

I‘m new here and have the following problem. I have developed a module in vhdl which scales the frequency of an input clk by the input prescaling value (0-255) s.t. the frequency of the output signal ...
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1answer
81 views

VHDL code and unintended latches

I am working on coding a Regsiter a1 with input signals b1,rst and wra1 the register ...
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1answer
87 views

Shift Register Vs Multiplexer

I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way. ...
2
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1answer
77 views

VHDL How to Design a Screen (Frame) Buffer

I am trying to use a screen buffer to store, change and output the bits of a video data to the DVI transmit interface. I am using Altera Cyclone III development kit. I will be using 1440x900@60Hz ...
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4answers
576 views

how to properly save an architecture in a fpga ic forever

Considering I made an architecture to do some specific thing, wrote in vhdl, for example. Can I 'burn' it in a fpga chip, forever? Or how should I do it, protecting the intelectual property knowing ...
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1answer
62 views

Using a Counter to Determine next MSB position in polynomial division

I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right When ...
2
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1answer
44 views

Switching tone on and off at 120 bpm not working

I am trying to make a design that toggles a sound at a rate of 120 BPM (once every .5 seconds), and I am using a 50 MHz clock. Here's the tone module: ...
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1answer
107 views

CLK net warning for stopwatch code on FPGA nexys2 board?

I'm coding for a stopwatch which displays 10ths of a second on the rightmost two displays and seconds on the left two displays. The synthesis completes properly but after I make the UCF file and try ...
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0answers
32 views

Video system processing using FPGA. Options [duplicate]

I have to design a PCB where a FPGA, ASIC or SOC will be used and the system has to be able to record the video from a camera and display the live video in a display HD. The camera has a resolution ...
2
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0answers
85 views

How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would ...
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1answer
109 views

ARM Processor or FPGA to video signal processing? [closed]

I want to design a PCB where a video camera will take images and they will be shown in a display HD. So I have several questions in order to achieve it: I would like to know what is the best option ...
0
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1answer
79 views

How to interface 1 MSPS ADC with processing module in FPGA?

I have DE1-SoC board which contains 1 MSPS ADC, I am trying to take samples from ADC and process them. ADC Controller clock is 20 MHz and data is available every 16 clock cycles. The module that takes ...
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2answers
77 views

How do I route many FPGAs in JTAG chain?

I'm designing a chain of Xilinx FPGAs. There are many (e.g 32 or more) devices with short distance (about 10~15 cm) that I want to connect them together in a chain. I'm not sure about TMS and TCK ...
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1answer
57 views

Blocking and Nonblocking statements in same procedural block

Code module block; reg a; reg b = 1'b0; reg c = 1'b1; initial begin c = b; a <= c; end endmodule I simulated the code fragment shown in ...
15
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5answers
2k views

Can FPGA out perform a multi-core PC?

I don't understand how FPGA can be used to accelerate an algorithm. Currently I'm running a time consuming real time algorithm on a quadcore laptop so that four computations can be done in parallel. ...
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1answer
65 views

Can program FPGA but not PROM on my Spartan-3A dev board

I decided to brush the dust off my Xilinx Spartan-3A starter board that I got a while back, and learn to use Verilog. So with the help of Pong Chu's book FPGA Prototyping By Verilog Examples: Xilinx ...
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2answers
113 views

How do FPGA's implement sequential circuits?

I know they implement combinational circuits using LUTs, but LUTs don't have feedback, so I don't see how they can be used for sequential circuits. So how do FPGA's implement sequential circuits? ...
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2answers
83 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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1answer
65 views

Reconfiguration of FPGA in ML605 Board- THe ICAP IS NOT WORKING

The aim of my project is to load 3 bitstreams into the PROM; according to our requirement we load the 1or second or 3 bit file. PROBLEM FACING: THe problem is I'm unable to know whether the ICAP ...
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4answers
100 views

Altera DE2 interfacing with analog sensor

Can Altera GPIO pins read the analog output of a light sensor? The light sensor output is analog and I want the Altera to turn an LED on whenever the signal of the sensor is greater than some specific ...