A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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High Speed Op-Amp recommendation

I am tasked with the issue of driving an IC that wants 5V input signals from an FPGA (3.3V outputs). Now, the most daunting part of it is the slew-rate requirements, with rise time \$t_r = 1.5 ...
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3answers
354 views

Why does my rectangle function on a FPGA look like this?

I programmed my FPGA to create a simple 1 MHz rectangle function. But when I display the resulting function on my oscilloscope it shows some oscillation after the edges. At first I thought this might ...
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78 views

How is a neuromorphic chip different from an FPGA?

So basically they are all programmable, operates in parallel, with small blocks capable of acting like connected state machines. What's the big deal with neuromorphics chips?
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1answer
33 views

How to programm a Lattice board?

I wrote a few lines in VHDL and I declared pins into a lpf file for my Lattice MarchX03 board. But now I want to flash the board and honestly the documentation is very unclear. So I got Diamond ...
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33 views

Mealy Machine and registered outputs and delay increase

I am implementing an absolute value block containing a bit-serial Subtractor, the output connected to an 8-bit shift register which in turn connects to a two's complement block at the output there is ...
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0answers
53 views

How can we compare processing times of two designs implemented on different FPGAs?

How can we compare two different designs that perform same task (e.g. processing a 256x256 image) and both implemented on different FPGAs, in terms of processing time(seconds)? For example one of ...
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36 views

Lattice FPGA - declare pin

I am learning VHDL and I am using the Lattice boards. I want to know how to declare a GPIO. I found the following block of code in the diamond software folder example. It is ".lpf" file and I guess it ...
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1answer
34 views

Trouble running picoblaze code

I am running a simple picoblaze code where I am using two addresses and sending a high strobe on both the addresses, the assembly code has no loop, so technically my code should run ONLY once but the ...
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44 views

Clock Forwarding Won't Work

I am trying to forward a global clock signal to an output pin. I am using a Spartan SP601 evaluation board, LX16CSG324. Refer to the end of this segment of code. I am using a 2.5 V LVDS differential ...
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43 views

NCO synthesis with VHDL

I'm trying to build a function generator with an FPGA. I can generate different waves at different frequencies but the problem is that I have a lot of jitter. I think the problem is the overflow of ...
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32 views

Altera Megafunction generics

I am using the Altera Megafunction LPM_ROM in one of my designs using the block diagram editor in Quartus. I want the ROM to have a configurable initialization file. For example for my component X ...
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79 views

X-Ray tube Current Control based on PWM

I want a control module to be implemented in FPGA(Altera Cyclone IV running on NIOS2) using VHDL which controls current flow to a X-Ray tube. The scenario is I have the expected current value say ...
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2answers
36 views

Spartan-6 LVCMOS33 input pin: can it take 5V without damage?

My Spartan-6 device has an input pin with IOSTANDARD = LVCOMS33 as constraint. If I accidentally or otherwise connect it to a 5 V signal, will the FPGA get damaged? ...
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1answer
44 views

What is Partial Crossbar Interconnection

I have difficulties understanding the concept of Partial Crossbar Interconnection and I could not find any reference on internet to read on. I have the photo below from a lecture slide of many years ...
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1answer
74 views

Simplest way to send data to and from FPGA

I've got a Basys2 board and need to transfer data between the FPGA and my PC(linux, transfer in both directions). It doesn't have to be fast, but it should be easy to implement and not take up to ...
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1answer
93 views

CDC Synchonisation primitives for an Altera FPGA

I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC). There are multiple resources (amongst others) which discuss various architectures for CDC and ...
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18 views

Interfacing with Series Elastic Actuators using Simulink

I'm in a newly founded student team where we are building an exoskeleton to let paraplegic people walk again. As the technical manager I am tasked to analyse the feasibility of tech which allows us to ...
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1answer
68 views

Can I implement a FM Radio Rx on the the Spartan 3E kit?

Can I implement a FM Radio Rx on the the Spartan 3E kit? Starting Problems I am facing- How do I interface the Antenna with the Spartan 3E kit? Implementing the A/D converter.
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1answer
59 views

Spartan 6: How do I use my differential clock?

my SP601 Evaluation Board comes with one 2.5 V LVDS differential 200 MHz Oscillator. Until now, I have only been using the single-ended clock provided with the board. I am having trouble with how to ...
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44 views

Parallel FFT on Xilinx FPGA

I am trying to compute the Fast Fourier Transform (FFT) of 16 parallel input data and therefore, I would like to retrieve 16 output data in parallel. The transform size of my project is N=16. More ...
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1answer
39 views

FPGA Board running

I must work with an FPGA board with a Nios embedded processor, it is APEX 20K200E device I wanted to know : Is this board coming with a kit? I just have the board, a download cable and a power ...
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1answer
69 views

Nonlinear increase in logic utilization for FPGA design

I am creating a design using the Altera Stratix V GX-series FPGA. For host device communication we are using the PCIe x8 interface. The interface itself takes up 3,058 ALMs (out of available ...
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1answer
65 views

Reliability FPGA depending on its number of gates

I am currently working on a little project and the goal is to find a new model for calculating FPGA's reliability. I have been working with the MIL-HDBK-217F+N2, but when it comes to the complexity ...
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How to build an FPGA based video filter? [closed]

I have a computer that outputs a low-resolution (1280x720) image via DisplayPort. I want to take this image and, by programming an FPGA, apply an image processing algorithm that 'upscales' this image ...
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Cheapest FPGA PCIe board for Software Acceleration [closed]

This question is somewhat related to an earlier question: Cheapest FPGA's. I have been searching for a cheap FPGA board with PCI express 2.0 or 3.x support. Such boards can be plugged in one of the ...
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2answers
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For a PLL Clock multiplier, where does the new clock come from?

If I understand it correctly, you use a PLL in an FPGA to get a higher clock from, say, a 50 MHz oscillator by synchronizing the faster clock to the slower reference one. Like if I had a 50MHz crystal ...
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66 views

How to start with replacing a hardware with FPGA/microcontroller? [closed]

I'm currently stuck with how to start with a project I took on. The project is that I emulate the results given by a program when connected to a hardware using the same program and a ...
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2answers
69 views

Crossing a single-cycle spike signal from a fast clock domain to a slower one

I have a 1-bit signal coming from a part of my circuit that is running on a 40 MHz clock. The signal is mostly 0, except it is 1 for a single 40 MHz-cycle every ~million cycles. Another part of my ...
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57 views

How to use simple generated clock in Verilog Code Vivado 2015.2

I am new to FPGAs. I am using an Artix-7 that comes in the Nexys4DDR, and I am programming in Verilog. I want to create a simple D-Flip Flop that will be triggered by a CLK of 50MHz. The CLK in the ...
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2answers
67 views

How to correctly connect a MicroSD card to an FPGA device

I want to ask how to correctly connect a MicroSD card to an FPGA device(not spi version), consider all FPGA pins will be floating for an amount of time before FPGA is configured. I've found a lot of ...
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40 views

What is the easiest/cheapest way to get relative ASIC area estimates from a HDL design?

I've been working on some HDL designs and testing them on an FPGA. I have various possible ways I can go with the design with differing tradeoffs between amount of logic, registers, and width/depth ...
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1answer
69 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
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56 views

J1 CPU problem, for get the variable value, I must read two times

I'm working with the J1 Forth CPU Core (on Digilent Nexys 2). When I use variables, I need to read two times to get the stored value in the variable. For example: ...
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How are FPGA's configured when operating independently?

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
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1answer
222 views

What is the difference between SoC FPGA and 'regular' FPGA?

I've recently developed an interest in implementing projects on top of an FPGA dev board, and wish to purchase one such as the Altera DE1. Looking in the company's site, I noticed there is another ...
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1answer
61 views

Size of DRAM logic designs

I am a beginner with FPGAs and EE in general, so please bear with me! It is my understanding that many modern FPGAs are SRAM-based, and for good reason: SRAM can handle higher clock speeds and has ...
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87 views

FPGA - Data transfer via Ethernet

I have a Verilog module that is able to make my FPGA blink its LEDs at frequencies according to certain variables/constants I've set within the code. However, I would like to change these variables ...
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3answers
378 views

FPGA boards with high clock speeds (hundreds of MHz)?

It appears that most FPGA boards, such as the Mojo and Papilio, have built-in clocks on the order of 50 MHz, even though the FPGA chips themselves can go up to several hundred MHz. However, I ...
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Why won't the Xilinx block RAM in a Spartan-3E consistently return data in a single clock cycle?

I'm creating a design using Verilog on a Xilinx Spartan-3E (XC3S500E) that uses multiple dual-port block RAMs, all instantiated through Verilog primitives such as ...
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Putting Linux on a Lattice ECP3 FPGA

On my Xilinx Zedboard, I booted Linux from an SD card and then ran a Linux application (written in C) from the SD card. This application created a server using sockets that would return whatever is ...
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Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?

I am trying to create a sequential circuit on a development board with a Xilinx Spartan3E XC3S500E in an FT256 package. The board has a 50MHz crystal oscillator connected to pin B8, which is marked as ...
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1answer
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fpga clock muxing

We are using an fpga with limited resources, the IGLOO Nano, so to implement all our functionality, we need to share a FIFO between two different vhdl components, which are using different clocks. The ...
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3answers
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Having trouble implementing a 1Hz blinking light on a Spartan 6 FPGA

I currently have a Spartan-6 FPGA in a Digilent Nexus 3 board. I am using Xilinx 14.6 Project Navigator to write the code and program the FPGA. My code for the top (and only) module is the following: ...
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1answer
42 views

Zedboard Linux Socket Application Error

After creating the linux boot image from the tutorial for the zedboard, I tried creating a socket application to talk to the computer. The Zedboard would be the server and the program in visual studio ...
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44 views

Why can't ISE map the BTNRST pin of the Atlys board?

I want to use the Reset button of Digilent's Atlys board, but ISE can't map the pin because the site type is not an IOB (it's an IOBS, see section 6 of this question). As far as I can see there is no ...
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155 views

FPGA floating pins, when place pull-up/down resistor on Input or Output

I've looked my FPGA datasheet and found that there is no pull-up/down resistors on it's pins(just a pull-up but that need to be enabled). So, when I power up my circuit I've for a "big" amount of time ...
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74 views

Axi DMA correct parameters

I'm making my design with Vivado HLs and Vivado and I'm doing some somewhat big transfers between DDR and my custom IP block and vice-versa. Each transfer from DDR to custom IP is of 256x256x4=262144 ...
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PAR taking too long - Xilinx ISE

I am trying to compile a project and it takes a very long time to route. - ISE 14.3 In my main module, I am using a package where I have declared an array of constants. These constants use functions ...
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Results analysis of the sequential filter and strength-reduced filter in frequency domain

I realized two low-pass filters by Verilog. The filter can be represented as following equation: 1. Sequential filter with 32 stages. For saving the multipliers, I only use one multiplier and do ...
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Does the altera ROM megafunction have a startup delay?

I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...