Tagged Questions

A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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0
votes
2answers
39 views

Fix Conflicting IO Standards

I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD. You can find all of the IOSTANDARD's available for Spartan-3E in this ...
3
votes
2answers
59 views

FPGA Logic Gate Count

I found an FPGA board that I liked. It uses a Xilinx Spartan 6 LX45. When I went to the datasheet for the Spartan 6 series, it only said that there were 43,661 logic cells. How many gates does that ...
2
votes
3answers
86 views

How can I figure out an unknown UART's speed?

So I have a piece of hardware I'm reverse engineering. I believe I've found a UART on the board. I have an FPGA connected to it that just does: ...
1
vote
2answers
57 views

what is a transceiver reconfiguration controller on FPGA

I have come across this on an (Altera) FPGAs that make use of high speed protocols but don't know what it does.
-1
votes
0answers
33 views

Does anyone know of a good starting point for learning about Spartan 6 LX45 boards? [closed]

I have no idea how or what I can do with this FPGA, but I want to learn. I have a background on some digital logic and I'm working on Verilog now, but I was wondering if anyone had knew of a good ...
0
votes
3answers
70 views

Synchronizing SPI ports for higher data rate

I am designing a new board which uses the NXP LPC4330 (Cortex M4 microcontroller) with a XESS Xula2 FPGA development board. In this design, the Xula 2 has limited I/O pins since it is designed to fit ...
-5
votes
0answers
62 views

Applications with kernels that can be accelerated in hardware [closed]

Could you give me a list of applications with kernels that can be accelerated in hardware? Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others. To ...
-3
votes
0answers
75 views

Microcontroller, ARM, and FPGA [closed]

I'm going to study Wireless Sensor Network. I'm looking for a good way for understanding micro-controller, ARM and FPGA: i mean books, free technical materials available on the web, like university ...
2
votes
1answer
135 views

How exactly do all FPGAs work together on this board to carry out high speed calculations

The board I am referring to is called "Merrick 3" from "Enterpoint (ltd)". The web page can be found here: http://enterpoint.co.uk/products/asic-development-high-performance-computing/merrick-3/ I ...
3
votes
1answer
175 views
+100

Working with FTDI library for accessing FPGA memory

I asked a related question here. The board is Lattice MACHX02 1200 ZE. I am using FTDI Library FTCSPI to access Lattice FPGA UFM through FTDI chip FT2232H. I configured the FPGA in SPI slave by using ...
-1
votes
1answer
25 views

PCI with EP2C8Q208 testbench? [closed]

Does anyone of you have experience on testbench for PCI on Quartus ? Any links or knowledges will be very appreciated, thank you
0
votes
0answers
19 views

Error in Diamond 2.0: Device#1 LCMXO2-1200ZE: Failed to verify the ID (Expected: 0x012B2043 Read: 0x012B2040)

I followed the instructions for running Blinking LED VHDL code on MACHX02 1200-ZE. Every thing goes fine without any error till I got tools->programer and then click "program" tab to dump .xcf file ...
2
votes
2answers
143 views

RTL vs HDL? Whats the difference

What is the main difference between RTL and HDL? To be honest I searched / googled it yet people are divided in their opinions. I remember one saying that HDL is the computer language used to describe ...
2
votes
1answer
70 views

How do I buffer a high Frequency clock on a Spartan 6?

I am trying to create a high speed clock on my Spartan 6 Atlys Board. The onboard clonck is 100MHz. I am trying to use an on chip PLL to get a faster clock. I am using a the clocking wizard IP to ...
2
votes
1answer
53 views

JTAG Design for altera cyclone 3

I am designing the JTAG for a Altera Cyclone 3 (EP3C5E144C8N). I was only aiming at normal JTAG, and do not need Active Serial. I have attached the schematic and board in the *.zip file ...
0
votes
0answers
74 views

SPI interfacing between FTDI and Lattice FPGA

I am trying to establish SPI interface between FTDI FT2232H and Lattice MachX02-1200ZE. The following code for this purpose compiles successfully and the last SPI_ReadHiSpeedDevice() function returns ...
6
votes
1answer
97 views

Does an SD card in SPI mode respect chip select/slave select? Seems to be resetting in my application

I have an application where I have a microcontroller (NXP LPC1343) which is connected to an FPGA via 16-bit SPI. There is also an SD card using the same SPI port (MISO/MOSI) but with a different CS/SS ...
-1
votes
0answers
40 views

HD-SDI to SD-SDI

I need to convert a HD-SDI signal to SD-SDI. I have been looking into deserializers and fpga, but have not found a good solution yet. How can this be done? Preferred is a "simple" solution, that ...
0
votes
0answers
48 views

OpenCL for Altera FPGAs

Recently I have been quite interested in OpenCL of the Khronos Group, and already gained some experiences with the language. I'm excited to know that OpenCL now works with Altera FPGA. ...
2
votes
4answers
135 views

Most efficient way to select between 10 large buses?

I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so? Currently I have the following SystemVerilog implementation ...
0
votes
2answers
48 views

Power supply from PCI connector pin B25 or B5

Can I use pin B25 on PCI connector on my motherboard as a power supply or I need to use pin B5 and B6 (5V) from PCI connector on motherboard and regulate it with AM1117 3.3V for my PCI board ? I need ...
4
votes
3answers
259 views

Minimizing Logic in a Spartan-6 for a Game of Life Cell

While trying to learn FPGA programming, I've decided to implement a massively parallel game of life. Here's my first attempt: ...
2
votes
1answer
65 views

In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?

I'm writing some verilog and simulating it using modelsim. I have a block that looks like this: ...
-7
votes
1answer
47 views

3-phase lock loop in verilog

I want to implement a phase lock loop in verilog hdl. The input is the source voltage (which is a sine wave) and the output is theta(in terms of sin and cos).
0
votes
2answers
127 views

Square law device using FPGA

I am trying to implement Square Law Device on Virtex 5 Family FPGA but before burning it to the FPGA I was trying to simulate it in the Xilinx ISE kit. I am not sure whether the code is correct or not ...
-2
votes
1answer
60 views

picking a microcontroller (or FPGA) board OEM [closed]

I am creating a project that would require high speed data communication between PC and my little "black box", so I am looking for a microcontroller or FPGA OEM board (not a single chip to avoid ...
0
votes
4answers
179 views

Design a FPGA based Oscilloscope

I want to design a little oscilloscope that is able to analyze signals up to 1 MHz using a Xilinx FPGA. I want use the VGA interface in order to display the signals. Is it possible obtain a good ...
0
votes
1answer
22 views

What to change when migrating designs from Altera DE2 to DE2-115?

I'm migrating a working design from Altera DE2 to Altera DE2-115 and I'm running into problems. First everything works with DE2 just like mentioned in the exercises doing what is instructed. Now I ...
-1
votes
0answers
63 views

FPGA Development platform for a video splitter with many HDMI outputs?

I am trying to build a video splitter prototype. It is intended to receive a video signal through an HDMI port, split and send it (through HDMI) to an array of displays. I have the idea about the ...
-1
votes
1answer
130 views

Best FPGA to work with [closed]

I want to work on DSP and artificial intelligence for my freshman project, I was thinking on make an FPGA based system, the problem is that I have little experience working with FPGA's; I already know ...
0
votes
1answer
67 views

Digilent Basys 2 using TinyOS-nesC

I wonder if it is possible to use the TinyOS-nesC environment to program a Basys2 card? Digilent has developed a driver for this card under Linux but their technical department says that it utilizes ...
3
votes
3answers
196 views

Oscilloscope noise reduction when measuring IC voltage

I am trying to monitor the voltage of an IC. The supply voltage of the IC is 3.3V and clock frequency is 24MHz. Here are some parameters for the channel used for measuring voltage: vertical scale to ...
1
vote
3answers
90 views

Spartan 6 FPGA IO changes state disregarding design

Hello I have made Spartan 6 board and now I'm trying to get it work, I have successfully managed to get programming of SPI flash working so I can upload bitstreams, but I have problem that some of IO ...
4
votes
1answer
89 views

Triple modular redundancy (TMR) in hardware

I would like to know if there are already ASICs/FPGAs implemented on top triple modular redundancy for fault tolerance/if they themselves implement TMR for fault correction. Any reference to research ...
0
votes
2answers
82 views

Can we run Quartus II on Ubuntu?

I can compile digital components and download them to the boards DE2 and DE2-115 I got. I do it from Windows 7 but I want to enable this on ubuntu while the files from Altera are for Red Hat Linux. ...
5
votes
1answer
131 views

Is there an FPGA based vector graphics card project?

I have been messing around with VGA projects as my latest interest. I have a Xilinx Spartan 3E 250K FPGA, which has just barely too little RAM for a full 640x480 frame buffer. So, I'm looking at ...
0
votes
0answers
59 views

Best camera and processor for High-Speed Stereo Vision [closed]

I'm currently developing a high-speed stereo vision project. So far we've coded all the necessary algorithms and already tested a prototype in matlab (which couldn't get above 30fps). The next step is ...
6
votes
2answers
94 views

process timing on FPGA

I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one ...
-4
votes
0answers
98 views

Ideas for a project combining arduino and FPGA [closed]

I would like some suggestions for my project. I need to implement ARDUINO and FPGA, nothing too complex nothing too easy. Just something Simple! where I can show that I have knowledge of these ...
1
vote
2answers
79 views

How to get MicroBlaze running on Papilio Pro

I am new to the FPGA world, and there seems to be gazzilions of boards and FPGA vendors. I just bought the Papilio Pro, which is based on the Spartan 6 LX9, and although I can already bitstream basic ...
1
vote
1answer
145 views

Improve my “From NAND to Tetris” ALU in VHDL

I'm following the course From NAND to Tetris, but instead of using the author's software, I'm trying to directly program a Spartan 6 FPGA. I'm now solving the ALU exercise, and ended up writing the ...
1
vote
2answers
84 views

Static power of Xilinx FPGA

From the results given by power analyzer, I find that the Xilinx FPGAs always have a high static power consumption no matter what your design is, although it will vary if your design utilize different ...
0
votes
1answer
96 views

VHDL: logical block 'dcm' with type 'DCM_BASE' could not be resolved

I keep getting the following error when I go to implement my design in Xilinx ISE: ...
1
vote
3answers
67 views

Simulating Altera FPGAs with an old version of ModelSim?

I'm hoping to do some development work on Altera FPGAs that will likely be larger than is supported by the free edition of ModelSim. I have an old copy of the full version hanging around (version ...
0
votes
1answer
157 views

hold time violation during FPGA post place and route simulation in modelsim

I am designing a simple encryption circuit on Xilinx Virtex-5 FPGA. I have given the timing constraint in the UCF as below: ...
1
vote
1answer
69 views

Interfacing SJA1000 to Spartan6 FPGA

As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA. The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...
0
votes
3answers
225 views

Vhdl VGA Problem

I'm doing a fpga project in vhdl for my studies. I'm displaying a dog on the screen that I try to move. That works well for right, left and up but trying to make the dog go down, it moves in a ...
0
votes
0answers
85 views

Using the FT232 with FPGA to program SPI Flash

I want to interface my Xilinx FPGA XC3s250E chip with an external SPI based flash. I am looking at indirect programming where-in the FPGA and the Flash are connected to each other and the FPGA is the ...
0
votes
1answer
40 views

Xilinx Xpower Analyzer: Expected scope definition in VCD

I use a VCD file to evaluate the power of my design. The VCD is generated using the following command in the testbench file. ...
0
votes
2answers
106 views

How to implement Serial port RS-232 from 2.5V IO signal?

I am playing with a Xilinx Spartan-3A development (XC3S50A-TQ144C) and then I tried to implement RS-232 serial port by following the guide here: http://www.fpga4fun.com/SerialInterface.html I bought ...

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