A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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Crossing a single-cycle spike signal from a fast clock domain to a slower one

I have a 1-bit signal coming from a part of my circuit that is running on a 40 MHz clock. The signal is mostly 0, except it is 1 for a single 40 MHz-cycle every ~million cycles. Another part of my ...
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29 views

How to use simple generated clock in Verilog Code Vivado 2015.2

I am new to FPGAs. I am using an Artix-7 that comes in the Nexys4DDR, and I am programming in Verilog. I want to create a simple D-Flip Flop that will be triggered by a CLK of 50MHz. The CLK in the ...
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58 views

How to correctly connect a MicroSD card to an FPGA device

I want to ask how to correctly connect a MicroSD card to an FPGA device(not spi version), consider all FPGA pins will be floating for an amount of time before FPGA is configured. I've found a lot of ...
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36 views

What is the easiest/cheapest way to get relative ASIC area estimates from a HDL design?

I've been working on some HDL designs and testing them on an FPGA. I have various possible ways I can go with the design with differing tradeoffs between amount of logic, registers, and width/depth ...
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1answer
57 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
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53 views

J1 CPU problem, for get the variable value, I must read two times

I'm working with the J1 Forth CPU Core (on Digilent Nexys 2). When I use variables, I need to read two times to get the stored value in the variable. For example: ...
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46 views

How are FPGA's configured when operating independently?

I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
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1answer
198 views

What is the difference between SoC FPGA and 'regular' FPGA?

I've recently developed an interest in implementing projects on top of an FPGA dev board, and wish to purchase one such as the Altera DE1. Looking in the company's site, I noticed there is another ...
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1answer
46 views

Size of DRAM logic designs

I am a beginner with FPGAs and EE in general, so please bear with me! It is my understanding that many modern FPGAs are SRAM-based, and for good reason: SRAM can handle higher clock speeds and has ...
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1answer
56 views

FPGA - Data transfer via Ethernet

I have a Verilog module that is able to make my FPGA blink its LEDs at frequencies according to certain variables/constants I've set within the code. However, I would like to change these variables ...
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3answers
353 views

FPGA boards with high clock speeds (hundreds of MHz)?

It appears that most FPGA boards, such as the Mojo and Papilio, have built-in clocks on the order of 50 MHz, even though the FPGA chips themselves can go up to several hundred MHz. However, I ...
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46 views

Why won't the Xilinx block RAM in a Spartan-3E consistently return data in a single clock cycle?

I'm creating a design using Verilog on a Xilinx Spartan-3E (XC3S500E) that uses multiple dual-port block RAMs, all instantiated through Verilog primitives such as ...
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1answer
57 views

Putting Linux on a Lattice ECP3 FPGA

On my Xilinx Zedboard, I booted Linux from an SD card and then ran a Linux application (written in C) from the SD card. This application created a server using sockets that would return whatever is ...
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58 views

Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?

I am trying to create a sequential circuit on a development board with a Xilinx Spartan3E XC3S500E in an FT256 package. The board has a 50MHz crystal oscillator connected to pin B8, which is marked as ...
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95 views

fpga clock muxing

We are using an fpga with limited resources, the IGLOO Nano, so to implement all our functionality, we need to share a FIFO between two different vhdl components, which are using different clocks. The ...
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3answers
71 views

Having trouble implementing a 1Hz blinking light on a Spartan 6 FPGA

I currently have a Spartan-6 FPGA in a Digilent Nexus 3 board. I am using Xilinx 14.6 Project Navigator to write the code and program the FPGA. My code for the top (and only) module is the following: ...
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1answer
37 views

Zedboard Linux Socket Application Error

After creating the linux boot image from the tutorial for the zedboard, I tried creating a socket application to talk to the computer. The Zedboard would be the server and the program in visual studio ...
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36 views

Why can't ISE map the BTNRST pin of the Atlys board?

I want to use the Reset button of Digilent's Atlys board, but ISE can't map the pin because the site type is not an IOB (it's an IOBS, see section 6 of this question). As far as I can see there is no ...
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1answer
76 views

FPGA floating pins, when place pull-up/down resistor on Input or Output

I've looked my FPGA datasheet and found that there is no pull-up/down resistors on it's pins(just a pull-up but that need to be enabled). So, when I power up my circuit I've for a "big" amount of time ...
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1answer
54 views

Axi DMA correct parameters

I'm making my design with Vivado HLs and Vivado and I'm doing some somewhat big transfers between DDR and my custom IP block and vice-versa. Each transfer from DDR to custom IP is of 256x256x4=262144 ...
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1answer
54 views

PAR taking too long - Xilinx ISE

I am trying to compile a project and it takes a very long time to route. - ISE 14.3 In my main module, I am using a package where I have declared an array of constants. These constants use functions ...
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31 views

Results analysis of the sequential filter and strength-reduced filter in frequency domain

I realized two low-pass filters by Verilog. The filter can be represented as following equation: 1. Sequential filter with 32 stages. For saving the multipliers, I only use one multiplier and do ...
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1answer
40 views

Does the altera ROM megafunction have a startup delay?

I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...
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1answer
102 views

Fpga Crossing signals between related clock domains

I have an fpga design with two clocks, one is 54MHz and the other is a divide-by-4 clock of the 54MHz, this is 13.5MHz clock. The 13.5MHz clock is generated by dividing the 54MHz clock in vhdl, and ...
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36 views

Strange outputs in Zedboard (sometimes)

I made a block in Vivado HLS to normalize some 512x512 pixel maps. These maps are read from the SD card into memory (and they are read correctly,I've confirmed) and then they are passed to my Vivado ...
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2answers
77 views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
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2answers
91 views

Why mosfet is preffered over voltage divider for voltage level shifting

Before writing this question I read several similar threads, but didn't found the answer I am looking for. When we need a voltage level shifter the first thing that come to the mind is a voltage ...
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1answer
65 views

Reading and processing 32+ ADC channels at high frequencies

For a project I need to sample 32 or more photoresistors at a time and return an ID and value of the brightest photoresistor over some communication (i2c, serial, etc doesn't really matter to me). I ...
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1answer
37 views

NFC - FPGA - TFT Question [closed]

Im working on an idea but am having a problem finding even a starting point for research. The idea is to have images (video) sent over NFC to a NFC connected to FPGA (or something else could do?) and ...
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39 views

Why use decode stage on pipeline to forward control signals?

In a pipelined processor we use decode stage to decode an instruction and forward the control signals that were found until they are used. Why we don't pipeline the whole instruction and let each ...
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1answer
55 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
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47 views

How can I scan an One-Wire (1-Wire) bus for all connected devices and list their IDs

I have written a One-Wire (1-Wire, OW) controller in VHDL for FPGA designs. Currently I use a USB-OW adapter from Dallas/Maxim on my PC to get the sensors' IDs. I would like to scan the bus directly ...
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1answer
58 views

SMPS control components and technologies

Preface: the switch-mode power supply is a flyback power-factor corrected AC-DC converter. I'm currently using a combination of AVR microcontroller (ATmega64A) with some analog (such as DACs) and ...
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153 views

What's the difference between CPLD and an FPGA? [closed]

What's the difference between a CPLD and an FPGA?
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60 views

Memory scheduling in FPGA

I am trying to design an image processing system on an FPGA to do Canny Edge Detection. The design is shown in the image below. I have a large block ram to store my image. then i have smaller ...
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38 views

Axi DMA maximum velocity and DCache clarification

This is a 2 question in one thread. I'm basing my model on the matrix multiplication example. First set of questions: After some optimizations I have now a MM2S velocity of 1009 Mbytes/s and a S2MM ...
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MatrixMult modification - Xilinx

I was following the example of the matrix multiplications present in here. As my objective is different since I don't need to multiply matrices but only all the elements of the entrance matrix by ...
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22 views

Xilinx ap_axiu parameters

I'm using ap_axiu from ap_axi_sdata.h in Vivado HLS like I saw in some example to stream data throught the AXI DMA. I'm defining my value like this: ...
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2answers
286 views

FPGA Floating-point to Unsigned 32bits

Regarding something I read in a Xilinx manual saying this: Because floating-point operations use considerable resources relative to integer/fixed point operations, the Vivado HLS tool utilizes ...
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73 views

Drive electo-optic modulators with FPGA

I am currently using an FPGA (Virtex II NI RIO7831R) to generate the clock for a pulse generator used to drive a Linbo3 optical phase modulator. ...
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2answers
55 views

Syncronization Flip-flops

I've a doubt about clock domains and synchronization FF. I'm working on a FPGA and I've two clock domains. In the firs clock domain there is a clock frequency of 125 MHz, in the second the frequency ...
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1answer
93 views

UART to Bluetooth

I seem to find only partial explanations regarding this question, I've used Bluetooth in previous projects but I plan to use it on an FPGA project. Currently The FPGA is connecting using a UART ...
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2answers
106 views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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48 views

OR1K on DE0-Nano

I seem to be having difficulty finding much information on implementing the OpenRisc architecture onto the DE0-nano with support for linux. I found one particular article on the official site from an ...
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4answers
105 views

Required subjects to understand FPGAs [closed]

I would like to get into FPGAs. I'm a computer engineer student and I have knowledge of electronic, electromagnetism, circuit, architecture, microcontroller, software development... but I studied them ...
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Power seq. in FPGAs and MCUs

I've a question about Power Seq. requested by FPGA/MCU datasheets. I see always in datasheets that a particular power supply input must reach a voltage level before another power supply input(for ...
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1answer
71 views

Multicycle : Is it possible?

I've to constraints an Lattice Semiconductor FPGA and I've some doubts about the multicycle constraint described here. I've the following RTL : Basically it is a counter that is driven by a rising ...
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1answer
89 views

In a Lattice MachXO2, how can I use the EFB SPI slave and configuration SSPI (multiplexing)?

I am using a Lattice MachXO2 FPGA eval board and Lattice Diamond 3.4.0.80 on Linux. I want to use the configuration SSPI to update the FPGA configuration. During user mode, I want to use the same ...
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1answer
23 views

How to access the selectmap pins (both hardware and software) in Virtex 5 development board?

We are trying to interface a Raspberry Pi with an Virtex 5 dev. board to read the configuration memory. We have decided to use the selectmap protocol and we understand the signals involved and ...
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2answers
52 views

Single input for consecutive state transitions in an FSM: preventing fall-through

Consider the following state diagram where the inputs are c and v. The system is also receiving a high frequency clock ...