A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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Altera TimeQuest SDC I/O constraint with SDRAM - does input delay include output hold time?

I am using a Altera Stratix IV with an ISSI 42x SDRAM device. I'm trying to understand the timing constraints for the data inputs of the FPGA (which is the data output from the SDRAM). According to ...
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20 views

spi slave megafunction in quartus II 14.0

I am tring to add an spi slave megafunction in quartus II 14.0.00 for a Cyclone IV EP4CE22F17C8 altera Fpga. I only need a simple slave functionality to write and read registers.... if i search in ...
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22 views

Is source code compatible between DE2 and DE2-115?

I have 2 FPGAs: Altera DE2 and DE2-115. I was reading that source code is compatible between different computers and different cores. I have written a C program for use with the Micrium ucos rtos with ...
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1answer
64 views

CPU Core frequency [on hold]

I was going through the selection criteria of CPU (MCU/MPU/FPGA) and observed that core frequency is one important parameter while selecting a CPU. But I was unable to get information regarding, how ...
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1answer
61 views

blinking a display using trigger

I've been banging my head over this for a while now, basically I have this display driver that in normal conditions would update a seven segment display continuously. What I would like to do, and I'm ...
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43 views

FPGA to C Variable Transfer [closed]

Is there a way to actively send data to a computer program written in C in order to utilize that data within the program?
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0answers
35 views

ALU vhdl code using fpga [closed]

i need help to design this code. please anyone will do this and send me?? Use VHDL to design a basic 4-bit ALU to carry out the following operations: 1) Addition, 2) Subtraction, 3) 'Comparison' and ...
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1answer
16 views

Why build errors when connecting timers in Quartus ii?

I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g. ...
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1answer
46 views

ise complaining index out of range, but it seems to be in range?

I'm righting a vhdl module that calculates the LPCs from incoming DT samples. My ise editor is complaining that my index is out of range. Is there any reason anyone can see that it should be ...
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1answer
41 views

How to connect WIFI module to FPGA board [closed]

I am working on creating a lunar rover to be controlled over wifi so the rover can be controlled remotely. The rover is controlled using a M1A3PL FPGA board with a Actel ProASIC 3 chip. I am trying to ...
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0answers
22 views

turn on led using external light dependent resistor (LDR) with nios ii and qsys design

I want to use qsys and nios ii to design a system that uses an external ldr to turn on led on an altera fpga.how can i go about this, what are the components i need in my qsys design and how to ...
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0answers
27 views

Upsampling QPSK Symbols in FPGA

I am trying to implement QPSK modulator in FPGA using Verilog. I have a question about upsampling. Assume that I want to send this byte: 1 0 1 1 0 1 0 1 I channel ...
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1answer
88 views

Convert C to FPGA

I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator. Problem is, there are tons of information out there and almost all good programs need an ...
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1answer
24 views

MityDSP and Ephiphany doubts

I've searched the documentation and tutorials about these two families of boards but I have not yet understood something. Both support ANSI-C and they both have FPGAs, so my doubt is: how is one ...
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1answer
24 views

Which is the “write enable” pin of flash memory in Stratix IV GX?

I am trying to use flash memory in Stratix IV GX fpga kit. For that I went through the pin details of the same. But the I was expecting "write enable" which will determine data is to be written to or ...
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3answers
110 views

How can I view, debug, or analyze data being input to my FPGA?

I'm working with a Xilinx Spartan6 on Digilent's Nexys3 board. I've also purchased their PmodMIC so I can try to get some audio data onto my board to perform some signal processing. The ...
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0answers
72 views

7 Segment display driver issues

I have this code for driving a seven segment display for hex. From my understanding its logically correct, but when I try and run it on my Nexsys 3 board I never get the correct output, it seems that ...
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0answers
48 views

Phase delay through LUTs

Hello all, I am trying to double the frequency of an external clock signal by implementing the circuit above in Spartan 6 FPGA. The external clock signal is asynchronous and I sync it with the FPGA ...
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1answer
100 views

Capturing data at 500MHz

I have an ADC sampling at 500MHz (It is collecting data from an Ultrasound sensor). I need to be able to stream this data to my PC (for the time being - this will be done through a wireless unit). I ...
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1answer
83 views

Iris recognition on FPGA

I want to implement iris recognition algorithm on FPGA. before i want to start i want to make sure that fpga is the right choice for image processing. I will use a camera ov7725 to connect to an ...
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5answers
66 views

Digital circuit for adding multiple frequencies

The goal is to implement a kind of a digital piano on an FPGA. Until now, I managed to produce individual notes using counters. Basically, I generate a square wave of a certain frequency, that ...
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0answers
42 views

Setup and hold time violation constraints for Xilinx Fifo generator

I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual. I am using the fifo generator version 9.2 (manual ) to generate a fifo. I would like to ...
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0answers
43 views

Is it possible to encode a mpeg2-ts video with a FPGA linux core?

I need to take an unencrypted HDMI input, buffer that to memory, overlay it if possible, than encode it as mpeg2-ts and output it to an external device. I could do that with a raspberrypi and an ...
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2answers
63 views

other uses of soft core in fpga applications?

I recently got a job dealing with FPGAs. My first project is to modify an old board that uses an FPGA + MCU + Flash setup into something like FPGA (with soft core) + Flash, so we'll have one less ...
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33 views

connecting PC-104+ to laptop [migrated]

I purchased a stereo camera vision system that process the data using an FPGA which uses a PC-104+ interface (typically used by embedded applications) to connect to an embedded computer. I would like ...
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1answer
35 views

Can DE2-115 handle more than 3.3V on its GPIO

In my current project I want to connect some logic to Altera DE2-115 using 40-pin exapnsion header (JP5). Unfortunately, I can't ...
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32 views

FMC fpga connection

I'm trying to conect a FMC150 card to zedboard to get values from adc of FMC card and then pass them trough zedboard to my computer to use that values in Matlab. But now i'm currently stuck, because i ...
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4answers
109 views

What are my options for interfacing **30** incremental encoders to an MCU?

Background: I am familiar with interfacing a few incremental/quadrature encoders to a single MCU chip. My go-to chip STM32F10x can decode 4-5 encoders even in a ...
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1answer
68 views

Interfacing DDS with FPGA

I'm trying to use an FPGA (Altera Deo-Nano) to send data to a DDS (AD9910) using the parallel ports of the DDS. I am using the GPIO headers of the FPGA. I have only connected the parallel input pins ...
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1answer
95 views

frequency doubler on fpga

is it in general possible to implement a frequency doubler completely on FPGA? I saw some implementations on google by delaying the input and XORing it with the original. But they also say that this ...
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1answer
53 views

FPGA - Routing Diagram - what are the physical parts

In Xilinx ISE I've generated a very simple piece of hardware and when looking at the routed design I'm unsure what some of the parts are and require some clarification on what some of these parts are. ...
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2answers
49 views

Using FPGA specific hardware components when writing RTL

I have heard at times that someone writing a digital circuit design may want to use actual primitives present on the FPGA directly in the design. This means including the library which contains those ...
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0answers
47 views

TCL command in Libero SOC [Microsemi] to generate the IP cores

Does anybody knows the TCL command to generate the IP cores in a design for the Libero Soc tool of Microsemi (v11.4 SP1)? So the IP core (e.g. a FIFO) is configured and in the design. However, the ...
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2answers
54 views

FPGA power input isolation

I am working on a design that has at least a dozen FPGA's. In the past I have had an FPGA get damaged by a faulty voltage regulator and short out the supply input to ground.Chasing down which FPGA ...
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2answers
81 views

Read decimal value of a 4-bit binary input

I am quite a rookie in the VHDL world, but I seem to have hold of the basics. Atm I am working on a project, which involves me to take a 4-bit binary input (switches), read this value and convert it ...
2
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3answers
109 views

Spartan 6 DCM unstable clock output

Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a 8x clock based on an input ...
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2answers
77 views

The easiest way to transmit data with clock using an MCU

Assume you have an MCU running at 80Mhz (Currently working with TI M4) This MCU has 128kB of memory allocating some data. What would be the proper way to transmit this data in its raw form (bits ...
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1answer
28 views

clocking on spartan6 FPGAs [duplicate]

Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a divide-by-8 clock based on an ...
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1answer
31 views

Why the port type of this module default to 'var'?

In "IEEE Std 1800-2012 SystemVerilog", p. 668, I find this: module mh11(output integer x); // output var integer x I wonder why it is default to 'var' but not ...
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2answers
54 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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1answer
98 views

Generating pseudo-random numbers with restricted hardware

I have a need to generate a 448-bit value that appears random, for use in a test circuit. The "randomness" of the values is not overly important; the size of the generator hardware is. I am using an ...
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1answer
37 views

reuse Cyclone IV fpga Pasive serial configuration pin for SPI

Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ? This are the dual purpose pin options: if i set "use as Regular I/O" , i ...
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1answer
99 views

Is it technically feasible to design a microchip that won't fail foreign characters? [closed]

I used to work as web developer and did the same part of the project for several decades: Making sure that our Scandinavian characters åäöÅÄÖ... will work. It was feasible and it did work, basically ...
2
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1answer
52 views

I can't get a meaningful output from a circuit in Thomas & Moorby's exercise 2.7

I'm working out the exercises in "The Verilog Hardware Description Language" to learn Verilog. I'm currently stuck in exercise 2.7, and since I couldn't find anything on the web about it I thought I'd ...
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2answers
102 views

VHDL Plus operator `+` and Downto syntax

Considering variable a and b as STD_LOGIC_VECTOR (31 DOWNTO 0) we have ...
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2answers
68 views

Oscilator with Limited oscillation count

I did implement below oscillator using cascaded not gates. I want to know how can I change such circuit to oscillate only for limited number of oscillations? e.g. I want designed circuit oscillate ...
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5answers
1k views

What are the differences and similarities between FPGA, ASIC and General Microcontrollers?

I have read this post and it does not answer my question in its entirety: I think of a microcontroller as anything that has some memory, registers, and can process a set of instructions such as LOAD, ...
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1answer
29 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...
2
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1answer
94 views

How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector. If it is on, show Y = SW[15:8], if it is off, ...
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1answer
71 views

Xilinx Virtex 6 Board - ISE gives error [Design Contains no instances]

I'm receiving a "design contains no instances" error but I'm unable to find out the cause of the error despite Googling a lot and trying out the solutions suggested on forums. Below is a report ...