A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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What could be the usage of material declaration datasheet for Spartan-6 package?

I'm starting to work with FPGAs and CPLDs. like other professional EEs when I bought a Spartan-6 board, started to search in the website of manufacture (that was Xilinx) to find everything about my ...
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35 views

8-point FFT on FPGA using verilog

I have implemented 4-point FFT using xilinx software, for 8-point FFT, we have twiddle factors (1+0j) (0.707-0.707j) (0-1j) (-0.707-0.707j). when i give twiddle factor as 0.707 and simulate it in ...
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30 views

FPGA : Tri-state inout buffer

I have a DE1 Altera Board and I program the FPGA with Quartus software. My goal is to set Vnode (see the scheme) HIGH (3.3 V) when I push a button (KEY[2]) contrariwise when I release the button I ...
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2answers
69 views

Can we simulate FPGA board?

As a part of my curriculum, I am required to implement a project on FPGA. However, even the cheapest available boards are out of my reach (blame currency conversion !) and besides, even if I buy one, ...
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1answer
39 views

VHDL SPI xilinx spartan 3E

I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher. I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. ...
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12 views

Missing a TCL command in Libero

Libero, the IDE to build FPGAs of Microsemi has an TCL interface. But I'm missing a command to regenerated the IP's (e.g. FIFO, ...) in the project. I can't find anything in the documentation. ...
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1answer
27 views

Why has a LUT6 based SRL only 32 entries but not 64?

Xilinx FPGAs are capable of using LUTs as memory elements. The can be used as ROM, RAM and Shift Register (SRL). New Xilinx devices use 6-input LUTs, which gives 64x1 bit for RAMs/ROMs, but only 32 ...
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91 views

Using FPGA to get an image from analog signal [on hold]

I want to get an image from an analog output which is our video output. I tried researching online and I found out that I could use SPARTAN 3 E starter board to convert my data from analog to digital, ...
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0answers
33 views

linking FPGA to PCIe [on hold]

What i ask here might be extremely stupid, but I am very new to the whole thing and am still struggling with the concepts. I have gone through the user guides and googled a lot of things, but can not ...
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0answers
41 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
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42 views

high speed ADC interfacing

now I'm pretty lost , recently I've taken it upon myself to try build an oscilloscope for fun. I want to do it with high speed ADCs (unless anyone knows of a better way?) I'm hoping for about ...
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1answer
45 views

LED1 on SASEBO-W doesn't turn on [closed]

I have a SASEBO-W / 3-94336-3 board for testing side-channel attacks. I followed the steps that is mentioned in the manual for setting jumpers and switches. But after connecting USB cable and JTAG ...
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24 views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
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2answers
37 views

Using a mif file in Quartus

I have created an mif file in Quartus and I am working with cyclone 2 Altera. My query is "How can I use this mif file to initialize a variable in my top level design architecture"? Let me elaborate. ...
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43 views

How to simulate and initialise Block Memory ROM created using Xilinix CORE generator?

I created the ROM correctly using the CORE generator and the correct .coe file. There is supposed to be instruction words inside the memory (32*256). But the data bus out of the memory is always set ...
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2answers
53 views

FCS verification of ethernet frame

i am trying to transmit a Ethernet frame from fpga to pc. my udp frame is: ...
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2answers
50 views

Lattice Diamond gitignore

I am looking for .gitignore file for the Lattice Diamond IDE. I've been trying to only add what I need, but it would be nice to have a .gitignore that just ignores all of the automatically generated ...
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23 views

Setting up T2080 to FPGA PCie DMA

I'm doing an FPGA design using a T2080 MPC interfacing to an Altera Cyclone V FPGA. The goal is to use my FPGA to pump 2 other FPGAs on the same board. I need to create a scheme that allows the ...
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1answer
44 views

How to check output after FPGA Implementation?

I have 10 numbers saved in RAM. I sorted it using Verilog code and saved output in another RAM. I did simulation and it was doing correct sorting. I synthesized it and generate bit file. Now i want ...
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27 views

Resistance or impedance offered by GPIO pins and SMA external clock pin in cyclone 2

I tried connecting a square wave from a signal generator as an external clock through the SMA pin. But I need to know the impedance offered by the SMA pin. What is it and how o find it? Besides the ...
3
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1answer
66 views

Poor clock output from Spartan6 FPGA

I am using the LX9 Microboard from AVNET with the Spartan 6 PFPGA. I implement SPI to read from an ADC (ADS7822). I was getting wrong sampled values. When I ched the signals with an oscilloscope, it ...
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55 views

Communication between FPGA and PC via ethernet [duplicate]

I am trying to establish communication between a PC and an FPGA. I am using Atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip. My frame ...
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1answer
99 views

Xilinx bitgen warning

I am getting a warning in bitgen like: This design is using one or more 9k block RAMs(RAMB8BWER). 9k block RAM data, both user defined and default requires a special bit format. Is it a ...
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2answers
70 views

Finite State Machine in Verilog

So I am trying to make a basic FSM in verilog to turn on 3 different LEDs. I've looked at examples and other people's work, but I can't understand why mine wont work. Maybe someone can help me spot a ...
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1answer
69 views

How is a LUT in an FPGA configured? [duplicate]

I got to understand what a LUT actually is. The inputs of a logic function acts as drivers for address lines of a memory block (typically a RAM block) and the address lines are decoded to point to a ...
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1answer
98 views

Microcontroller and FPGA Manufacturing Process Technology and Size

I'm comparing the power consumption of several microcontrollers, FPGAs and an ASIC I've developed, which all perform the same task. For a fair comparison the current consumption must be scaled due to ...
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3answers
89 views

sine wave in FPGA

I am supposed to generate a sine wave in cyclone 2 altera? I get that I have to store the values in LUT or some memory. I think cyclone 2 uses a 4 input LUT. I am not sure how I should go on with the ...
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2answers
444 views

What is an LUT in FPGA?

I have gone through various sources... But I am not quite sure what it is.I want an and gate and the logical equivalent is two inputs feeding to one gate and for Y=AB' the logical equivalent is ...
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1answer
199 views

1000 Hz+ refresh rate displays/ projectors? (for making volumetric displays)

I have found only few volumetric displays for the kind of effect I'm looking for. They can be divided by two characteristics into two separate groups each: rotating or moving screens, and moving ...
3
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1answer
40 views

FPGA utilization augmentation in a System Generator core when updating from ISE 13.2 to ISE 14.7

I have a huge system generator core originally developed with 13.2 version. Actually we are updating some projects to the latest version of ISE, the 14.7. In the final step we consolidate the project ...
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3answers
85 views

PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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43 views

Verilog->FPGA: Synthesis, Implementation, and Bitstream (Xilinx Vivado)

I'm taking an introductory course in verilog/fpga. Can someone tell me where I can find detailed information on what the 3 processes (synthesis, implementation and bitstream) are doing before I ...
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40 views

How the change the frequency of a clock in Quartus II?

I have a clock in VHDL: ... process(clock) begin if rising_edge(clock) then ... When I check the timequest analyzer, it sets this clock to a default 1 GHz ...
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2answers
73 views

VHDL Block RAM Inference

I am storing a 16k constant sine table of 14 bit signed vectors in a package. I use this package in my module to read out the array in a clocked process But I get this warning during synthesis and ...
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15 views

Program Nexys3 board over USB Host

The Nexys3 FPGA can be programmed with a USB stick formatted in FAT and containing the *.bit file in the root directory. The J8 jumpers must also be in certain position according to the manual. After ...
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1answer
58 views

What type of memory allows for most parallel read/write operations per clock cycle in an FPGA?

If you imagine basic motion detection where you have two frames stored in memory: a previous 640x480 frame and the current 640x480 frame, what type of memory (SRAM, DRAM, SDRAM, DDR SDRAM, etc) would ...
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2answers
158 views

How to control 200 relays with micro controller?

I want to control 200 relays, I want to use AVR controller. Because I am out of pins, I was thinking of connecting the micro controller (for routines and such things) to a FPGA and use the output of ...
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1answer
47 views

Store consecutive UART inputs to register

I have implemented a UART receiver/transmitter (8-bits) in VHDL for use on a Digilent Nexys 3 FPGA. So far I have managed to read inputs in a FIFO, process each byte individually and write the output ...
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2answers
36 views

How to multiply base system clock using .xdc constraints in Vivado

This question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock ...
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3answers
80 views

Datasheet hunting -

I'm having difficulty trying to figure out voltage outputs for FPGAs. Let's use the Xilinx XC3S2000 FG900 as an example, and say I'm trying to figure out the voltage for pin T22. I do a search for the ...
2
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1answer
66 views

Implementing feedback shift registers in a FPGA

I am not up on the latest FPGA capabilities. What would be the lowest cost FPGA chip that can implement 1050 linear feedback shift registers of 71 bits each register? The shift registers have to be ...
2
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1answer
85 views

Why are IPs for FPGAs alwawys so large? [closed]

Why when you synthesise some of the IP provided by the FPGA manufacturers, you end up using huge amount of resources? For example Altera's DDR RAM controller synthesises on 5386 logic units on Cyclone ...
1
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1answer
76 views

getting started fpga video processing? [closed]

Hi i am a electrical engineering student first year since we study only microcontrollers and processors I have decided to learn more about fpga (I have a little experience with spartan 3e vhdl) . My ...
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1answer
21 views

Node assigned to IOBANK

I'm working with an Altera FPGA. In the Pin Planner there is a choice in the combo box for a 1-bit inout node to be connected to an "IOBANK_n" (under "Location" row). I was expecting only "PIN_nn" are ...
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1answer
123 views

What runs a g-shock watch?

I am currently trying to learn more about watches and what it takes to build them. I currently own a watch called the G-Shock 7900b and was wondering what runs it inside. Here is a link to the watch: ...
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3answers
85 views

Do $fopen and $fwrite works with FPGA implementation also?

I used $fopen , $fclose and $ fwrite in my verilog code. It worked with simulation but when i did FPGA implementation it is not working. My question is that these works with FPGA implementation also ...
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3answers
68 views

How to define a clock in Quartus II?

I have this piece of code here: ...
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1answer
44 views

How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

I wrote a code that use RAM (created by Xilinx block generator). It's size is 10X10 (total 100 data) . I used INSTANTIATION as below: ...
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2answers
67 views

FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
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50 views

Read .txt (matrices) from SD to DDR - Zedboard

I'm converting a C algorithm into VHDL with Vivado HLS, and after exporting the RTL into Vivado and completing the design I'm using Xilinx SDK to right in the ARM9 PS. Problem: The algorithm is meant ...