A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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VHDL: Using '*' operator when implementing multipliers in design

Present day FPGAs have built in DSP blocks, the latest FPGAs even have built in IEEE-754 compliant floating point units. It is possible to create DSP entity/module using a GUI after selecting the ...
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61 views

50 MHz FPGA (Cyclone IV @ DE0-Nano) and 60 MHz input from FT2232H

I want to read data from FT2232H used in an FT245 style synchronous FIFO mode (http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf p.27) with DE0-Nano FPGA board: ...
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23 views

W5300 verilog or VHDL driver [on hold]

I would like to have a LAN interface between FPGA board and my PC via this a WIZnet W5300 IC. Could anyone help me write control module or it's state machine in verilog or VHDL?
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2answers
97 views

Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [on hold]

The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates. In the first year of Make Magazine - they describe a person who builds a simple ...
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1answer
25 views

Report entire failing path in Quartus

I am trying to optimize a design that does not meet the constrains. I know that you can use Timequest Timing Analyzer -> Report Top Failing Paths to report the paths that have negative slack but it ...
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39 views

2 Transistor 2:1 MUX with negative waveform

My PTL(Pass transistor logic) 2:1 mux show -ve waveform at at some inputs combination ckt and waveform show below: simulations perform at 180nm tech, 250mhz,1.8v power supply. How to cope this ...
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1answer
61 views

How to protect FPGA from relays?

I'm preparing for a project that will interface an FPGA with many 3v relays on its gpio. Additionally, some of the relays will be powered with the same power supply that the FPGA uses. The FPGA will ...
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29 views

High I/O-pin count fpga evaluation/breakout board [closed]

I need an fpga breakout- or evaluation board with at least 150 I/O pins. This one is not longer available but exact what I'm searching for. Most of the available evaluation boards have max. 100 ...
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47 views

How does the read & write FIFO of the Xilinx work?

I'm having a problem understanding the mechanisms of the read FIFO and write FIFO of Xilinx IP core generator (in the Xilinx platform studio software). I don't understand how the read FIFO sends data ...
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1answer
93 views

How many IP can I fit into an FPGA?

How can I calculate if a certain IP will fit into a certain FPGA? If the unit of measurement of an FPGA size is the LUT, I need that FPGA lut >= core lut For example, can I put a S1 core (37k look up ...
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45 views

Vivado optimizing away my pins

I'm fighting Vivado over what seems like a fairly stupid issue to me. I wrote some Verilog code in ISE (and simulated it). I generated a bitstream in ISE and downloaded it onto the board via impact, ...
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75 views

Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...
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172 views

custom FPGA PCB Design tips

I am planning to design a custom FPGA PCB. the PCB will contain sensors. I need to read the output of the sensors and process them in the processor. I have completed many projects using FPGA's, but ...
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1answer
123 views

counter that MSB toggles every 2 seconds [duplicate]

I want a counter that the Most significant bit toggles every 2 seconds, and gets values 0 and 1.So for example it will have 0 for 2 seconds and after 1 for another 2 seconds etc.. I need it like that ...
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80 views

Explanation of performance graph of FPGA design

After implementing a mathematical function on a FPGA chip. The following graph shows for ~40 inputs the time response, i.e. how long it took to get the output calculated. This data is part of the ...
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2answers
33 views

Altera III Cyclone FPGA input synchronization problem

I have a problem with the asynchronous input signal synchronization. I am trying to make the IIC_Slave based on Cyclone III FPGA Starter Kit. I saw 3 cases: 1) If I not use synchronization ...
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125 views

Bidirectional FPGA implementations (parallel ADC)

New FPGA convert here. I am trying to interface with a parallel ADC as part of a data acquisition project. The pins on the ADC are used for both input and output (not simultaneously). Therefore, I ...
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1answer
45 views

Xilinx Video Timing Controller freezes processor

I'm trying to acquire video from an image sensor using a ZedBoard with Vivado 2014.2 and I used an existing (working) video passthrough project of mine and simply added in a debayer (color filter ...
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34 views

Write in mass storage using File manage and control chip CH376

I tried to create a file in a mass storage device(flash memory)and write some data in it,with fpga using ch376 as a file manager.I tried to do this according to ch376 datasheet but I could not write ...
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87 views

2 Transistor XOR Cell Floating Output Problem

I designed the following 2T XOR cell for my full adder purpose: Theoretically it gives correct output for all input combinations. But on Tanner Eda using 180nm technology 5V supply, it gives logic ...
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2answers
65 views

Strange I2C signals emitted from FPGA

I have a ZedBoard FPGA device and I'm trying to implement an I2C interface to communicate with a camera module. I'm using Vivado 2014.2 and I have added an AXI IIC block to my design with the SCL ...
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96 views

Simulate a simple calculator with FPGA

I'm a beginner in FPGA and I studying some VHDL programming. so for my first project I want to create a simple calculator with keypad and LCD Display and FPGA processor. I know that I must first ...
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62 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
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1answer
72 views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
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FPGA RAM / SRAM in VHDL

Today I ran out of gates on my Xylinx Spartan 3 (Basys2 by Digilent) FPGA. This was not a surprise to me as I had implemented an 8 bit x 2048 array for use as an FIFO buffer. Code: ...
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109 views

FPGA Systems with good Linux support

I am working on a project using a Xylinx FPGA, board produced by Digilent. More precisely, it is the BASYS2. I have been programming the FPGA using Windows 7 as I was unable to install the support ...
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Synchronizing input and output

How do I synchronize this system? The data valid at the input indicates when the data is valid at the input. Similarly the data out valid indicates when the output data is valid. Both ...
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2answers
96 views

How do you set the time resolution in Synplify?

I am generating a 1khz pulse from a 32MHz clock, naturally via a counter. Not a difficult task, so you can imagine my surprise when the result runs at 992Hz... Simulating the behavioural model of ...
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73 views

Outputting a clock signal from an FPGA

Referring to question here: Click here, I'd like to use the 16 channel LED driver to run my 7-segment displays. I'm using a Spartan 6 LX9 FPGA to implement a 16-bit microprocessor that will take care ...
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102 views

Can a barrel shifter be done combinatorially?

I was told that 66b/64b encoding in 10Gb Ethernet (10GBASE-R) requires a one-cycle barrel stage, which adds a necessary one cycle to the theoretical terminal latency. The Wikipedia page on barrel ...
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39 views

Altera Quartus II: FPGA .sof file corrupt all the time

Problem Background: I have a synthesized design using Quartus II 14.0 Output file its in .sof format, to program an Altera Cyclone It works correctly on my computer I can load the file to the FPGA ...
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76 views

VHDL 'buffer' vs. 'out'

I was wondering about the 'buffer' i/o option for entities in the VHDL language. I have found that my code is much cleaner if I use the 'buffer' option instead of 'out' in any circumstance where I ...
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38 views

Configuration an FPGA on installation

I am working on a project using a Virtex-5 FPGA. The small projects that I've worked on with FPGAs has only required me to program the FPGAs on development boards using JTAG or loading the bit file ...
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26 views

Installation of IceCube2 on Linux

I am trying to install the Lattice IceCube2 software on my linux box (i am using Fedora 20 64bit) but i only get the message that the binary installer cannot be executed. Does anyone know how to ...
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1answer
67 views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
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1answer
83 views

How do I reset an FPGA development board to its factory settings?

I have programmed an Altera board in configuration mode so that it runs my program when booted up. Now I want to revert it back to factory configuration. How do I do that?
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69 views

UM232H-B Breakout Module as a parallel port

I want to build something like UM232H-B Breakout Module. This configuration uses an FT232H, to convert usb to serial/parallel. I don't know whether it works with FPGA parallel port programming cable ...
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91 views

What is bit-true implementation

What is bit-true implementation (with an example if possible)? I was reading a paper and it was stated "a bit-true implementation of the algorithm on a FPGA was performed." So what exactly is ...
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314 views

Reading the program off a FPGA

Suppose I have some sensitive proprietary software (VHDL/Verilog) on an FPGA connected to my server so I can control it by SSH. Now suppose an attacker compromises my server and can communicate with ...
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fpga verilog dual access

I need to write to a register from 2 sources.. in this case, a pci host and a microcontroller. The 2 will never access the register at the same time (basically once the PCI is done , it hands it ...
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How does a non-FPGA (ie a PC with a CPU, RAM, hard drive) mimic logic gates?

I know that an FPGA uses look-up tables (LUTs) to synthesize logic gates. A LUT is a block of RAM that is indexed by a number of inputs. The output is the value stored at that memory address. The ...
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33 views

Generating a desired pulse train in Xilinx ISE software

Need some help with VHDL and FPGA since I am new to it. I have a Virtex-4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will ...
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140 views

Is 'IF' statement necessary for the clock process?

I'm used to writing the following process that will react on the rising edge of the CLK (script 1): ...
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244 views

having distorted image in VGA with FPGA board

I'm using spartan 3E-100 CP132 fpga board to display a basic plus image on a monitor. I have tried using 800x600 72 hz and 640x480 60 Hz but I always get a distorted vertical lines. Is it because the ...
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1answer
38 views

Problem simulating FSM in Quartus II Simulator

I am trying to simulate a FSM using vector simulator... the state machine variable is called "Tstep_Q", I added it to waveform editor... however, when I start the functional simulation all signals are ...
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1answer
36 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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59 views

USB mouse with a PS/2 adapter for FPGA PS/2 interface

I'm designing a PS/2 mouse interface for BASYS 2 FPGA board. As you might know to communicate with a PS/2 mouse you need a protocol, so if I write my VHDL program for the PS/2 protocol and then ...
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131 views

generating 40 mhz clock from 50 MHz

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
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81 views

generating 40 MHz clock from 50 MHz in VHDL [duplicate]

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
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86 views

Read and write FPGA registers via USB or Ethernet

I'm working on an FPGA project on an Atlys Spartan 6 board. I'm programming it in VHDL. I have two 32 bit registers, one for output, the other for input. I need to be able to, respectively, read and ...