A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

learn more… | top users | synonyms

1
vote
1answer
27 views

Using Enable to switch between two Decoders

I am trying to put an enable input in a 4-to-16 decoder so I can select between two decoder. Here is a schematic: I am using two decoders to select two different addresses in a 16x16 SRAM. I am ...
1
vote
1answer
49 views

Can I use an AND gate before a clock input?

Can I use an AND gate with a clock input? For example, in the picture below, I have a positive-edge D flip-flop. I'm using an AND gate with the Select_chip input and the Clock input but I'm not sure ...
0
votes
0answers
27 views

Pipeline loop with sum

I'm working with a Zedboard and I'm trying to optimize some functions in Vivado HLS. However, when there are functions like the following where I don't know what to do. E.g: ...
2
votes
1answer
47 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
1
vote
1answer
47 views

Is it possible to drive a net from two processes when the assignments are conditionally mutually exclusive?

In my experience, driving a net from two separate processes (or always blocks) is a bad idea and will result in a multi-driver error in the tools. However, one of my acquaintances claims that if the ...
0
votes
0answers
17 views

Verilog multidimensional array

first of all, I already read a lot about multidimensional arrays in Verilog, but I was not able to find an answer. The following code is part of a example program using an oled display on my ...
0
votes
1answer
33 views

Artix - 7 Voltage Specification I/O standard

I want to design a PCB for FPGA prototyping. Please help me understand if I need to supply these voltages and why? Vref Vrefp Vin These voltages are from the Artix-7 Datasheet. ...
0
votes
0answers
19 views

How to output audio using an altera DE0 FPGA?

I am working on a project that involves realtime image processing using altera DE0 fpga board. Due to the nature of the project I am also really interested in including audio output. However according ...
0
votes
0answers
38 views

How to connect Xbee to FPGA using SPI?

I am trying to connect an Xbee to a FPGA using SPI. I found some code online to read in the MISO and convert to an 8bit output register. I have it working in the simulation but I cannot get the ...
1
vote
1answer
78 views

Need optimization advice

I'm developing an application with goal to achieve maximum throughput from device. By throughput i mean maximum amount of "cores" running at max frequency. So, we have: Virtex-6 XC6VLX240T, ISE 14.4 ...
0
votes
0answers
21 views

Can I generate a 90° Clock signal with Xilinx's ODELAY for RGMII?

Some time ago I implemented a GMII interface for my Gigabit Ethernet core. Now I'm trying to do the same with the RGMII protocol. The reference implementation from Xilinx uses IDELAY[|E1|E2] ...
-4
votes
1answer
44 views

Logic Gate Cookbook [on hold]

Is there a concise book that brings together all of the different Logic devices that can be implemented with basic logic gates? I have several digital/computer architecture books that have the ...
0
votes
0answers
18 views

Digilent EPP handshaking problem

I intend to use my Spartan-6 board as an interface between my mic (which produces I2S data) and PC for live recording. Since UART is too slow, i planned on using Digilent's parallel interface with ...
-3
votes
1answer
56 views

H264 IP core encoder estimated cost [on hold]

I would like to get an idea of what the licensing models for IP cores are (flat or per device?), and how much approximately an h264 encoder core could cost. I see that other similar but more vague ...
0
votes
0answers
14 views

Is SN74CBTD3861PWR or alike available in DIP?

I need to find some DIP IC to bidirectionally shift 5v-3v for FPGA interfacing. I have found that SN74CBTD3861PWR is more than capable of doing that. Is there any IC like this, except in DIP? Thanks ...
0
votes
1answer
49 views

Any reason not to bend the pins on TQFP and VQFP packages

I have an FPGA with a VQFP package, and I need to bend some pins back and hand solder them to fine gauge wire. Is it likely that this will damage the device?
1
vote
1answer
39 views

Newbie: From bitstream to QPSK

I'm a complete newbie. I don't want to bother this fantastic resource with my ignorance, but I'm starting to have strange thoughts. How do I go from a bitstream (say, the output of an USB port) to a ...
1
vote
2answers
37 views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
1
vote
1answer
64 views

Hardware test of FPGA, thousands of combinations?

My colleagues longtime ago have designed an FPGA (using VHDL) for a special purpose. Another colleague prepared the test scenarios. Now they want me to test this FPGA board following these written ...
0
votes
0answers
35 views

BitBus interface [on hold]

Looking for information about BitBus interfacing - preferably has anyone implemented BitBus via a CPLD controller or in an FPGA? Can see questions about CAN bus and so on, but BitBus is going back to ...
0
votes
0answers
42 views

DFT implementation on FPGA

I am trying to implement Discrete Fourier Transform on FPGA to identify the magnitude of an incoming RF signal. The RF signal is fed to an ADC clocked at sampling frequency of 50 Mhz. The ADC gives ...
0
votes
2answers
64 views

Numerically Controlled Oscillator (NCO) Sample quantity

Ive been doing some research on NCOs and some initial information (or lack of information) is bugging me. Ive read a few articles on this topic: FPGA based NCO Blog on NCOs But i still don't ...
0
votes
1answer
64 views

De1-soc HPS-to-FPGA AXI bridge

I work on DE1-Soc. I am using a linux BSP (linux console) that i found in terasic's website linux image. I have some questions about the AXI bridge. In fact i would like to send some data from the ...
1
vote
2answers
80 views

How can I implement a simple, Q only, D-latch using VHDL?

I just started VHDL today and I'm the type of person that can only learn by doing stuff, so after I made some basic gates in VHDL, I tried making a simple D-latch(so no clock signal), however without ...
0
votes
0answers
61 views

display FPGA frequency on oscilloscope?

I used sparten 3e starter board.i want to DISPLAY the PWM frequency output on Oscilloscope?which output pin i have to used ?I used J1 and J2 .the signal is distorted .why? How ? please
-1
votes
1answer
54 views

Can a microprocessor ( specifically the ALU) be considered as an FPGA that is re-programmed by the Instruction Decoder

So, I have been reading about FPGAs. As I understand, they work by providing logic blocks for the programmer to link together to solve a particular task. Many such tasks may run in parallel; so an ...
0
votes
1answer
52 views

Gate-level design with a Smartfusion2

I am working with a SmartFusion2 FPGA, and I am trying to implement a fine delay line. For that, I would like to control exactly the content of some LUTs, to get cells with no logic properties but ...
1
vote
1answer
39 views

Having trouble synchronizing serial data from FPGA to python script

I have a Spartan 6 that's collecting some data I need to send over serial to a python script where it can be displayed on my PC. This is actually the first time I've ever dug into serial ...
0
votes
3answers
58 views

Adjustable Clock Generator between 15.5 MHz and 17.4 MHz

I'm looking for an inexpensive component to generate frequencies between 15.5 MHz and 17.5 MHz. My intention is a medium-run product (a few hundred units). The issue is that I would like to change ...
0
votes
0answers
57 views

Altera TimeQuest SDC I/O constraint with SDRAM - does input delay include output hold time?

I am using a Altera Stratix IV with an ISSI 42x SDRAM device. I'm trying to understand the timing constraints for the data inputs of the FPGA (which is the data output from the SDRAM). According to ...
-1
votes
0answers
33 views

spi slave megafunction in quartus II 14.0

I am tring to add an spi slave megafunction in quartus II 14.0.00 for a Cyclone IV EP4CE22F17C8 altera Fpga. I only need a simple slave functionality to write and read registers.... if i search in ...
0
votes
0answers
27 views

Is source code compatible between DE2 and DE2-115?

I have 2 FPGAs: Altera DE2 and DE2-115. I was reading that source code is compatible between different computers and different cores. I have written a C program for use with the Micrium ucos rtos with ...
-1
votes
1answer
66 views

CPU Core frequency [closed]

I was going through the selection criteria of CPU (MCU/MPU/FPGA) and observed that core frequency is one important parameter while selecting a CPU. But I was unable to get information regarding, how ...
0
votes
1answer
67 views

blinking a display using trigger

I've been banging my head over this for a while now, basically I have this display driver that in normal conditions would update a seven segment display continuously. What I would like to do, and I'm ...
0
votes
1answer
20 views

Why build errors when connecting timers in Quartus ii?

I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g. ...
0
votes
1answer
51 views

ise complaining index out of range, but it seems to be in range?

I'm righting a vhdl module that calculates the LPCs from incoming DT samples. My ise editor is complaining that my index is out of range. Is there any reason anyone can see that it should be ...
0
votes
1answer
75 views

How to connect FPGA to Xbee? [closed]

How can I connect an Xbee to FPGA to transmit data.
0
votes
0answers
26 views

turn on led using external light dependent resistor (LDR) with nios ii and qsys design

I want to use qsys and nios ii to design a system that uses an external ldr to turn on led on an altera fpga.how can i go about this, what are the components i need in my qsys design and how to ...
0
votes
0answers
30 views

Upsampling QPSK Symbols in FPGA

I am trying to implement QPSK modulator in FPGA using Verilog. I have a question about upsampling. Assume that I want to send this byte: 1 0 1 1 0 1 0 1 I channel ...
0
votes
1answer
103 views

Convert C to FPGA

I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator. Problem is, there are tons of information out there and almost all good programs need an ...
0
votes
1answer
27 views

MityDSP and Ephiphany doubts

I've searched the documentation and tutorials about these two families of boards but I have not yet understood something. Both support ANSI-C and they both have FPGAs, so my doubt is: how is one ...
0
votes
1answer
29 views

Which is the “write enable” pin of flash memory in Stratix IV GX?

I am trying to use flash memory in Stratix IV GX fpga kit. For that I went through the pin details of the same. But the I was expecting "write enable" which will determine data is to be written to or ...
1
vote
3answers
123 views

How can I view, debug, or analyze data being input to my FPGA?

I'm working with a Xilinx Spartan6 on Digilent's Nexys3 board. I've also purchased their PmodMIC so I can try to get some audio data onto my board to perform some signal processing. The ...
1
vote
0answers
79 views

7 Segment display driver issues

I have this code for driving a seven segment display for hex. From my understanding its logically correct, but when I try and run it on my Nexsys 3 board I never get the correct output, it seems that ...
0
votes
0answers
51 views

Phase delay through LUTs

Hello all, I am trying to double the frequency of an external clock signal by implementing the circuit above in Spartan 6 FPGA. The external clock signal is asynchronous and I sync it with the FPGA ...
4
votes
1answer
124 views

Capturing data at 500MHz

I have an ADC sampling at 500MHz (It is collecting data from an Ultrasound sensor). I need to be able to stream this data to my PC (for the time being - this will be done through a wireless unit). I ...
-1
votes
1answer
93 views

Iris recognition on FPGA

I want to implement iris recognition algorithm on FPGA. before i want to start i want to make sure that fpga is the right choice for image processing. I will use a camera ov7725 to connect to an ...
1
vote
5answers
71 views

Digital circuit for adding multiple frequencies

The goal is to implement a kind of a digital piano on an FPGA. Until now, I managed to produce individual notes using counters. Basically, I generate a square wave of a certain frequency, that ...
1
vote
0answers
60 views

Setup and hold time violation constraints for Xilinx Fifo generator

I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual. I am using the fifo generator version 9.2 (manual ) to generate a fifo. I would like to ...
0
votes
0answers
54 views

Is it possible to encode a mpeg2-ts video with a FPGA linux core?

I need to take an unencrypted HDMI input, buffer that to memory, overlay it if possible, than encode it as mpeg2-ts and output it to an external device. I could do that with a raspberrypi and an ...