A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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VHDL code and unintended latches

I am working on coding a Regsiter a1 with input signals b1,rst and wra1 the register ...
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39 views

FPGA with integrated operational amplifiers?

Do you know of any FPGA/CPLD chip with embedded op-amps and ADCs? Or maybe another way to amplify weak signals ( <1mV) inside an FPGA, without using external op-amps (simulation using DDA maybe)? ...
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60 views

Shift Register Vs Multiplexer

I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way. ...
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54 views

VHDL How to Design a Screen (Frame) Buffer

I am trying to use a screen buffer to store, change and output the bits of a video data to the DVI transmit interface. I am using Altera Cyclone III development kit. I will be using 1440x900@60Hz ...
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4answers
542 views

how to properly save an architecture in a fpga ic forever

Considering I made an architecture to do some specific thing, wrote in vhdl, for example. Can I 'burn' it in a fpga chip, forever? Or how should I do it, protecting the intelectual property knowing ...
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1answer
58 views

Using a Counter to Determine next MSB position in polynomial division

I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right When ...
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1answer
40 views

Switching tone on and off at 120 bpm not working

I am trying to make a design that toggles a sound at a rate of 120 BPM (once every .5 seconds), and I am using a 50 MHz clock. Here's the tone module: ...
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1answer
61 views

CLK net warning for stopwatch code on FPGA nexys2 board?

I'm coding for a stopwatch which displays 10ths of a second on the rightmost two displays and seconds on the left two displays. The synthesis completes properly but after I make the UCF file and try ...
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30 views

Video system processing using FPGA. Options [duplicate]

I have to design a PCB where a FPGA, ASIC or SOC will be used and the system has to be able to record the video from a camera and display the live video in a display HD. The camera has a resolution ...
2
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0answers
51 views

How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would ...
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1answer
85 views

ARM Processor or FPGA to video signal processing? [closed]

I want to design a PCB where a video camera will take images and they will be shown in a display HD. So I have several questions in order to achieve it: I would like to know what is the best option ...
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1answer
62 views

How to interface 1 MSPS ADC with processing module in FPGA?

I have DE1-SoC board which contains 1 MSPS ADC, I am trying to take samples from ADC and process them. ADC Controller clock is 20 MHz and data is available every 16 clock cycles. The module that takes ...
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2answers
67 views

How do I route many FPGAs in JTAG chain?

I'm designing a chain of Xilinx FPGAs. There are many (e.g 32 or more) devices with short distance (about 10~15 cm) that I want to connect them together in a chain. I'm not sure about TMS and TCK ...
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1answer
48 views

Blocking and Nonblocking statements in same procedural block

Code module block; reg a; reg b = 1'b0; reg c; initial begin c = b; a <= b; end endmodule I simulated the code fragment shown in figure ...
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5answers
2k views

Can FPGA out perform a multi-core PC?

I don't understand how FPGA can be used to accelerate an algorithm. Currently I'm running a time consuming real time algorithm on a quadcore laptop so that four computations can be done in parallel. ...
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1answer
43 views

Can program FPGA but not PROM on my Spartan-3A dev board

I decided to brush the dust off my Xilinx Spartan-3A starter board that I got a while back, and learn to use Verilog. So with the help of Pong Chu's book FPGA Prototyping By Verilog Examples: Xilinx ...
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2answers
104 views

How do FPGA's implement sequential circuits?

I know they implement combinational circuits using LUTs, but LUTs don't have feedback, so I don't see how they can be used for sequential circuits. So how do FPGA's implement sequential circuits? ...
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2answers
75 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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1answer
48 views

Reconfiguration of FPGA in ML605 Board- THe ICAP IS NOT WORKING

The aim of my project is to load 3 bitstreams into the PROM; according to our requirement we load the 1or second or 3 bit file. PROBLEM FACING: THe problem is I'm unable to know whether the ICAP ...
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4answers
76 views

Altera DE2 interfacing with analog sensor

Can Altera GPIO pins read the analog output of a light sensor? The light sensor output is analog and I want the Altera to turn an LED on whenever the signal of the sensor is greater than some specific ...
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2answers
58 views

Why feedback is needed in PLL FM Demodulator?

I am trying to build FM Demodulator in FPGA. The architecture I am trying to use is PLL-based FM Demodulator like the one below. I searched for the working principle of this demodulator but there is ...
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0answers
80 views

Can Altera GPIO pins read the input voltage?

I have ALtera DE2-115, and I have a light sensor module, the output of the light sensor is a voltage, how can I use the Altera GPIO pins to read the coming voltage? Thanks
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1answer
34 views

How can I use an IO ports on Digilent Genesys Virtex 5 to drive 6 external leds?

I have a project which requires led output. Right now I'm using the onboard leds, but I would like to use 6 external LEDs instead. Which IO pins should I use, and how should this be done? I'm ...
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1answer
39 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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1answer
70 views

Using one channel from adc (pin connections) [closed]

For a heart rate calculator project by using Basys2 and VHDL, I am trying to connect ADC0808 in order to get 8bit digital output from my pulse sensor's output. However, although I designed the circuit ...
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1answer
63 views

FPGA based theremin , is possible?

I remember a while ago , i saw some Digital based Theremins circuits from glasgow university... http://www.theremin.info/-/viewpub/tid/10/pid/65 would it be possible to make a theremin by using an ...
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1answer
96 views

How to drive external LEDs using Digilent Genesys (Virtex-5) FPGA? How to use pressure or IR sensor input?

I'm in a Reconfigurable Logic course. Our final project is to program a Digilent Genesys Virtex-5 FPGA board to simulate a traffic light controller for a 2-lane intersection, with outputs being the ...
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1answer
47 views
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1answer
73 views

FPGA simulates well and passes timing check but fails in PCB

So you have finished your FPGA design. You have simulated it with an extensive test bench created by a different engineer and it works, event at speed after it has been compiled, placed and routed. ...
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2answers
52 views

Why does this adder need two clock cycles (two pushes of the button) to display a result?

I'm implementing a simple adder with carry out in VHDL on a BASYS2 board. This is the code below: ...
2
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1answer
61 views

Can FPGA-based ASIP be used in real life?

Imagine I want to design an ASIP for, say, some automotive application. The ASIP is developed and tested using FPGA board. Is it possible to take the FPGA and put it into the car (without creating ...
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1answer
29 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
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34 views

Using XST synthesis with Vivado 2014.3 +

Long time ago, I used to use a Vivado (2012.x) and could modify the setting of the synthesis menu to support XST and add extra option to choose from when doing synthesis. The command ...
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2answers
96 views

Text File tranfer between PC and Atlys board (FPGA)

I am new to FPGA. While doing calculations I found that I can not input number in real time to FPGA. My instructor told me to write my numbers (or data) in a text file on PC and tranfer it to FPGA in ...
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2answers
64 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
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34 views

Acquiring H-sync and V-Sync signals of video from BNC conections for FPGA boards

I am new to FPGA's and I want to do some video processing task. Assuming I have the sync signals, the algorithm is almost complete. But I don't know how to get them in hardware, in fact I don't know ...
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0answers
83 views

Transferring data from FPGA to PC (new to FPGAs)

FPGA beginner here. I have a Basys2 FPGA board(i code in verilog) and i wish to make it communicate with my PC. Currently it receives data from a slave device and stores it in an 64 bit register. ...
2
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2answers
89 views

Building a framebuffer

I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the ...
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0answers
52 views

How can an ASIP design be implemented in hardware at low cost?

Imagine, I have created an ASIP (Application-specific instruction-set processors) design in the IDE, have done the tests and in simulation, it works well. Now I want to test it in hardware. But it ...
2
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2answers
77 views

Running functions on FPGA on startup

I am wondering if it is possible to execute a function or a certain logic automatically without any impulse once the FPGA image is loaded on the the bit file. Something like an initialization sequence ...
4
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1answer
92 views

Secure signals on boot time to prevent unwanted operations

How can I be sure that at boot time my module won't get random values to it's control signals and write to an address* before I reset the module? *(or anything that shouldn't be done before reset) ...
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1answer
86 views

How can I read in an image in Verilog?

I have a .mif image that I want to encrypt in Verilog. To do so, I need to read the image into the program and store it in an array. The image would be 160 by 120 and I would like to store it in an ...
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1answer
92 views

LED PWM controller

I want to create Led PWM controller and I tought it is easy but one line in my code generates more warnings than all my previous little projects. Here is the code: ...
1
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1answer
91 views

How to create a triple redundant clock tree in FPGA manually?

I am exploring a range of techniques to implement TMR clock trees as part of a global TMR design (all resources including i/o pins, clock trees, reset trees, logic and registers are implemented with ...
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0answers
37 views

Balanced partitioning turned off?

I am programming with a CPLD of Lattice Semiconductors (ispMACH 4000ZE) and the program ispLEVER Project Navigator. I want to implement a quadriture counter. First I implemented the counter only for ...
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1answer
55 views

Forwarding a signal from RX to TX using a USRP with FPGA

This is a LabVIEW (Software) FPGA (Hardware) question so I don't know whether I should post here or on Stack Overflow. I have a USRP-2953R and I want to achieve a very simple project. I want to read ...
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2answers
58 views

Structural D flip flop in Verilog

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1answer
276 views

Generate a 100 Hz Clock from a 50 MHz Clock in Verilog

I have a DE0 board with a 50 Mhz clock that am I trying to to bring down to 100 Hz in Verilog. Could anyone help me with the code to do this?
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1answer
59 views

nRF8001 DevKit usage with FPGA and Embedded Linux

I would like to develop an application with Nordic's nRF8001 DevKit. The master emulator of this kit is an USB Dongle and it is originally meant for PC connection. My final goal for the project is to ...
0
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2answers
91 views

Signal(s) form a combinatorial loop VHDL

I was trying to implement Dual-priority encoder but I get following warnings during synthesize: WARNING:Xst:2170 - Unit prEnc : the following signal(s) form a combinatorial loop: done, first<3>, ...