A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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Project to Print School ID on a 7 Segment Display - All Segment Outputs are High When Simulated

I am working on a project that uses a BCD up-counter block, a BCD to school ID block, and a BCD to 7-segment display, in order to print out my school ID on the 7-segment display of an FPGA. Here is ...
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18 views

Discrepancy in output of post PAR simulation and bit file output

I am using Xilinx ISE to generate a bit file. I verified the functionality by post synthesis as well as post Place and route simulation . But when same bit file was loaded in FPGA there was a zero ...
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43 views

Help with the use of FPGAs to make custom microprocessor chips [on hold]

I have been reading up on FPGAs, and I was wondering how can I get my hands on one? If I were to get my hands on one, would I hire someone to perform the tasks that I needed to get done with the FPGA. ...
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35 views

Obtaining consecutive values from PS/2 [on hold]

I am trying to design a 8-bit multiplier, for instance 11110000*10101010. PS2 keyboard is used to obtain 1's and 0's. Basys2 is the used FPGA. JA, JB, JC and JD outputs of the basys2 is connected ...
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1answer
69 views

Inequality outside of process (in when statement?) (VHDL)

I am rewriting a VGA controller in (I hope) a better way; I have a 'blank' signal which means that the current pixel is outside of the visible area, and I have the gut feeling it would be better to ...
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2answers
77 views

Well written VHDL codes? [on hold]

I have years of practice in C and C++ but I recently started learning VHDL (I've done a WAV -translated to COE- player and I'm close to having a VGA controller) and I am not feeling comfortable with ...
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2answers
57 views

VGA driver in VHDL displays only black

Goal & Data I am trying to make a VGA driver on a Spartan 6 (Embedded Micro Mojo board) to display something simple like the french flag on an LCD monitor, in 640x480 8 colors. I live in Europe ...
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54 views

Dynamically Configure FPGA From Host Program

I was wondering if anyone knows an efficient way to program the FPGA(PL) for a Xilinx Zynq-7 series or related devices,from a host C program (not on the SoC, but from the host PC). Is there an Xilinx ...
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1answer
53 views

Communication between FPGA and OMAP 3530 using GPMC

I am working on a project which requires communication of data between Xilinx Spartan 6 FPGA (XC6SLX45T-2FGG484) and OMAP 3530, I have a ULK dev board on which The 32Kx8 (256Kbits) serial ...
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31 views

JESD204 ADC - fiber optic?

There's a Youtube video of a high speed ADC, using JESD204 high speed interface, interfacing with an FPGA via a fiber-optic transceiver: http://youtu.be/vkrms2udeKI Is there a commercial version of ...
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2answers
73 views

125 MHz parallel bus in a double 2.54mm header

I have a BeMicro CV low cost dev board from Altera. It features a Cyclone V. FYI: Schematics and gerber here They routed impedance controlled differential lines to some dual 2.54mm standard headers. ...
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29 views

can we design our own blocks in xilinx system generator [closed]

Iam doing morphological operations on image using system generator by designing our own blocks(custom blocks) in my project.My doubt is can we really design our own blocks which are unavailable and ...
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55 views

Optimal sorting algorithm in a fpga

I have a fixed set of 9 values that needs to be sorted in an FPGA. What would be an optimal sorting algorithm to implement?
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2answers
106 views

Pattern Recogniser on FPGA

I am trying to code a simon Game on my FPGA, and I am a bit stuck at how i should create a pattern and detect it. simon Game : http://www.freesimon.org/ My idea until now is, I create 99 states (99 ...
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41 views

Can I use full-size 64/72 bit DDR2/DDR3 memory module with CycloneV hardware controller of 24 + 24 bits?

I thinking of using Cyclone V FPGA and its hardware memory controller: There is "Cyclone V FPGA Multiport Memory Controller" document from Altera: ...
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1answer
86 views

What must be done, a new design?

I tried to compile a TCP / IP project for the MicroC / OS II RTOS with an Altera DE2 and a .sof design. I can run the MicroC / OS II with other apps but when trying ...
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1answer
58 views

Max output current per I/O pins from Basys2 (SPARTAN 3E) board [closed]

I am trying to drive IR leds out of spartan 3E fpga on xilinx's BASYS2 board. I will be using external current amplifier to drive the IR lEDs with control singal from the FPGA. I need to know the max ...
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69 views

Avoiding crosstalk between makeshift wires

My setup is as follows. I have 6 foot long 22-gauge wires connecting pin headers of an audio codec eval board and an FPGA daughterboard. I am sending an 8KHz and 128KHz clock signals and a data signal ...
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1answer
65 views

Problem with Xilinx SDK - Failed to Scan JTAG Chain

I am having an issue with running a simple Hello World program on the Trenz TE0720-01 board with a Zync 7020 FPGA. I have been following the tutorial to setup and run the Hello World program given ...
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1answer
49 views

Reason behind Altera's divide functions pipeline delay?

In Quartus II, the standard lpm_divide function has a parameter PIPELINE_DELAY. The default value is floor(WIDTH_Q div 2) - ...
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1answer
56 views

Finite state machine FSM model of FIR filter in VHDL for FPGA

I want to make a FSM model of FIR, for that I need to write FIR calculation code line in FSM implementation. Here is the actual and correct code for FIR ...
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79 views

Why does the fpga run though the entire 32bit counter sequence quickly but when running it test on the computer it took a long time [closed]

Why does the fpga run though the entire 32bit counter sequence quickly but when running it test on the computer it took a long time??
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60 views

Bidirectional bus in vhdl

I need to understand the concept of bidirectional bus. What i want to do is connect a memory with ports din and dout to a inout port named data. So along with memory i use a tristate buffer as ...
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3answers
64 views

VHDL - how to use inout as inout and as normal out?

I wanted to ask if it is possible to use an inout pin as inout and normal out? The two behaviours should be switched through a MUX. The reason for this weird looking implementation is that I have two ...
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82 views

How do I transmit an FM signal from the VGA_R port on the DE2-115?

The best reference for my question would be this youtube video: https://www.youtube.com/watch?v=4VW017qPT6Y I'm trying to do exactly what they did with the following resources: Matlab 2013a with ...
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1answer
57 views

Spartan 3AN FPGA DCM

While I use the internal clock for DCM clkin input I am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins. I changed from previous coding like this and ...
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42 views

DDR3 interface to Lattice ECP3 FPGA - TDQ

I'm looking at implementing a Lattice ECP3 FPGA with an interface to DDR3. I'm looking at the schematic for the evaluation board: Lattice ECP3-Versa Eval Board User's Guide I am unfamiliar with DDR3 ...
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1answer
82 views

Retrieving samples from an FPGA using Ethernet

I have a Spartan 3 FPGA for implementing a specific kind of digital modulation. I read the output signal by UART and RS232 but the rate is too slow for following high frequency signals. It was ...
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1answer
66 views

In-System Programming of FPGA by MCU

Let me know if this is the wrong place for this, but I am looking to program an FPGA (Spartan 6, I believe) using a microcontroller. Right now the way I am thinking about doing this is I will load ...
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2answers
96 views

Help needed with SPARTAN-3AN FPGA frequency doubler

Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked ...
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1answer
116 views

Why is my simple counter VHDL not working? Where did my signals go?

I'm a complete beginner with VHDL and an almost beginner with digital logic and I'm having a problem working through a book I'm reading. In particular, an exercise asks to build a counter with an ...
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72 views

VHDL Fpga debouncing

I had some troubles with debouncing on one button, so i searched on Google to find a solution for my debouncing problem. I found this code: ...
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39 views

What are the jitter characteristics of PLLs internal to Stratix V FPGAs?

I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying ...
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1answer
65 views

What is the 1G Ethernet jitter requirements?

We have a Stratix V FPGA on which we want to run a 1G Ethernet PHY and MAC. Because we don't have a readily available 125MHz reference clock, we are considering using a PLL internal to the FPGA to ...
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1answer
111 views

Generate -10V to 2V from 12V to 0V

I am generating square pulse 3.3V to 0V from FPGA and through a level shifter (12V to 0V). output we require is -10V to 2V. Any suggestion? We are wondering to use comparator now or is there any ...
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637 views

What are the disadvantages of using FPGA dev kits as the 'final product'?

I understand that serious HW firms can manufacture their own boards, but what are the disadvantages of using a development board 'in production', i.e. placing a PCIe card into a server and performing ...
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1answer
75 views

Synchronizing multiplier with adder to form mac

I have designed an 8-bit multiplier in Verilog which takes a maximum of 8 clock cycles to give the product. I have also coded a 16 bit adder based on combinational logic. I now want to integrate the ...
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1answer
98 views

Curious noise on FPGA Microcontroller connection

I have the following setup: An FPGA eval board has a daughterboard with pin headers connected to it. From these headers I have connected 16 ~10 inch 24-gauge wires to feed a bus to a TI OMAP-138 ...
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2answers
50 views

Constraining a 7 segment display in VHDL

Right now I'm just trying to configure a single digit 7 segment display, and I'm pretty stuck. All of the resources I can find say to use a 7 bit logic vector and just stop there. So I understand ...
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75 views

How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
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2answers
80 views

BCD to 7 Segment Decoder Schematic: Need help fitting in page

I am working on the schematic for a BCD to 7 segment decoder right now. I understand the logic, but it is the design of the schematic that I need help with. Here is my schematic so far: As you can ...
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88 views

How to scale output of FIR filter implemented in VHDL

For a DSP school project we need to implement sound effects in a SPARTAN 6 FPGA using VHDL. We tried to keep it simple and start off with a simple (100Tab) FIR filter. As coefficients we used those ...
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221 views

Why does splitting a FPGA critical path work to improve performance?

Context I am currently reading the (very good) course material on "Introducing the Spartan 3E FPGA and VHDL" promoted here (community ads) and I don't really get the idea of splitting a critical path ...
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127 views

Drawbacks of using single-ended communication over differential pairs

I recently bought a ZYBO FPGA board only to find out that there are exactly six regular single-ended GPIO lines wired to the FPGA. In contrast to that, 18 differential lines are available. The board's ...
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1answer
79 views

Creating large counters / timers

I often need to create a large counter in my projects, mostly to do some timing stuff, which could be to blink an LED every second ect. I have done this by creating a large counter, as shown in the ...
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1answer
53 views

Any good suggestions for Basys2 optional oscillator 50 MHz or 100 MHz? [closed]

I want to get the optional stable oscillator for the Basys-2 but don't know which would be the best choice for 50 MHz and 100 MHz? Has anyone bought and used any? If so, what is the part number?
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44 views

Xilinx Spartan3-E FPGA input impedance and input leakage current for the GPIO pins

I am trying to use one of SPARTAN3-E FPGA GPIO pin as an input to ADC. I want to know the input impedance and the leakage current for GPIO? Should I just connect my circuit's Vout to GPIO pin or ...
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2k views

How can an FPGA outperform a CPU

I hear of people using FPGAs to improve performance of systems that do things like bit-coin mining, electronic trading, and protein folding. How can an FPGA compete with a CPU on performance when ...
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95 views

FPGA output pin high capacity load

I am writing an interface for a HITACHI SX19V001-ZZA that is a color LCD display. Please have a look at the datasheet (pages 13-14) to understand the references I am going to make. My interface sadly ...
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51 views

How the delay locked loop (DLL) align the clock?

The delay locked loop is used for align the clock in integrated circuits. In the IC there are no of flip flops and other devices. I want to know that how the DLL align the no of clocks going to ...