Tagged Questions

A Field-programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an ...

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5 views

FPGA project sanity check, PCIE and video processeing

I have an Altera DE4 education FPGA that I'd like to use for video processing... But the thing doesn't have many ports to work with, and I don't have the funds to purchase any daughter boards. My ...
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1answer
37 views

Ultra high bandwidth serial data stream

I have a ultra high bandwidth data stream (USB 2.0 Highspeed), on which I need to add an header for synchronization. This needs to be done, since the datastream needs to be transmitted wireless on a ...
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1answer
26 views

Verilog - syntax doubt

In an FPGA code, if I have something like the following: (* LOC="M18" *) output reg lcd_e; where lcd_e is an input/output port. Does this mean that I do not need to create a UCF file ...
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1answer
44 views

Serial Camera recommendations? [closed]

I have an altera stratix iv FPGA, given to me by my professor to do a project that involves video processing. The ports I have to work with are RS232 (female), an IDE port and several SATA ports, and ...
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2answers
53 views

Using Webpack from the command line, but without a project file?

I recently got Webpack to sorta work for me on my Linux system... but I tried using ISim for simulation of my designs and got hit by a problem. And from what I can tell, this problem isn't Xilinx's ...
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1answer
132 views

Interfacing HD44780 compatible LCD display and Spartan 3 FPGA

I've recently bought HD44780 compatible LCD screen (16x2) from eBay. I want to use it with my Spartan 3 FPGA development board, but after I've thought a little about it, I'm not sure that I can use ...
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3answers
149 views

Help wanted explaining signals coming with higher frequency than clock and how to handle them

I am getting my hands on Verilog and FPGA programming. So I wrote a simple module that handles two inputs - button signal and a clock. Initially, it lights up two LEDs and when the user presses and ...
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6answers
198 views

Random bit sequence using Verilog

I want to generate a random bit sequence using Verilog. i.e. the random bit sequence would be composed of 1 and 0. Can someone guide me as to how to do it? Does anything equivalent of rand() in C/C++ ...
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3answers
76 views

What are the “embedded” and “non-embedded” design flows?

I'm reading the Spartan 6 user guide on the Memory Controller Block (MCB). The following quote discusses two design flows: There are two supported design flows for the MCB: 1) Non-embedded ...
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2answers
40 views

What is an “IP implementation”?

I'm reading the Spartan 6 user guides, specifically the Memory Controller Block guide. I quote the introduction: The Memory Controller Block (MCB) is a dedicated embedded block multi-port memory ...
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2answers
78 views

What is an FPGA package?

I'm reading the Xilinx Spartan 6 user guides. They seem to make the distinction between a Spartan 6 FPGA device and a Spartan 6 FPGA package. I'm assuming that an FPGA package contains an FPGA ...
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3answers
218 views

What happens when an FPGA is “programmed”?

From what I understand, the process of programming an FPGA comes in two parts: Encode the hardware description into bits that the FPGA can understand (i.e. write some HDL and compile it) Load the ...
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2answers
130 views

2 Ethernet Ports and a FPGA

I need to develop an Ethernet encryption scheme. All that needs to be done is take the input on Ethernet and encrypt the packets and send them out the output Ethernet. Is there ANY way I could do this ...
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1answer
31 views

Attaching two identical PSRAMs to the same set of signals

I have an ARM microprocessor connected to an FPGA through one 47 pin memory bus. Also, two identical PSRAMs (datasheet available here) are connected to the FPGA through 65 pins (47 for first PSRAM + ...
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3answers
154 views

What is the I2C ACK, and how do I detect it?

I am writing an FPGA driver in Verilog for a temperature sensor (datasheet available here). The communication protocol is SMBus, a close cousin of I2C. Now reading the datasheet, I understand that the ...
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2answers
113 views

Dealing with bidirectional communication over 1 pin

I am writing a Verilog driver for a simple temperature sensor connected to an FPGA. (The temperature sensor datasheet is available here.) Communications occur over one pin, the sda pin, where the ...
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1answer
109 views

Working with Spartan-6 LX9 clock

I am a novice in digital design and are learning things using "Advanced Digital Design with the Verilog HDL" along with a Spartan-6 LX9 board by Xilinx. So far I have managed to blink few leds on the ...
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2answers
134 views

Transferring a 1MB bitstream to a FPGA and reading it out

I am using Spartan 3E Starter Kit and I need to store a sequence of bits around 1MB long. It is a constant bitstream and will be known to me at the time of programming the board. I need to be able to ...
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1answer
202 views

Microprocessor controlling SRAM through an FPGA

I have an ARM Cortex 3M (reference manual here) connected through the FSMC (Flexible Static Memory Controller) to a Spartan 6 FPGA. In turn, the Spartan 6 is connected to some external SRAM. I need ...
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1answer
82 views

Do I need to buy USB Blaster with DE0-Nano?

I am moving this question here to separate question altogether: [DE0-Nano] [l]ooks really good, but do I need to buy the USB Blaster (or another programmer) too? Please, explain the context in ...
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2answers
46 views

Is every in-field stimulus replay-able during simulation?

I always though that simulation of hardware architectures (FPGA/ASIC) cannot cover every possible stimulus and corner-case that can be encountered in real conditions, and that hardware-accelerated ...
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1answer
142 views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
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2answers
130 views

Unexpected Verilog warning re FPGA clock assignment

I've got a question about something I don't understand that is going on in my FPGA project. I need to control two devices (AGC and ADC) through an SPI bus. As as the FPGA will be the master device, ...
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2answers
142 views

Extracting images from a camera in real-time

Me and a group of students are building a UAV and we want to put a high quality camera in it (i.e. a decent ~100mm zoom lens) and interface the imagery with on board processing. I have looked around ...
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2answers
182 views

Sharing an oscillator between two ICs

I have a microcontroller and an FPGA on the same board. If they're both going to run at the same clock speed, can I just use one oscillator to clock them both? There seems like there is something I ...
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2answers
145 views

FPGA or Microcontroller for Production Design?

I have a very simple LED driver circuit connected to a 7 segment display and a couple of buttons. I want to move this design to production, on a scale of +1k units. I have implemented the design on ...
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2answers
240 views

Hello world VHDL program - blinking LED

I am trying to get a simple blinking LED program working on my FPGA and I am having problems. Instead of blinking the LED stays on the entire time. I tried writing my on but then I just copied an ...
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4answers
375 views

When is it neater to use VECTOR representations vs INTEGERs?

In the comment thread on an answer to this question: Wrong outputs in VHDL entity it was stated: "With integers you don't have control or access to the internal logic representation in the FPGA, ...
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1answer
176 views

How to utilize HDMI port on FPGA (basic)

Two questions. I have a Xilinx Spartan 6 FPGA which only has HDMI ins and outs. Is there some sort of guide or pre-written code that I can use to start sending images to the screen? I have no idea ...
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1answer
66 views

ModelSim for XILINX 12.1 design suite

I ve downloaded XILINX ISE 12.1 but I am facing problems with modelsim. I ve download it as well but theres no set up file in the Modelsim folder. How I get this installed? Do I have to install ...
2
votes
2answers
185 views

Minimal requirements for a dedicated VNC client

On many occasions I've considered doing a small hobby project to design a minimal dedicated VNC client, in essence with a goal of a $2 cloud-based computer! (ok $2 is chosen completely arbitrarily). ...
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votes
1answer
49 views

I would like a guide to make a monitoring project for home power supply and other appliences [closed]

Aim Make a device that sends sms to a predefined number every time the current/voltage fulctuates, send sms everytime the power supply from source fails. It (the hardware) will have its independent ...
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2answers
134 views

Protecting fpga / ram against mistakes

I'm looking to build a board using a xilinx xc3s50a fpga and using a static ram chip of some kind. Perhaps something such as the GSI Tech GSI71116A. My worry is about the data lines of the ram chip. ...
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0answers
70 views

EMIF interface between FPGA (virtex5) and TI - DDUC GC6016

I am trying to interface the FPGA and Texas DDUC GC6016 with EMIF interface. I am a little bit confused in the part of interface: can you help me out? Problem: the data(16bit), address (8bit), write ...
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4answers
235 views

Clock generation using FPGA

I am trying to use Spartan 3E kit to generate 50 MHz clock. The kit comes along with a 50 MHz crystal which I am trying to use. So, I wrote a simple code to output the clock from the FPGA to the SMA ...
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0answers
56 views

Quartus - Export Verilog as Gate Level (FPGA)

I've got a project in Altera's Quartus II software which is written in Verilog. I'm curious if anyone here has figured out how to export the Verilog as a gate level netlist. I'd like to simulate the ...
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1answer
135 views

How to output signal though SMA connector in Spartan 3E Starter Kit

I want to output a signal through the SMA connector available on the Spartan 3E starter kit board. Can someone guide me as to how to do it?
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votes
1answer
89 views

Option to fail Xilinx process if pins are unconstrained

I am using Xilinx WebPack 13.2 and I recall there being a setting to force the Xilinx process to fail if a top level input/output net isn't constrained to a pin. I would like for the process to fail ...
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2answers
217 views

Syncing Signals with Global Clocks in FPGAs/CPLDs and Edge Detection

I am a newbie in digital logic design and I'm trying to get my head around syncing external signals to the global clock in an FPGA. For example, the SCK signal/clock fed to an FPGA by the SPI Master. ...
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3answers
268 views

Export restrictions on components like FPGAs

I'm considering upgrading the FPGAs on a product of mine from small Spartan3A-200s to low-to-mid-scale Spartan6s. The Spartan6s are actually cheaper, and I've just about outgrown the 200. It looks ...
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2answers
177 views

What is the most efficient method of storing statistics in an FPGA?

I'm trying to work out the most efficient way of storing statistics in an FPGA. Here is a point form summary of the situation: Many 32bit and 64bit values are calculated / stored. Any number of the ...
6
votes
3answers
299 views

Are there any Analog FPGAs?

As I understand it FPGAs are flexible "digital" circuits, that let you design and build and rebuild a digital circuit. It might sound naive or silly but I was wondering if there are FPGAs or other ...
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1answer
118 views

Need an advice with choosing FPGA kit to be used for wireless application [closed]

I need to implement a Wireless (802.11n) firewall as a FPGA application, so basically what i need is an FPGA kit that can handle the trans-receiver part for me, while giving me the ability to process ...
1
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0answers
105 views

Interfacing memory to papilio fpga board

A while ago I asked this question about using a ram chip for generating VGA signal from an fpga. After reading the replies I realized there were considerable practical difficulties with doing that, ...
7
votes
2answers
235 views

When do I need to use a clock buffer IC?

I am designing a circuit and PCB for driving 7 DACs from an FPGA. (DAC is AD9762) Would it be possible to drive the clock inputs on all 7 DACs with a single clock output (from a PLL output pin) of ...
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1answer
172 views

How can I simulate x6500 or x6000 FPGAs?

For some odd reason, Altera does not have anymore cyclone II education kits here. I was planning to use them for bitcoin mining or some other number crunching. Then I found x6500 and x6000 FPGAs but ...
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1answer
126 views

Detect this FPGA board, where to find Schemantics?

Google image search returns birds and balls with this image but, as far as I see, it has nothing to do with them. Google image search returns clothes, cotton and some odd small people with this ...
2
votes
1answer
190 views

Not able to get ac97 audio output from Atlys board

I am trying to get audio output from Atlys board (uses LM4550 audio codec). I got the ac97_controller.v core file which generates the serial o/p for the codec. It takes slots as inputs and puts them ...
9
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5answers
446 views

Embedded linux on FPGA

I have very limited experience with FPGAs (Altera - used only the visual design tools). I am planning for a new project in which I need FPGA and I could benefit a lot from an actual linux running ...
2
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1answer
154 views

Is there anything inherently wrong whith this fpga project?

I am a software engineer in 3d graphics by day so please bear with any obvious mistakes. I am looking for a project that I can use my software knowledge with in hardware and am thinking of creating a ...

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