A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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What runs a g-shock watch?

I am currently trying to learn more about watches and what it takes to build them. I currently own a watch called the G-Shock 7900b and was wondering what runs it inside. Here is a link to the watch: ...
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3answers
51 views

Do $fopen and $fwrite works with FPGA implementation also?

I used $fopen , $fclose and $ fwrite in my verilog code. It worked with simulation but when i did FPGA implementation it is not working. My question is that these works with FPGA implementation also ...
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2answers
29 views

How to define a clock in Quartus II?

I have this piece of code here: ...
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1answer
34 views

How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

I wrote a code that use RAM (created by Xilinx block generator). It's size is 10X10 (total 100 data) . I used INSTANTIATION as below: ...
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2answers
49 views

FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
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29 views

Read .txt (matrices) from SD to DDR - Zedboard

I'm converting a C algorithm into VHDL with Vivado HLS, and after exporting the RTL into Vivado and completing the design I'm using Xilinx SDK to right in the ARM9 PS. Problem: The algorithm is meant ...
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3answers
44 views

VHDL synthesis doubt

Does the synthesis tool consider an initial value of a signal given before begin of the architecture. What happens when this value is not a constant but another signal. is it better to provide ...
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1answer
94 views

Using an FPGA over an Arduino

Having read this excellent answer on FPGA's vs Microcontrollers I have a few queries. I recently completed a project that utilised reflectance sensors. Simply put, it reads the reflectance by ...
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1answer
65 views

Why there are two or more PCIe Hard IPs in some FPGAs?

I was looking for FPGA with PCIe Hard IPs. And I found some FPGAs with more than one Hard IPs. what is the advantage of having more than one Hard IPs in a single FPGA?
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1answer
41 views

How to feed data into a PCIe hard IP?

I want to implement FPGA module which can communicate using PCIe. I am using Stratix IV GX which has PCIe Hard IP in it. How I can use this Hard IP module to communicate. To develop my module I ...
2
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0answers
54 views

How to optimise Boolean functions in very many variables?

Given a black box with N binary inputs and specification of the output for every one of the 2**N possible input states (but no pre-knowledge of the logic in the box) I need software tools to design ...
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1answer
36 views

microSDXC Card not responding to SD Interface commands in 3.3V mode

I want to interface a 64GB microSDXC Card via 50MHz SD Bus mode (not UHS, 400kHz during initialization). My initialization sequence works fine with the regular 2 GB SD card from my phone up to ACMD41, ...
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1answer
21 views

Post Map simulation reliability

I'm designing a module in VHDL for an FPGA. My module is added to already existing design. It has a Wishbone slave interface. The IDE (Lattice Semiconductor Diamond 3.2 ) allows to do post map ...
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2answers
116 views
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1answer
28 views

VHDL synthesizing a module doesn't work, but simulating it does. Error: Bad synchronouse description

I am wondering why synthesizing this code doesn't work, but simulating does. ONLY WHEN TRYING TO SYNTHESIZE I get the following error: Signal sig_enable cannot be synthesized, bad synchronous ...
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1answer
45 views

Synthesizable memory blocks

In Verilog, I am trying to store the input up to 4 previous values and then operate on them.The code is fine in simulation but on FPGA, it calculates output with the current input instead of previous ...
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45 views

Porting Costas Loop from Matlab to FPGA

I have designed a Costas Loop for carrier synchronization in MATLAB, here is my code: ...
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1answer
67 views

Is there an easy way to physically implement a simple digital circuit?

I designed a digital circuit which, in total, has about 27-30 gates. Building that circuit in real life using a 74 series IC would mean using a lot of through hole/SMD chips, which wouldn't be ...
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1answer
38 views

Using Enable to switch between two Decoders

I am trying to put an enable input in a 4-to-16 decoder so I can select between two decoder. Here is a schematic: I am using two decoders to select two different addresses in a 16x16 SRAM. I am ...
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1answer
67 views

Can I use an AND gate before a clock input?

Can I use an AND gate with a clock input? For example, in the picture below, I have a positive-edge D flip-flop. I'm using an AND gate with the Select_chip input and the Clock input but I'm not sure ...
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1answer
40 views

Pipeline loop with sum

I'm working with a Zedboard and I'm trying to optimize some functions in Vivado HLS. However, when there are functions like the following where I don't know what to do. E.g: ...
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1answer
63 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
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1answer
57 views

Is it possible to drive a net from two processes when the assignments are conditionally mutually exclusive?

In my experience, driving a net from two separate processes (or always blocks) is a bad idea and will result in a multi-driver error in the tools. However, one of my acquaintances claims that if the ...
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29 views

Verilog multidimensional array

first of all, I already read a lot about multidimensional arrays in Verilog, but I was not able to find an answer. The following code is part of a example program using an oled display on my ...
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1answer
52 views

Artix - 7 Voltage Specification I/O standard

I want to design a PCB for FPGA prototyping. Please help me understand if I need to supply these voltages and why? Vref Vrefp Vin These voltages are from the Artix-7 Datasheet. ...
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36 views

How to output audio using an altera DE0 FPGA?

I am working on a project that involves realtime image processing using altera DE0 fpga board. Due to the nature of the project I am also really interested in including audio output. However according ...
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73 views

How to connect Xbee to FPGA using SPI?

I am trying to connect an Xbee to a FPGA using SPI. I found some code online to read in the MISO and convert to an 8bit output register. I have it working in the simulation but I cannot get the ...
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1answer
82 views

Need optimization advice

I'm developing an application with goal to achieve maximum throughput from device. By throughput i mean maximum amount of "cores" running at max frequency. So, we have: Virtex-6 XC6VLX240T, ISE 14.4 ...
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1answer
153 views

Can I generate a 90° Clock signal with Xilinx's ODELAY for RGMII?

Some time ago I implemented a GMII interface for my Gigabit Ethernet core. Now I'm trying to do the same with the RGMII protocol. The reference implementation from Xilinx uses IDELAY[|E1|E2] ...
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1answer
52 views

Logic Gate Cookbook [closed]

Is there a concise book that brings together all of the different Logic devices that can be implemented with basic logic gates? I have several digital/computer architecture books that have the ...
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24 views

Digilent EPP handshaking problem

I intend to use my Spartan-6 board as an interface between my mic (which produces I2S data) and PC for live recording. Since UART is too slow, i planned on using Digilent's parallel interface with ...
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1answer
68 views

H264 IP core encoder estimated cost [closed]

I would like to get an idea of what the licensing models for IP cores are (flat or per device?), and how much approximately an h264 encoder core could cost. I see that other similar but more vague ...
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15 views

Is SN74CBTD3861PWR or alike available in DIP?

I need to find some DIP IC to bidirectionally shift 5v-3v for FPGA interfacing. I have found that SN74CBTD3861PWR is more than capable of doing that. Is there any IC like this, except in DIP? Thanks ...
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1answer
50 views

Any reason not to bend the pins on TQFP and VQFP packages

I have an FPGA with a VQFP package, and I need to bend some pins back and hand solder them to fine gauge wire. Is it likely that this will damage the device?
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1answer
42 views

Newbie: From bitstream to QPSK

I'm a complete newbie. I don't want to bother this fantastic resource with my ignorance, but I'm starting to have strange thoughts. How do I go from a bitstream (say, the output of an USB port) to a ...
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2answers
73 views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
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1answer
66 views

Hardware test of FPGA, thousands of combinations?

My colleagues longtime ago have designed an FPGA (using VHDL) for a special purpose. Another colleague prepared the test scenarios. Now they want me to test this FPGA board following these written ...
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47 views

DFT implementation on FPGA

I am trying to implement Discrete Fourier Transform on FPGA to identify the magnitude of an incoming RF signal. The RF signal is fed to an ADC clocked at sampling frequency of 50 Mhz. The ADC gives ...
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2answers
80 views

Numerically Controlled Oscillator (NCO) Sample quantity

Ive been doing some research on NCOs and some initial information (or lack of information) is bugging me. Ive read a few articles on this topic: FPGA based NCO Blog on NCOs But i still don't ...
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1answer
111 views

De1-soc HPS-to-FPGA AXI bridge

I work on DE1-Soc. I am using a linux BSP (linux console) that i found in terasic's website linux image. I have some questions about the AXI bridge. In fact i would like to send some data from the ...
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2answers
83 views

How can I implement a simple, Q only, D-latch using VHDL?

I just started VHDL today and I'm the type of person that can only learn by doing stuff, so after I made some basic gates in VHDL, I tried making a simple D-latch(so no clock signal), however without ...
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67 views

display FPGA frequency on oscilloscope?

I used sparten 3e starter board.i want to DISPLAY the PWM frequency output on Oscilloscope?which output pin i have to used ?I used J1 and J2 .the signal is distorted .why? How ? please
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1answer
58 views

Can a microprocessor ( specifically the ALU) be considered as an FPGA that is re-programmed by the Instruction Decoder

So, I have been reading about FPGAs. As I understand, they work by providing logic blocks for the programmer to link together to solve a particular task. Many such tasks may run in parallel; so an ...
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1answer
56 views

Gate-level design with a Smartfusion2

I am working with a SmartFusion2 FPGA, and I am trying to implement a fine delay line. For that, I would like to control exactly the content of some LUTs, to get cells with no logic properties but ...
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1answer
47 views

Having trouble synchronizing serial data from FPGA to python script

I have a Spartan 6 that's collecting some data I need to send over serial to a python script where it can be displayed on my PC. This is actually the first time I've ever dug into serial ...
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3answers
67 views

Adjustable Clock Generator between 15.5 MHz and 17.4 MHz

I'm looking for an inexpensive component to generate frequencies between 15.5 MHz and 17.5 MHz. My intention is a medium-run product (a few hundred units). The issue is that I would like to change ...
0
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0answers
83 views

Altera TimeQuest SDC I/O constraint with SDRAM - does input delay include output hold time?

I am using a Altera Stratix IV with an ISSI 42x SDRAM device. I'm trying to understand the timing constraints for the data inputs of the FPGA (which is the data output from the SDRAM). According to ...
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30 views

Is source code compatible between DE2 and DE2-115?

I have 2 FPGAs: Altera DE2 and DE2-115. I was reading that source code is compatible between different computers and different cores. I have written a C program for use with the Micrium ucos rtos with ...
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1answer
70 views

CPU Core frequency [closed]

I was going through the selection criteria of CPU (MCU/MPU/FPGA) and observed that core frequency is one important parameter while selecting a CPU. But I was unable to get information regarding, how ...
0
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1answer
73 views

blinking a display using trigger

I've been banging my head over this for a while now, basically I have this display driver that in normal conditions would update a seven segment display continuously. What I would like to do, and I'm ...