A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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Axi DMA correct parameters

I'm making my design with Vivado HLs and Vivado and I'm doing some somewhat big transfers between DDR and my custom IP block and vice-versa. Each transfer from DDR to custom IP is of 256x256x4=262144 ...
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1answer
39 views

PAR taking too long - Xilinx ISE

I am trying to compile a project and it takes a very long time to route. - ISE 14.3 In my main module, I am using a package where I have declared an array of constants. These constants use functions ...
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28 views

Results analysis of the sequential filter and strength-reduced filter in frequency domain

I realized two low-pass filters by Verilog. The filter can be represented as following equation: 1. Sequential filter with 32 stages. For saving the multipliers, I only use one multiplier and do ...
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1answer
35 views

Does the altera ROM megafunction have a startup delay?

I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...
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1answer
88 views

Fpga Crossing signals between related clock domains

I have an fpga design with two clocks, one is 54MHz and the other is a divide-by-4 clock of the 54MHz, this is 13.5MHz clock. The 13.5MHz clock is generated by dividing the 54MHz clock in vhdl, and ...
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29 views

Strange outputs in Zedboard (sometimes)

I made a block in Vivado HLS to normalize some 512x512 pixel maps. These maps are read from the SD card into memory (and they are read correctly,I've confirmed) and then they are passed to my Vivado ...
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2answers
61 views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
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2answers
76 views

Why mosfet is preffered over voltage divider for voltage level shifting

Before writing this question I read several similar threads, but didn't found the answer I am looking for. When we need a voltage level shifter the first thing that come to the mind is a voltage ...
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46 views

FPGA- ETHERNET-VHDL [on hold]

I have a PCI card.The card contains SRAM and Ethernet Interface. I need to send my data from SRAM to client PC through Ethernet. I have to write vhdl code for SRAM and ethernet interface. but i ...
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1answer
62 views

Reading and processing 32+ ADC channels at high frequencies

For a project I need to sample 32 or more photoresistors at a time and return an ID and value of the brightest photoresistor over some communication (i2c, serial, etc doesn't really matter to me). I ...
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1answer
55 views

Whats are the FPGA boards which are low cost to get started with image manipulation [closed]

I am looking for performing certain operations on images/slow low resolution video. For this I need to get an FPGA board which is capable of handling video in and video out. I also need to interface ...
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36 views

NFC - FPGA - TFT Question

Im working on an idea but am having a problem finding even a starting point for research. The idea is to have images (video) sent over NFC to a NFC connected to FPGA (or something else could do?) and ...
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35 views

Why use decode stage on pipeline to forward control signals?

In a pipelined processor we use decode stage to decode an instruction and forward the control signals that were found until they are used. Why we don't pipeline the whole instruction and let each ...
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1answer
51 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
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2answers
35 views

How can I scan an One-Wire (1-Wire) bus for all connected devices and list their IDs

I have written a One-Wire (1-Wire, OW) controller in VHDL for FPGA designs. Currently I use a USB-OW adapter from Dallas/Maxim on my PC to get the sensors' IDs. I would like to scan the bus directly ...
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1answer
51 views

SMPS control components and technologies

Preface: the switch-mode power supply is a flyback power-factor corrected AC-DC converter. I'm currently using a combination of AVR microcontroller (ATmega64A) with some analog (such as DACs) and ...
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2answers
140 views

What's the difference between CPLD and an FPGA? [closed]

What's the difference between a CPLD and an FPGA?
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1answer
58 views

Memory scheduling in FPGA

I am trying to design an image processing system on an FPGA to do Canny Edge Detection. The design is shown in the image below. I have a large block ram to store my image. then i have smaller ...
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34 views

Axi DMA maximum velocity and DCache clarification

This is a 2 question in one thread. I'm basing my model on the matrix multiplication example. First set of questions: After some optimizations I have now a MM2S velocity of 1009 Mbytes/s and a S2MM ...
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18 views

MatrixMult modification - Xilinx

I was following the example of the matrix multiplications present in here. As my objective is different since I don't need to multiply matrices but only all the elements of the entrance matrix by ...
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21 views

Xilinx ap_axiu parameters

I'm using ap_axiu from ap_axi_sdata.h in Vivado HLS like I saw in some example to stream data throught the AXI DMA. I'm defining my value like this: ...
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2answers
277 views

FPGA Floating-point to Unsigned 32bits

Regarding something I read in a Xilinx manual saying this: Because floating-point operations use considerable resources relative to integer/fixed point operations, the Vivado HLS tool utilizes ...
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22 views

timing constraint on enable signal

I'm using the Igloo Nano FPGA, and have a question, which generally relates to FPGA design. For test purpose I've written the "dummy" code below. In my VHDL test bench, I have set the "en" signal to ...
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2answers
68 views

Drive electo-optic modulators with FPGA

I am currently using an FPGA (Virtex II NI RIO7831R) to generate the clock for a pulse generator used to drive a Linbo3 optical phase modulator. ...
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2answers
51 views

Syncronization Flip-flops

I've a doubt about clock domains and synchronization FF. I'm working on a FPGA and I've two clock domains. In the firs clock domain there is a clock frequency of 125 MHz, in the second the frequency ...
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1answer
76 views

UART to Bluetooth

I seem to find only partial explanations regarding this question, I've used Bluetooth in previous projects but I plan to use it on an FPGA project. Currently The FPGA is connecting using a UART ...
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2answers
78 views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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46 views

OR1K on DE0-Nano

I seem to be having difficulty finding much information on implementing the OpenRisc architecture onto the DE0-nano with support for linux. I found one particular article on the official site from an ...
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4answers
104 views

Required subjects to understand FPGAs [closed]

I would like to get into FPGAs. I'm a computer engineer student and I have knowledge of electronic, electromagnetism, circuit, architecture, microcontroller, software development... but I studied them ...
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2answers
51 views

Power seq. in FPGAs and MCUs

I've a question about Power Seq. requested by FPGA/MCU datasheets. I see always in datasheets that a particular power supply input must reach a voltage level before another power supply input(for ...
2
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1answer
65 views

Multicycle : Is it possible?

I've to constraints an Lattice Semiconductor FPGA and I've some doubts about the multicycle constraint described here. I've the following RTL : Basically it is a counter that is driven by a rising ...
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1answer
63 views

In a Lattice MachXO2, how can I use the EFB SPI slave and configuration SSPI (multiplexing)?

I am using a Lattice MachXO2 FPGA eval board and Lattice Diamond 3.4.0.80 on Linux. I want to use the configuration SSPI to update the FPGA configuration. During user mode, I want to use the same ...
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1answer
21 views

How to access the selectmap pins (both hardware and software) in Virtex 5 development board?

We are trying to interface a Raspberry Pi with an Virtex 5 dev. board to read the configuration memory. We have decided to use the selectmap protocol and we understand the signals involved and ...
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2answers
51 views

Single input for consecutive state transitions in an FSM: preventing fall-through

Consider the following state diagram where the inputs are c and v. The system is also receiving a high frequency clock ...
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1answer
35 views

Lattice Diamond 3.4. template/schematic generation

I'm following this tutorial: Lattice Diamond Hierarchical Design Test Bench Tutorial However i am using Lattice Diamond ver. 3.4.1, and some details are different. The Problem i am facing is with the ...
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52 views

Cannot program Xilinx FPGA with MicroBlaze project in SDK - missing download.bit file

I have a Xilinx FPGA project that I put together in Vivado 2014.4 (64-bit on Linux). The project uses a MicroBlaze. I've written my MicroBlaze firmware in Xilinx SDK 2015.1. My target hardware is the ...
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1answer
39 views

FPGA expansion pin problem

I am sending a pulse to the expansion pin of an FPGA board which I am monitoring using an oscilloscope. Why is the oscilloscope reading the pulse in the attached photo? Why it is not a pure square ...
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59 views

Having FPGA to output sound on “line out” pin using verilog

I am trying to write a verilog code for FPGA which will output sound from the embedded "line out" pin. I use Quartus II and Altera DE1. I am new to hardware programming, therefore it just takes too ...
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24 views

How to create several synthesis and implementantion runs in PlanAhead with different generics inputs?

I have set several synthesis runs in a PlanAhead 14.7 project. The main differences between these runs are some generic instantiation set in the "More Options" synthesis parameter by this way: ...
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4answers
122 views

Generate an 40MHz Clock on an FPGA with 100Mhz clock

I'm trying to generate an 40MHz clock on an 100Mhz FPGA kind of strugle with the Verilog CODE, I rediredted the Clock to a pin to check the 100Mhz: ...
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25 views

XC7Z020 JTAG not connecting

In our design I am using a Xilinx XC7Z020 Zynq SoC. In some of the boards JTAG is not connecting, I have checked JTAG cables are working with other boards.
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40 views

What could be the usage of material declaration datasheet for Spartan-6 package?

I'm starting to work with FPGAs and CPLDs. like other professional EEs when I bought a Spartan-6 board, started to search in the website of manufacture (that was Xilinx) to find everything about my ...
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47 views

8-point FFT on FPGA using verilog

I have implemented 4-point FFT using xilinx software, for 8-point FFT, we have twiddle factors (1+0j) (0.707-0.707j) (0-1j) (-0.707-0.707j). when i give twiddle factor as 0.707 and simulate it in ...
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91 views

Can we simulate FPGA board?

As a part of my curriculum, I am required to implement a project on FPGA. However, even the cheapest available boards are out of my reach (blame currency conversion !) and besides, even if I buy one, ...
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1answer
70 views

VHDL SPI xilinx spartan 3E

I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher. I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. ...
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16 views

Missing a TCL command in Libero

Libero, the IDE to build FPGAs of Microsemi has an TCL interface. But I'm missing a command to regenerated the IP's (e.g. FIFO, ...) in the project. I can't find anything in the documentation. ...
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38 views

Why has a LUT6 based SRL only 32 entries but not 64?

Xilinx FPGAs are capable of using LUTs as memory elements. The can be used as ROM, RAM and Shift Register (SRL). New Xilinx devices use 6-input LUTs, which gives 64x1 bit for RAMs/ROMs, but only 32 ...
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59 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
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63 views

high speed ADC interfacing

now I'm pretty lost , recently I've taken it upon myself to try build an oscilloscope for fun. I want to do it with high speed ADCs (unless anyone knows of a better way?) I'm hoping for about ...
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49 views

LED1 on SASEBO-W doesn't turn on [closed]

I have a SASEBO-W / 3-94336-3 board for testing side-channel attacks. I followed the steps that is mentioned in the manual for setting jumpers and switches. But after connecting USB cable and JTAG ...