A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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MMC/eMMC Boot sequence

I've been trying to hook up an eMMC chip to a FPGA, that receives commands via a micro-controller to initialize and trigger write/read operations on given sectors. I'm having trouble with the boot ...
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7 views

Altera DE2 - LCD (CFAH1602B-TMC-JP) Initialization Sequence

I have a Terrasic DE2 and am trying to initialize the LCD and then turn on the backlight for confirmation. I've modeled the sequence all the way up to the final point described in the datasheet (link ...
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23 views

SystemVerilog Memory Addressing

Just to preface this I am new to HDL. I had a semester long course on it last year but we didn't cover buses or memory in enough detail. I have been modifying some System Verilog code I was give as a ...
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61 views

Make DE0 Nano board to be Bootable and use SDRAM to store hardware and software

I have been stuck with this problem for MONTHS, please help me. I am currently working on a Nios II based design using the DE0-Nano board and the on board 32Mb sdram. My system is as follows: ...
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41 views

How do I start for the practical implementation of fpga? [on hold]

I've learned how to work with Xilinx ise. I want implementation of fpga on borad. what is borad useful for training ?
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34 views

How to create phased array with 40Khz square wave by FPGA (verilog) [closed]

I doing research about levitation acoustic. . I am finding the how to create many 40Khz square wave with difference delay time as the following figure. Now, I using ultrasound of murata and a ...
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40 views

What is the OV5642's pixel clock?

I'm trying to implement with OV5642 omnivision's ov5642 in the FPGA. it has the input clock 6~27Mhz. But there is no any information about the pixel clock. I have to know the pixel clock to interface ...
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53 views

What is the work that DE0 Nano Soc can do but DE0 Nano can't? [closed]

DE0 Nano from Terasic is one of the good board that can perform tasks with low price. Recently, Terasic have just released the new DE0 Nano Soc which integrated ARM Cortex-A9 processor into the board. ...
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1answer
46 views

Nios II system generated by Qsys looks awful (All pin are at one side). Can we make it look better?

I have tried Quartus 16.0 and 14.1. Both of them generate Nios II system that looks very awful as shown in the figure below. Is there any way to make it look better like the previous version as ...
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64 views

How do I build an interface between MicroBlaze and the FTDI FT600

I would like to implement USB 3.0 communication (instead of UART) with a custom FPGA board using Microblaze. I have already testing basic communication functionality in verilog, writing and reading ...
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1answer
57 views

SPI Master: High impedance on MOSI?

I'm interfacing the Nordic nRF52 chip with an FPGA, and sometimes I need MOSI to be at a high impedance state (read "Z" in VHDL). Else the slave won't acknowledge that the data has been transferred ...
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149 views

SPI transaction between FPGA and Microcontroller

I'm trying to write a communication protocol between an FPGA and a Microcontroller through an SPI, the µC being the Master here. FPGA: Lattice iCE40 Ultra Breakout Board Rev.A (iCE5LP4K) µC : ...
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15 views

Xparameters: IP from sub blockdesign

I have a design based on a Zynq chip and a Block Design file. As I use a IP combination several times, I have made a second BD file with this chain inside. This BD is packaed as IP and inserted into ...
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42 views

Quartus partial compile or recompile

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. ...
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42 views

VHDL: Updating global variables of entity from the sub componets

I am trying to implement a cipher in VHDL. I am beginner to VHDL. In my design there is a main entity and several components that are called from this entity. Is there any way by which I can refer ...
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35 views

FPGA signal conflict between 0 and Z?

In FPGA behavioral simulation, I have the output of a register set to 'Z', which connects to a signal in the upper level design. While doing that, I also am driving that signal to '0' in the top level....
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387 views

FPGA weak signals

Is it safe to use "weak" signal declarations in VHDL? There are the signals 'H' 'W' and 'L', that act as logic declarations, but which can be overridden by strong signals like '1' and '0'. I assume ...
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46 views

How can I load a data file into external SRAM via Quartus

I am working with a Cyclone V GX starting board. It has 4mb of external SRAM. I have written a very simple memory interface for accessing it. That works. Now I would like to load a raw (hex?) file ...
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1answer
25 views

How to generate .xst file from command line + Xilinx-ISE

I am trying to learn how to generate bit files from command line. Is there a way to generate the .xst script file from command line tools? I can only find mention of it being something that the GUI ...
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1answer
32 views

Best utillization of M9K memory in max10

I've got a max10 with a nios processor built in my memory utillization on the part is: 414,198 / 562,176 ( 74 % ) but I've used up every M9K block on the FPGA. Here is a table for the utillization ...
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2answers
42 views

VHDL: Getting a part of the actual input in a variable

I am writing a VHDL code for implementing a cipher on FPGA. I am passing a hexdecimal value to a signal as an input input : in STD_LOGIC_VECTOR (63 downto 0); ...
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25 views

Altera Cyclone II JTAG after AS Programming

I've been playing with FPGA(Cyclone II EP2C5T144C8) with Quartus II 13.0 WebEdition 64bit and Altera USB Blaster. At first, I was using JTAG mode for programming FPGA into RAM. When I wanted to ...
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1answer
24 views

Bus to wire in quartus

I sometimes run into a problem with altera's Quartus that I would like a better solution to. Sometimes I use the graphical interface for design and I have a bus that I would like to pull off just one ...
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34 views

Connecting a Virtex 6 FPGA to a high speed DAC

I'm a university student who's relatively new to the FPGA so please forgive me if something's missing here. I've recently started worked with the Xilinx ML605 FPGA board and have tested it with some ...
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1answer
65 views

Actual speed of clocks in FPGA? [closed]

I have a clock running at 100Mhz (in Xilinx FPGA). My scope only runs at 25Mhz. I suspect I am having a problem measuring it as such. However I'd like to know how fast the clock actually is. My co-...
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3answers
81 views

How to speed up Modelsim simulation

How can I get Modelsim to run faster for simulation rather than something in the picosecond range (time interval)? Are there any other methods for speeding up simulation? It takes 45 minutes to get ...
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2answers
53 views

GUI for writing HDL and viewing simulation? [closed]

I am a software developer and I'd like to code for FPGAs. Prior to buying an FPGA I thought it might be better to obtain a simulator where I could practice my HDL and see whether I can get the hang of ...
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17 views

How to solve the unable to detect any supported xilinx cable in idenify?

Now I'm trying to run Identify Debugger, My Identify debugger is old version, 3.0. The problem is that I've got some error message as below. Meanwhile, I can use IMPACK as well. the IMPACK is work ...
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93 views

How does 2-ff synchronizer ensure proper synchonization?

Using 2-ff synchronizers has been a standard for a signal to cross clock boundaries. And there are lots of paper/figures illustrating the mechanism, such as this one: It seems bclk can only sample ...
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16 views

What is the FTDI config for a Numato WaxWing Spartan 6

Unfortunately I've overwritten the configuration of the FTDI chip on my Numato WaxWing Spartan 6 FPGA development board. I've managed to reset some values back, so I can at least communicate with it, ...
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86 views

Profiling for FPGA requirements for a high-performance camera

I would like to know how to do the profiling of an image acquisition and storing pipeline on an FPGA based system, capturing images from a CMOS image sensor through LVDS interface, do some basic image ...
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1answer
65 views

Is it possible to see how much logic an IP core uses?

Is it possible to see how much logic an IP core uses in Vivado? I just found out that one of my variable might create a giant mux. I want to know how much logic this mux uses, so I could document it ...
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1answer
54 views

Write to reserved registers in I2C

I'm trying to get a MPU-9150 motion sensor running with my FPGA-Board. The problem is that my I2C-master library doesn't support writing single bits. According to the Register Map there a for example ...
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43 views

Where is the variable stored?

I at the moment programming on a Zybo board, which has a Zynq chip on it, which tightly integrates a dual arm processore with an FPGA. I an on the Arm implemented a game which stores the game image ...
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129 views

Executing an long equation in one clock cycle [closed]

I am using DE2-115 Board for doing traversal in a forest data structure in 50 MHz frequency. Multiple trees have been stored in on-chip ROM, now I need to set the address which can point to a certain ...
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4answers
104 views

Interfacing Analog signal to FPGA?

Okey, let's try this again. The board I am working with is the Smartfusion2 (M2S010-FG484 package) Starter Kit. Link-> here. My main question is If I can interface an analog signal to a pin of the ...
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1answer
49 views

Sequential power circuit for 18 servos

I'm trying to design a servo control board to be a daughter card for DE0-NANO, but run into a problem where all the servos (18 for hexapod) get to the end position on power up. The initial idea was to ...
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2answers
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Altera Cyclone IV FPGA and jtag debugging

G'day All, Is there a method comparable to jtag debugging on a microcontroller (ATMEGA32) for the Cyclone IV family of FPGA? I am trying to debug my Verilog code so ideally I just want to be able to ...
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1answer
28 views

Altera Quartus. Technology Map Viewer looks different from expected

Recently, I've installed Altera Quartus 15.1 and now follow the "getting started" instructions, you can read it here. At the step: to see the resulting circuit go to Tools →Netlist Viewers →Technology ...
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63 views

Why does the 2-digit counter count the wrong number?

I am quite new to fpga and quartus II and I am working with the schematic design. I have designed a 2-digit counter with the circuit shown in the picture and I am testing it in an Altera development ...
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2answers
80 views

How do you design a bare-metal Zynq PS-PL system with an accelerator/coprocessor in the PL?

I am new to FPGA development and am trying to build a simple system using the Zynq SoC (on the Zedboard). It will consist of an IP block generated using Vivado HLS which will accept arrays of data, ...
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1answer
42 views

operand isolation in RTL

I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
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3answers
56 views

Linear Rise exponential fall pulse generator

For a neutrino detector related experiment, I need to design a circuit which generates the pulse similar to the detector. This is required to test the front end electronics. Here are my final goals: ...
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30 views

How to assign pins of Altera Cyclone II to 7 segment?

I am quite new to FPGA and I want to design a 1-digit counter on a 7-segment on an Altera development board. What I have done so far was to schematically design a bcd to 7-segment decoder in Quartus ...
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26 views

Using TCL (or other Script) file in Quartus to automate circuit creation

I have various simple modules (Verilog) written and included in my Quartus project file. Lets say each such module receives a 8 bit input, increments the value and outputs the new value. Depending ...
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49 views

Xilinx FPGA editor + Relate to Design

I am trying to learn a little more in depth about Xilinx place and route and how everything works. I have made a very simple schematic design and am looking at the result on the board using the FPGA ...
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3answers
109 views

Are there any standard FPGA internal buses?

Are there any standard FPGA internal buses? I've always used some sort of bidirectional bus between my internal blocks, but is there a standard way of doing this?
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39 views

Interfacing a TM4C123 with a Basys3?

I'm trying to build a shell-based real-time OS on a TM4C123 LAUNCHPAD. I already have the kernel and file system done, and I was hoping to add interactivity to this implementation. I was hoping to ...
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1answer
36 views

HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7

I'm working on XAPP495 on Digilent Atlys board with ISE 14.7 I want to run and test "vct_demo" coming with the XAP 495. I tried to compile it (with ISE 14.7) and failed because of the following ...
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Is there support XC5VLX110 list in ISE Project setting?

I'm just trying to setup ISE envirmonent. But There's not XC5VLX110 in Device list at the Project Settings in ISE as below picture. What should I do for solving in this situation?