Tagged Questions

A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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FPGA simulates well and passes timing check but fails in PCB

So you have finished your FPGA design. You have simulated it with an extensive test bench created by a different engineer and it works, event at speed after it has been compiled, placed and routed. ...
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47 views

Why does this adder need two clock cycles (two pushes of the button) to display a result?

I'm implementing a simple adder with carry out in VHDL on a BASYS2 board. This is the code below: ...
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1answer
55 views

Can FPGA-based ASIP be used in real life?

Imagine I want to design an ASIP for, say, some automotive application. The ASIP is developed and tested using FPGA board. Is it possible to take the FPGA and put it into the car (without creating ...
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19 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
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Using XST synthesis with Vivado 2014.3 +

Long time ago, I used to use a Vivado (2012.x) and could modify the setting of the synthesis menu to support XST and add extra option to choose from when doing synthesis. The command ...
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59 views

Text File tranfer between PC and Atlys board (FPGA)

I am new to FPGA. While doing calculations I found that I can not input number in real time to FPGA. My instructor told me to write my numbers (or data) in a text file on PC and tranfer it to FPGA in ...
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27 views

FPGA Implementation of Digital FIR FilterFPGA [on hold]

Can anyone please let me know how to reduce the frequency of the inbuilt clock of 50MHz to 1Hz on FPGA board EP2C35F672C6 of CycloneII family. Provise a verilog code snippet please urgent.
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45 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
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28 views

Acquiring H-sync and V-Sync signals of video from BNC conections for FPGA boards

I am new to FPGA's and I want to do some video processing task. Assuming I have the sync signals, the algorithm is almost complete. But I don't know how to get them in hardware, in fact I don't know ...
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58 views

Transferring data from FPGA to PC (new to FPGAs)

FPGA beginner here. I have a Basys2 FPGA board(i code in verilog) and i wish to make it communicate with my PC. Currently it receives data from a slave device and stores it in an 64 bit register. ...
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78 views

Building a framebuffer

I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the ...
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51 views

How can an ASIP design be implemented in hardware at low cost?

Imagine, I have created an ASIP (Application-specific instruction-set processors) design in the IDE, have done the tests and in simulation, it works well. Now I want to test it in hardware. But it ...
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2answers
75 views

Running functions on FPGA on startup

I am wondering if it is possible to execute a function or a certain logic automatically without any impulse once the FPGA image is loaded on the the bit file. Something like an initialization sequence ...
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1answer
76 views

Secure signals on boot time to prevent unwanted operations

How can I be sure that at boot time my module won't get random values to it's control signals and write to an address* before I reset the module? *(or anything that shouldn't be done before reset) ...
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1answer
51 views

How can I read in an image in Verilog?

I have a .mif image that I want to encrypt in Verilog. To do so, I need to read the image into the program and store it in an array. The image would be 160 by 120 and I would like to store it in an ...
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1answer
79 views

LED PWM controller

I want to create Led PWM controller and I tought it is easy but one line in my code generates more warnings than all my previous little projects. Here is the code: ...
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1answer
72 views

How to create a triple redundant clock tree in FPGA manually?

I am exploring a range of techniques to implement TMR clock trees as part of a global TMR design (all resources including i/o pins, clock trees, reset trees, logic and registers are implemented with ...
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Balanced partitioning turned off?

I am programming with a CPLD of Lattice Semiconductors (ispMACH 4000ZE) and the program ispLEVER Project Navigator. I want to implement a quadriture counter. First I implemented the counter only for ...
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1answer
53 views

Forwarding a signal from RX to TX using a USRP with FPGA

This is a LabVIEW (Software) FPGA (Hardware) question so I don't know whether I should post here or on Stack Overflow. I have a USRP-2953R and I want to achieve a very simple project. I want to read ...
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2answers
49 views

Structural D flip flop in Verilog

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1answer
161 views

Generate a 100 Hz Clock from a 50 MHz Clock in Verilog

I have a DE0 board with a 50 Mhz clock that am I trying to to bring down to 100 Hz in Verilog. Could anyone help me with the code to do this?
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1answer
41 views

nRF8001 DevKit usage with FPGA and Embedded Linux

I would like to develop an application with Nordic's nRF8001 DevKit. The master emulator of this kit is an USB Dongle and it is originally meant for PC connection. My final goal for the project is to ...
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74 views

Signal(s) form a combinatorial loop VHDL

I was trying to implement Dual-priority encoder but I get following warnings during synthesize: WARNING:Xst:2170 - Unit prEnc : the following signal(s) form a combinatorial loop: done, first<3>, ...
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4:2 compressors gate count increasing but area decreasing, How?

From literature's I got below definition, ...
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1answer
85 views

Parallel MAC unit based on modified booth algorithm

The below diagram is the parallel MAC structure. In parallel MAC both partial product addition and accumulation take place at same time. The partial product summation + accumulation unit of above ...
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When to use process statement in VHDL

I was wondering when I am suppossed to use process statement in VHDL. I saw some examples in books but all of them could also be written within concurrent structure? I use VHDL to program FPGA.
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249 views

is 'Ok' important when sendin AT commands to modem

I'm currently using VHDL to program the FPGA Spartan 3AN Kit-set. The objective is create a programme to send an SMS to a mobile phone, using the Kit-set via the modem. I'm done with the transmit ...
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65 views

Can oscillations occur in VHDL with concurrent statements?

Imagine we had two concurrent statements that depend on each other: ...
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3answers
77 views

Does it take long to implement RSA in hardware?

I just finished my first Digital Hardware course. We covered combinational circuits, sequential circuits and FSMs. We now need to create a final design project. We have 2 weeks to do so and we work ...
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1answer
44 views

Verilog Down Counter Logic Implementation

I'm trying to write logic for storing trigger data. For example, I'm using a 3-bit counter as an address generator to store data samples. When I have a trigger event, I want to store the 4 data ...
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All Xilinx Blocks must be contained in a level of hierarchy with a System Generator Token error in xilinx

I am trying to simulate psuedo random data generator on simulink but I am getting this error ...
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1answer
37 views

Adding VHDL modules in ISE

I saw in some screenshots that people had VHDL modules inside another VHDL module at Sources Window in ISE Project Navigator. Every time I try to add new VHDL module (using RMB -> New Source...) it is ...
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1answer
61 views

I2S interface ideas for multiple MEMS microphones

I plan on forming a microphone array with 4 MEMS microphones and doing the signal processing(beamforming) in matlab/C on my PC. MEMS mics i use have Digital I²S interface with high precision 24 bit ...
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1answer
71 views

what hardware is more suitable for a project measuring power constantly and keeping it on minimum ? Microcontroller, DSP, FPGA, FPAA, which one? [closed]

I have been looking for a hardware to implement a controller for over a month, but I can't reach a decision. I want to implement a controller, which constantly measures power and keeps it in minimum ...
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1answer
51 views

Using Nexys 4 audio port [closed]

I have a digilent Nexys 4 board that I am using for learning Verilog. I have written a code that requires connecting an audio speaker to the board for evaluating. What is the speaker that can be used ...
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1answer
42 views

BlockRAM location constraints (Xilinx)

I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins). How do I do this using Xilinx ...
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236 views

FPGA Test Equipment

I mostly have desktop software development background. Trying to learn hardware design. Question: The question is mostly for developers (mostly individual contractors) who develop for any expensive ...
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1answer
46 views

Can I use the same file for a diferent FPGA speed grade?

I have a design that works correctly for an ALTERA FPGA speedgrade 6. If I want to keep using same FPGA but in speedgrade 8 will the same synthesised file work in new FPGA, or do I need to re-compile ...
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78 views

Breadboard with high frequency digital signals

I'm trying to interface an ADC chip with my FPGA. The ADC is on a breakout board that fits nicely into my breadboard (.1" pin spacing). The clock input from my FPGA into the breakout board is 12.5 ...
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2answers
89 views

PC serial communication with FPGA

I am designing a simple 16 bit adder circuit in Digilent's Xilinx Spartan 6 FPGA. The Verilog design accepts two 16 bit inputs A and B and returns the 16 bit sum C = A+B. I am ignoring carry in and ...
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Efficient use of space in FPGA

Background and clarifications: I've never developed/written a single piece of hardware before, but I'm currently using Verilog to develop a huge project for a FPGA as my final graduation project. ...
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How does part of a microprocessor (Apple secure enclave) use a microkernel (L4)?

Please excuse my ignorance. I'm an 'old-fashioned' guy who thinks that there is just 'software' and 'hardware' - and these are two separate things. Along this line of thinking an OS is part of the ...
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1answer
57 views

Modeling FPGA logic element responses

I'm working on modeling a circuit implemented on an FPGA, and the fundamental question I keep running into is this: what is a logic element? I need to be able to model the temporal response of the ...
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62 views

Trouble configuring Virtex-5 FPGA using JTAG

I'm trying to configure a Virtex-5 FPGA on a custom board and I'm using Xilinx iMPACT in order to program the FPGA using a JTAG interface. But iMPACT has trouble detecting the FPGA and gives an error ...
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1answer
168 views

Is it possible to create an IIR filter in an FPGA that's clocked at the sample frequency?

This question is about implementing a IIR filter in a FPGA with DSP slices, with very specific criteria. Lets say you're making a filter with no forward taps and only 1 reverse tap, with this ...
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1answer
51 views

Why two Xilinx scripts with different bitgen options yield correct and incorrect behaviors?

I am really puzzled by a FPGA synthesis problem on Xilinx ISE. Precisely, it took me a long hour to discover why a same RTL design (set of VHDL files) works like a charm on a board using a synthesis ...
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1answer
87 views

VHDL USB UART Problem

I've just described an UART transmitter and receiver in VHDL. In simulation everything seems to be fine. In FPGA, the loopback interface works well: I push a button, the transmitter sends data, the ...
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0answers
44 views

Using nRF8001 as a master with an FPGA

I would like to use Nordic's nRF8001 modules in Master and Slave modes and also would like to connect it with Spartan-3E FPGAs using SPI. I am considering buying the nRF8001 DevKit. I believe it is ...
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1answer
374 views

Transceivers in the field of FPGAs: When and why will we use them?

I am recently getting myself into the field of FPGA design and development, and lately I've found myself hearing a lot about transceivers. I tried searching the net for some answers about these ...