A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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how to show two results on FPGA device ,vhdl

Description of the problem: I want to show two 6 bit binary numbers on an FPGA device. The enable signal for my component is Holdover.( ...
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1answer
24 views

Xilinx Video Timing Controller freezes processor

I'm trying to acquire video from an image sensor using a ZedBoard with Vivado 2014.2 and I used an existing (working) video passthrough project of mine and simply added in a debayer (color filter ...
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23 views

Write in mass storage using File manage and control chip CH376

I tried to create a file in a mass storage device(flash memory)and write some data in it,with fpga using ch376 as a file manager.I tried to do this according to ch376 datasheet but I could not write ...
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1answer
75 views

2 Transistor XOR Cell Floating Output Problem

I designed the following 2T XOR cell for my full adder purpose: Theoretically it gives correct output for all input combinations. But on Tanner Eda using 180nm technology 5V supply, it gives logic ...
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2answers
57 views

Strange I2C signals emitted from FPGA

I have a ZedBoard FPGA device and I'm trying to implement an I2C interface to communicate with a camera module. I'm using Vivado 2014.2 and I have added an AXI IIC block to my design with the SCL ...
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72 views

Simulate a simple calculator with FPGA

I'm a beginner in FPGA and I studying some VHDL programming. so for my first project I want to create a simple calculator with keypad and LCD Display and FPGA processor. I know that I must first ...
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1answer
55 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
4
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1answer
50 views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
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2answers
62 views

FPGA RAM / SRAM in VHDL

Today I ran out of gates on my Xylinx Spartan 3 (Basys2 by Digilent) FPGA. This was not a surprise to me as I had implemented an 8 bit x 2048 array for use as an FIFO buffer. Code: ...
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1answer
71 views

FPGA Systems with good Linux support

I am working on a project using a Xylinx FPGA, board produced by Digilent. More precisely, it is the BASYS2. I have been programming the FPGA using Windows 7 as I was unable to install the support ...
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2answers
75 views

Synchronizing input and output

How do I synchronize this system? The data valid at the input indicates when the data is valid at the input. Similarly the data out valid indicates when the output data is valid. Both ...
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2answers
80 views

How do you set the time resolution in Synplify?

I am generating a 1khz pulse from a 32MHz clock, naturally via a counter. Not a difficult task, so you can imagine my surprise when the result runs at 992Hz... Simulating the behavioural model of ...
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4answers
68 views

Outputting a clock signal from an FPGA

Referring to question here: Click here, I'd like to use the 16 channel LED driver to run my 7-segment displays. I'm using a Spartan 6 LX9 FPGA to implement a 16-bit microprocessor that will take care ...
4
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3answers
93 views

Can a barrel shifter be done combinatorially?

I was told that 66b/64b encoding in 10Gb Ethernet (10GBASE-R) requires a one-cycle barrel stage, which adds a necessary one cycle to the theoretical terminal latency. The Wikipedia page on barrel ...
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30 views

Altera Quartus II: FPGA .sof file corrupt all the time

Problem Background: I have a synthesized design using Quartus II 14.0 Output file its in .sof format, to program an Altera Cyclone It works correctly on my computer I can load the file to the FPGA ...
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1answer
63 views

VHDL 'buffer' vs. 'out'

I was wondering about the 'buffer' i/o option for entities in the VHDL language. I have found that my code is much cleaner if I use the 'buffer' option instead of 'out' in any circumstance where I ...
0
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1answer
35 views

Configuration an FPGA on installation

I am working on a project using a Virtex-5 FPGA. The small projects that I've worked on with FPGAs has only required me to program the FPGAs on development boards using JTAG or loading the bit file ...
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24 views

Installation of IceCube2 on Linux

I am trying to install the Lattice IceCube2 software on my linux box (i am using Fedora 20 64bit) but i only get the message that the binary installer cannot be executed. Does anyone know how to ...
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1answer
42 views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
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1answer
72 views

How do I reset an FPGA development board to its factory settings?

I have programmed an Altera board in configuration mode so that it runs my program when booted up. Now I want to revert it back to factory configuration. How do I do that?
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1answer
48 views

UM232H-B Breakout Module as a parallel port

I want to build something like UM232H-B Breakout Module. This configuration uses an FT232H, to convert usb to serial/parallel. I don't know whether it works with FPGA parallel port programming cable ...
2
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0answers
84 views

What is bit-true implementation

What is bit-true implementation (with an example if possible)? I was reading a paper and it was stated "a bit-true implementation of the algorithm on a FPGA was performed." So what exactly is ...
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2answers
305 views

Reading the program off a FPGA

Suppose I have some sensitive proprietary software (VHDL/Verilog) on an FPGA connected to my server so I can control it by SSH. Now suppose an attacker compromises my server and can communicate with ...
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1answer
46 views

fpga verilog dual access

I need to write to a register from 2 sources.. in this case, a pci host and a microcontroller. The 2 will never access the register at the same time (basically once the PCI is done , it hands it ...
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6answers
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How does a non-FPGA (ie a PC with a CPU, RAM, hard drive) mimic logic gates?

I know that an FPGA uses look-up tables (LUTs) to synthesize logic gates. A LUT is a block of RAM that is indexed by a number of inputs. The output is the value stored at that memory address. The ...
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1answer
30 views

Generating a desired pulse train in Xilinx ISE software

Need some help with VHDL and FPGA since I am new to it. I have a Virtex-4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will ...
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131 views

Is 'IF' statement necessary for the clock process?

I'm used to writing the following process that will react on the rising edge of the CLK (script 1): ...
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1answer
234 views

having distorted image in VGA with FPGA board

I'm using spartan 3E-100 CP132 fpga board to display a basic plus image on a monitor. I have tried using 800x600 72 hz and 640x480 60 Hz but I always get a distorted vertical lines. Is it because the ...
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1answer
36 views

Problem simulating FSM in Quartus II Simulator

I am trying to simulate a FSM using vector simulator... the state machine variable is called "Tstep_Q", I added it to waveform editor... however, when I start the functional simulation all signals are ...
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1answer
32 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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1answer
53 views

USB mouse with a PS/2 adapter for FPGA PS/2 interface

I'm designing a PS/2 mouse interface for BASYS 2 FPGA board. As you might know to communicate with a PS/2 mouse you need a protocol, so if I write my VHDL program for the PS/2 protocol and then ...
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1answer
122 views

generating 40 mhz clock from 50 MHz

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
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64 views

generating 40 MHz clock from 50 MHz in VHDL [duplicate]

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
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70 views

Read and write FPGA registers via USB or Ethernet

I'm working on an FPGA project on an Atlys Spartan 6 board. I'm programming it in VHDL. I have two 32 bit registers, one for output, the other for input. I need to be able to, respectively, read and ...
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4answers
178 views

High speed memory interface between 2 FPGAs (Virtex 6)

I have a board with 2 Virtex 6 FPGAs, which are connected to each other through 64 parallel IO lines that can operate up to 400 MHz. One FPGA, let's call it B, also has 2 GB of DDR3 memory connected ...
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1answer
111 views

What is the easiest way to transmit data from a computer to an FPGA?

I have never programmed for a physical interface before. This is the board I am currently using, although I do have access to most of the DE boards on the list. I need to continuously transmit 3 ...
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56 views

Routing errors when trying to implement PLL onto Spartan-6 FPGA board

I am attempting to synthesize and implement the reference design that is linked to in the 'Reference Design Additional Information' section of the following document. I get the following error ...
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1answer
76 views

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA. ...
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1answer
75 views

What is format of output data of a webcam?

I'm in the situation of turning a Spatran3 FPGA into a classic USB webcam (Yes it's weird I know). I have a thermal analog camera which is connected to a SAA7113H ADC. I need to interface USB port of ...
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52 views

windows can't recognize my lattice machxo2 board

I purchased a MACHXO2 - 1200ze evaluation board a few days ago. I started with designing and programming simple projects as blinking leds, which worked perfectly. After that at the same day I tried ...
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2answers
64 views

Serialize bits from input/output pin with VHDL

The code below reads 40 bits of data sent in serial from a DHT-11 temperature/humidity sensor and stores the data in a 5 byte array of RAM. The code is: ...
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2answers
58 views

What is the jitter of an asynchronous FIFO?

I have an asynchronous FIFO (in a Stratix V FPGA) with two asynchronous read and write clocks of the same frequency of 100 MHz. As I understand, asynchronous FIFOs have a two-register ...
3
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1answer
113 views

What are retimers?

I am working with a low latency 10G MAC IP core for a Stratix V FPGA. One of the parameters is "High performance mode". The documentation states When enabled, high performance mode enables all ...
5
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2answers
532 views

How to minimize the size a microcontroller implemented on an FPGA?

I have 1500 lines of 16-bit data that need processing. I designed a microcontroller to execute some data processing algorithm on the dataset. It does well when the number of lines is small (< 100), ...
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2answers
88 views

Short ISE FPGA Workflow Tutorial

I'd be much obliged if somebody could point me to a short ISE workflow tutorial that shows how to implement a simple circuit using VHDL. As indicated, the tutorial should be short as I'm not ...
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3answers
78 views

To Remove Debounce from MicroJoystick installed on LogicStart MegaWing (FPGA) and read input correctly

I am working on an FPGA board and coding in Verilog. I am trying to use the MicroJoystick installed on LogicStartMegaWing, the shield with Papilio-One 500k (my FPGA board). I have to do simple tasks ...
5
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4answers
592 views

What is a ripple clock?

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1 Volume 1: Design and Synthesis which states (p. 8): Ripple counters use cascaded registers, in which ...
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2answers
382 views

PIC programming through FPGA

I would like to know if there is a way to program a PIC for the first time (write in Flash) through an FPGA card. The PIC is already soldered to the FPGA and I can't remove it. No bootloader exists ...
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50 views

Troubleshooting audio output on Nexys 2 (FPGA)

I've recently purchased the PMOD AMP1 module from digilent for use with my Nexys 2. When I program the demo project and plug headphones or speakers on the headphone output I can hear a barely ...
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1answer
168 views

3D Rotation Using Fixed Point Arithmetic - Rotating Object is Deforming (and Shrinking)

I have an FPGA board (Virtex 5) for which I have created a Wireframe GPU with the ability to rotate a sample object using a 3 Axis Trackball. Additionally, I have connected the board to a PC Monitor. ...