A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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Max number of logic units / gates per logic-unit-output wire: FPGA

I couldn't find any info about this. Is there a general rule or does it change for all vendors(altera or xilinx)? Lets assume I have a flip flop and I want to wire 10 flip-flops to its output. ...
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1answer
13 views

Vivado: Block Design sub module

I'm working on a Video processing project with Vivado 2015.2 on a Zynq device. My block design starts to get huge and hard to read. As I have several times the same pipline implemented, I would like ...
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24 views

Cheap PLD for hobbyist [on hold]

As a hobbyist I sometimes need some glue logic to interface between chips, MCU and other devices. Currently I have to use discrete logic gates for that. So, I'm looking for PLD which very cheap ...
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24 views

How to implement a 3D converter software into an external main PCB board as a module?

I am working on a project which requires 2D - 3D conversion directly to screen. So in the system, input is 2D video coming in DisplayPort format and we need to convert it to 3-D(for a given depth ...
0
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1answer
49 views

An overall PWM system by using FPGA [on hold]

I need to combine this 3 coding to form one whole PWM system by using FPGA. I tried it, there is no error, but the process is not synthesizable. Please help me. Thank you. This is code for ...
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0answers
33 views

Matlab filter to vhdl

I want to filter a sine wave signal using Altera FPGA(cyclone IV). The sine wave is first converted by an ADC with Fs= 20Mhz, then stored into a register inside the FPGA. The frequency of my signal is ...
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0answers
26 views

Initial blocks not synthesized but with XST, yes [on hold]

Usually, initial blocks are not synthesizable but with Xilinx XST, they do. Where can I find this information ? I didn't find anything in the datasheet of my FPGA (XC3S1400A, spartan 3A). I read ...
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23 views

challenges in implementation of sequential circuits and memory in fpga [closed]

Actually I am trying to implement some sequential circuits on FPGA spartan 6. Can anybody give me suggestion about what challenges i will face during this process. What are the major requirements for ...
0
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0answers
43 views

Memory Interface with a Multiplexed Address/Data Bus

I want to implement a memory interface in VHDL between an FPGA and a processor. The address/data bus is a 16-bit multiplexed bus with an ALE, write protect and BusWait. According to the NVIDIA Tegra 3 ...
4
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3answers
47 views

Where do the mux select lines come from in a CLB?

I am trying to understand the inner workings of a CLB in an FPGA but I can't seem to find out exactly how the routing multiplexers WITHIN the CLB work. Well, I understand how they work and what they ...
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0answers
24 views

lwIP initialization hangs when configuring TEMAC

I am working on a my master thesis, designing an FPGA solution, and have run into a very resilient problem. I will try to provide as much information as possible, in the hopes that someone might have ...
0
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0answers
20 views

VHDL - how to get signals from inside a uut in a testbench? [duplicate]

I am writing a testbench for a component I created. In order to debug it, I would like to write the value of some of the internal signals to a textfile. I know it is perfectly possible to write the ...
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3answers
223 views

Why would you want to write to a file when writing VHDL? [closed]

I have never so far been in the need to write to a file when making a testbench in vhdl. Seeing the signals being plotted has always been enough so far. Could someone please give me a case or the ...
0
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0answers
32 views

CFI flash interface in verilog

I am working on an Intel’s CFI - Flash (28F640J3) interface in verilog. I have written a code and tested it for many commands; read, write, erase. But I am facing problem with 'Write Buffer’ and read ...
0
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2answers
61 views

Simple LED FPGA Circuit

I am new to digital design, and have recently purchased a Bemicro MAX10 FPGA development board to help get my feet wet. I am trying to learn VHDL, and have downloaded a few PDFs to get me started. The ...
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0answers
40 views

use of ISD4002 SPI with FPGA

I am trying to build a circuit that would be some kind of INTERCOM and will be controlled by FPGA (cyclon 2 by altera ) . Because I need to have multi voice channels I choose ISD4002 because in my ...
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0answers
16 views

VHDL-FPGA-BASYS2 project [closed]

I am new in electrical engineering, and I am taking the course Digital Circuit Design. I was asked to make a project where I am supposed to send some bits to a receiver, and also add some impurity ...
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0answers
17 views

How to view Nios 2 assembly code?

I use the Altera DE2 FPGA that can run my C program. If I want to view the generated assembly, how can I do it? It's usually some flag for gcc and I use Nios 2 IDE ...
3
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1answer
52 views

AM335x FPGA Memory Integration

I'm currently designing a digital mixing console. We have a somewhat large number of ADCs and DACs (more than the multi channel audio serial port on the processor can handle). We decided the solution ...
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2answers
45 views

How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?

How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110? It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
0
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0answers
55 views

How to divide 50MHz down to 5Hz in VHDL on Xilinx FPGA [duplicate]

How to divide 50MHz down to 5Hz in VHDL on Xilinx FPGA I have a Xilinx FPGA board, with a 50MHz crystal. I need to divide that down to 5Hz in VHDL. How do I do this?
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13 views

Hardware Co-Simulation using ml605 with ISIM simulator …?

I am trying to do RTL(verilog HDL) and Firmware(System C) Co-Simulation with ISIM Simulator using VIRTEX-6 ML605 FPGA board. I am unable to run co-simulation. I have reffered the document " Hardware ...
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0answers
31 views

Possible to Use a Papilio One 250k Logic Analyzer as an FPGA?

I've just bought a Papilio One 250k logic analyzer, which seems to be based on an FPGA dev board of (nearly) the same name. Can/should I try to use this as an FPGA board? Could I easily flash my own ...
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2answers
57 views

Correctly initialize a shift register (Verilog)

I've been struggling with a very simple Verilog program. It's a 4 bit shift register that gets rotated at every clock cycle and drives four LEDs. (As you can tell I'm new to FPAGs and HDLs.) The ...
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2answers
107 views

Working on an FPGA without an IDE [closed]

I've been programming microcontrollers for about 5 years now. In my current MCU development workflow, I use emacs to edit my firmware, I compile with arm-none-eabi-gcc, and I flash code with a segger ...
6
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2answers
176 views

Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...
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1answer
85 views

Generating video with ZYNQ, using IP block design?

I am trying to implement a video streamer on Digilent ZYBO board that has Xilinx ZYNQ 7010. By the way, reason of this thing is to test the quality of an encoder board. What I want is to: Generate a ...
0
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52 views

Procedures or structural architecture - which is preferable for synthesis in VHDL?

I'm writing VHDL code which I would like to implement on an FPGA. Currently I have written separate architectures for adders, multipliers etc and combined them all using a structural architecture in ...
1
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1answer
42 views

Synthesisable alternative to the wait statement in VHDL

I'm writing VHDL code for a filter which I want to implement on a Spartan 6 FPGA. When I tried running a testbench for my code, one of the processes entered an infinite loop, so I added a wait ...
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60 views
3
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1answer
51 views

Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code

I have created the following VHDL module, which is used as an up/down counter. ...
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1answer
56 views

Clock port and any other port of a register should not be driven by the same signal source

I get this Warning from Altera Design Assistant for the below: Clock port and any other port of a register should not be driven by the same signal source Critical Warning (308012): Node ...
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1answer
43 views

pixel clock generation for xga 65MHZ [closed]

Good morning, I am designing a xga timing generator in verilog but my problem is i am not sure how to create a pixel clock using 65 MHZ for xga specification. Does anyone have any idea?. Thank you ...
0
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1answer
46 views

Altera Quartus Design Assistant Critical Warnings

I get a number of Critical Warnings with respect to lpm_ff and lpm_counter: Below are few: Rule A102: Register output should not drive its own control signal directly or through combinational ...
0
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0answers
56 views

Using 4-Channel ADC With FPGA

I am using an ADC084S101 4 Channel 8-bit A/D Converter to sample 4 different analog voltages. The ADC is being driven by a Nexys3 FPGA. I am having issues getting the ADC to cycle through all four ...
0
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1answer
81 views

IC to patch pins arbitrarily?

Is there an IC that will support patching pins together arbitrarily for AC or DC signals going in both directions across any patched pair of pins? I'm pretty sure it could be done with an FPGA though ...
2
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34 views

How to specify a minimum clock to output time in output timing constrain?

In a design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constrain, so the output should be held for some ...
0
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0answers
27 views

Lattice fusemap error

So today at work I got a Lattice Platform Manager development board (LPTM10-12107-3FTG208CES and I started working on a program to test it. I created the JEDEC file, opened the programmer, connected ...
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2answers
76 views

can't solve latches

I would like to ask if someone could help me with some latches in my desing. I am working with an aes encrypt core taken from opencores and I have described in vhdl the surrounding system to ...
4
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2answers
100 views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...
1
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1answer
94 views

FPGA Frequency Divider

I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? ...
4
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1answer
51 views

Help with multiple receiver channels and single storage architecture

I want to build a datalogger that has multiple receiver channels that run on serial communication protocol RS232 and then collect the information from the channels in a single storage that would be ...
0
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1answer
48 views

Could an FPGA be connected via DMI to a processor, if so how would this be done? [closed]

Can an FPGA be connected to a processor via Direct Media Interface (DMI), without a dedicated Platform Controller Hub (PCH)? The FPGA would serve as the south bridge/ PCH. Along the lines of ...
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0answers
37 views

Failure: (vsim-3808) Incompatible modes for port

I am attempting use modelsim to simulate a peak detector and am having trouble with the simulation of the handshaking protocol between two modules: dataGen and dataConsume. I am certain that the code ...
0
votes
1answer
35 views

Generating Channel Select for Multichannel ADC

I am using a FPGA to control a 4-channel ADC (ADC084S101) to sample four different analog voltages. In order to tell the ADC which channel to sample next, there is a control register that can be ...
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65 views

Measuring power consumption of VHDL code

I am trying to find power consumption of my vhdl code.I am going to use the power estimator in xilinx 9.2.Do the power analysis results vary in xilinx 9.2 and xilinx 14.7?? Also will xilinx provide ...
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43 views

How to Erase and Flash MachXo2 with FTDI and JTAG communication

I am new to Jtag, in my project i am using FTDI2232H and MachXO2-1200ZE CPLD while i am trasferring Opcode of read device ID [0xE0] i am getting Perfect device id. here is my Device Id code ...
3
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1answer
49 views

HCI UART ? what's the difference with simple UART?

For now, I'm sending bytes from FPGA (verilog) to serial at 115200 bps. I would like to send at higher speed and connect to a bluetooth module (RN42). UART (SPP or HCI) and USB (HCI only) data ...
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1answer
83 views

AND Gate and posedge CLK ? simple question

I'm trying to do the seq system as the picture, I'm sure it's simple but I don't remember the "gate" of this. This clock cond will be used for sending bit in ...
2
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86 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...