Tagged Questions

A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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0answers
12 views

When to use process statement in VHDL

I was wondering when I am suppossed to use process statement in VHDL. I saw some examples in books but all of them could also be written within concurrent structure? I use VHDL to program FPGA.
2
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1answer
241 views

is 'Ok' important when sendin AT commands to modem

I'm currently using VHDL to program the FPGA Spartan 3AN Kit-set. The objective is create a programme to send an SMS to a mobile phone, using the Kit-set via the modem. I'm done with the transmit ...
3
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1answer
53 views

Can oscillations occur in VHDL with concurrent statements?

Imagine we had two concurrent statements that depend on each other: ...
0
votes
3answers
68 views

Does it take long to implement RSA in hardware?

I just finished my first Digital Hardware course. We covered combinational circuits, sequential circuits and FSMs. We now need to create a final design project. We have 2 weeks to do so and we work ...
0
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1answer
31 views

Verilog Down Counter Logic Implementation

I'm trying to write logic for storing trigger data. For example, I'm using a 3-bit counter as an address generator to store data samples. When I have a trigger event, I want to store the 4 data ...
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0answers
41 views

How to multiply 3-digit numbers with VHDL? [on hold]

I want to build a simple 4-operation calculator using VHDL and FPGA. My main goal is taking 3 digit decimals and operate them as in their binary equivalents. So, how can I multiply these numbers with ...
0
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0answers
14 views

All Xilinx Blocks must be contained in a level of hierarchy with a System Generator Token error in xilinx

I am trying to simulate psuedo random data generator on simulink but I am getting this error ...
0
votes
1answer
30 views

Adding VHDL modules in ISE

I saw in some screenshots that people had VHDL modules inside another VHDL module at Sources Window in ISE Project Navigator. Every time I try to add new VHDL module (using RMB -> New Source...) it is ...
0
votes
1answer
36 views

I2S interface ideas for multiple MEMS microphones

I plan on forming a microphone array with 4 MEMS microphones and doing the signal processing(beamforming) in matlab/C on my PC. MEMS mics i use have Digital I²S interface with high precision 24 bit ...
0
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1answer
67 views

what hardware is more suitable for a project measuring power constantly and keeping it on minimum ? Microcontroller, DSP, FPGA, FPAA, which one? [closed]

I have been looking for a hardware to implement a controller for over a month, but I can't reach a decision. I want to implement a controller, which constantly measures power and keeps it in minimum ...
1
vote
1answer
35 views

Using Nexys 4 audio port [closed]

I have a digilent Nexys 4 board that I am using for learning Verilog. I have written a code that requires connecting an audio speaker to the board for evaluating. What is the speaker that can be used ...
1
vote
1answer
35 views

BlockRAM location constraints (Xilinx)

I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins). How do I do this using Xilinx ...
4
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2answers
215 views

FPGA Test Equipment

I mostly have desktop software development background. Trying to learn hardware design. Question: The question is mostly for developers (mostly individual contractors) who develop for any expensive ...
2
votes
1answer
45 views

Can I use the same file for a diferent FPGA speed grade?

I have a design that works correctly for an ALTERA FPGA speedgrade 6. If I want to keep using same FPGA but in speedgrade 8 will the same synthesised file work in new FPGA, or do I need to re-compile ...
0
votes
3answers
70 views

Breadboard with high frequency digital signals

I'm trying to interface an ADC chip with my FPGA. The ADC is on a breakout board that fits nicely into my breadboard (.1" pin spacing). The clock input from my FPGA into the breakout board is 12.5 ...
0
votes
2answers
81 views

PC serial communication with FPGA

I am designing a simple 16 bit adder circuit in Digilent's Xilinx Spartan 6 FPGA. The Verilog design accepts two 16 bit inputs A and B and returns the 16 bit sum C = A+B. I am ignoring carry in and ...
2
votes
2answers
103 views

Efficient use of space in FPGA

Background and clarifications: I've never developed/written a single piece of hardware before, but I'm currently using Verilog to develop a huge project for a FPGA as my final graduation project. ...
1
vote
2answers
98 views

How does part of a microprocessor (Apple secure enclave) use a microkernel (L4)?

Please excuse my ignorance. I'm an 'old-fashioned' guy who thinks that there is just 'software' and 'hardware' - and these are two separate things. Along this line of thinking an OS is part of the ...
1
vote
1answer
56 views

Modeling FPGA logic element responses

I'm working on modeling a circuit implemented on an FPGA, and the fundamental question I keep running into is this: what is a logic element? I need to be able to model the temporal response of the ...
0
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0answers
47 views

Trouble configuring Virtex-5 FPGA using JTAG

I'm trying to configure a Virtex-5 FPGA on a custom board and I'm using Xilinx iMPACT in order to program the FPGA using a JTAG interface. But iMPACT has trouble detecting the FPGA and gives an error ...
7
votes
1answer
156 views

Is it possible to create an IIR filter in an FPGA that's clocked at the sample frequency?

This question is about implementing a IIR filter in a FPGA with DSP slices, with very specific criteria. Lets say you're making a filter with no forward taps and only 1 reverse tap, with this ...
0
votes
1answer
41 views

Why two Xilinx scripts with different bitgen options yield correct and incorrect behaviors?

I am really puzzled by a FPGA synthesis problem on Xilinx ISE. Precisely, it took me a long hour to discover why a same RTL design (set of VHDL files) works like a charm on a board using a synthesis ...
1
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1answer
67 views

VHDL USB UART Problem

I've just described an UART transmitter and receiver in VHDL. In simulation everything seems to be fine. In FPGA, the loopback interface works well: I push a button, the transmitter sends data, the ...
0
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0answers
31 views

Using nRF8001 as a master with an FPGA

I would like to use Nordic's nRF8001 modules in Master and Slave modes and also would like to connect it with Spartan-3E FPGAs using SPI. I am considering buying the nRF8001 DevKit. I believe it is ...
5
votes
1answer
363 views

Transceivers in the field of FPGAs: When and why will we use them?

I am recently getting myself into the field of FPGA design and development, and lately I've found myself hearing a lot about transceivers. I tried searching the net for some answers about these ...
3
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2answers
807 views

How can a microcontroller be more efficient than an FPGA?

If we don't count the cost of both (MCU, FPGA) are there any applications where a microcontroller can be more efficient than an FPGA? It is easier to program a microcontroller than an FPGA (embedded C ...
0
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0answers
49 views

Digital Buck Control

I wish to emulate a voltage mode buck control using FPGA. My idea was to obtain a discrete state space equation that can be implemented digitally. At first I calculated to the buck small signal open ...
0
votes
1answer
61 views

OLA adder and signed digit vhdl design problem

I have implemented the following online adder for signed digit using vhdl code and I have simulated my design according to the example table shown in the figure attached the problem is I am not ...
1
vote
1answer
61 views

External MMU for cortex-M

The Cortex-M processors are getting faster and more powerful. The Cortex-M7 has just been announced. Yet these cannot run Linux (other than uCLinux) because the chips lack an MMU - Memory Management ...
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0answers
25 views

Integration of Pulse Generator Module with FPGA

How can I get the number of pulses from a variable frequency pulse generator module through FPGA or how to integrate a pulse generator with FPGA in order to get the number of pulses?
0
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2answers
75 views

Uploading C program to the ARM core for execution through ethernet!

I want to write a c code on my local PC and upload it to ARM core on Zed-board for execution. I know we can do it using JTAG, but for obvious reason I want to use Ethernet interface. I will be glad ...
0
votes
2answers
62 views

How can an input signal to an FPGA be determined as the clock signal?

How can I determine a seemingly arbitrary signal applied to an FPGA to be the clock signal? Conditions: 1. There is no other clock signal available (as an input to the FPGA) for sampling this input.2. ...
3
votes
2answers
76 views

Transmitting HDMI/DVI over an FPGA with no support for TMDS

I'm hoping to be able to output HDMI/DVI-D for my next FGPA project but my FPGA doesn't have native support for TMDS outputs. The FPGA is a Spartan 3E and I believe it only has support for LVDS ...
2
votes
2answers
99 views

Selecting an external crystal for FPGA

Assuming that the FPGA has a clock multiplier to get much faster frequencies internally, what is good choice for an external crystal? Let's say I've got a Virtex 7 class FPGA, and I plan to run ...
0
votes
2answers
99 views

Online arithmetic with radix 2 addition

I am having trouble working with OLA(online arithmetic addition) radix 2 SD(signed digit) addition MSDF(most significant digit first). If I have an 8 bits range unsigned number and a redundant and ...
0
votes
2answers
180 views

Interfacing FPGA and a storage device

I'm doing this project called "High data rate logger". The requirements for this project is to sample the 2 analog signals simultaneously. 2x channel 14-bit ADC Store 60 MSps (mega samples per ...
4
votes
4answers
123 views

VHDL: Using '*' operator when implementing multipliers in design

Present day FPGAs have built in DSP blocks, the latest FPGAs even have built in IEEE-754 compliant floating point units. It is possible to create DSP entity/module using a GUI after selecting the ...
0
votes
1answer
138 views

50 MHz FPGA (Cyclone IV @ DE0-Nano) and 60 MHz input from FT2232H

I want to read data from FT2232H used in an FT245 style synchronous FIFO mode (http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf p.27) with DE0-Nano FPGA board: ...
1
vote
2answers
125 views

Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [closed]

The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates. In the first year of Make Magazine - they describe a person who builds a simple ...
0
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1answer
26 views

Report entire failing path in Quartus

I am trying to optimize a design that does not meet the constrains. I know that you can use Timequest Timing Analyzer -> Report Top Failing Paths to report the paths that have negative slack but it ...
0
votes
0answers
45 views

2 Transistor 2:1 MUX with negative waveform

My PTL(Pass transistor logic) 2:1 mux show -ve waveform at at some inputs combination ckt and waveform show below: simulations perform at 180nm tech, 250mhz,1.8v power supply. How to cope this ...
1
vote
2answers
106 views

How to protect FPGA from relays?

I'm preparing for a project that will interface an FPGA with many 3v relays on its gpio. Additionally, some of the relays will be powered with the same power supply that the FPGA uses. The FPGA will ...
0
votes
0answers
76 views

How does the read & write FIFO of the Xilinx work?

I'm having a problem understanding the mechanisms of the read FIFO and write FIFO of Xilinx IP core generator (in the Xilinx platform studio software). I don't understand how the read FIFO sends data ...
0
votes
2answers
144 views

How many IP can I fit into an FPGA?

How can I calculate if a certain IP will fit into a certain FPGA? If the unit of measurement of an FPGA size is the LUT, I need that FPGA lut >= core lut For example, can I put a S1 core (37k look up ...
0
votes
0answers
74 views

Vivado optimizing away my pins

I'm fighting Vivado over what seems like a fairly stupid issue to me. I wrote some Verilog code in ISE (and simulated it). I generated a bitstream in ISE and downloaded it onto the board via impact, ...
2
votes
0answers
106 views

Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...
3
votes
3answers
198 views

custom FPGA PCB Design tips

I am planning to design a custom FPGA PCB. the PCB will contain sensors. I need to read the output of the sensors and process them in the processor. I have completed many projects using FPGA's, but ...
1
vote
1answer
132 views

counter that MSB toggles every 2 seconds [duplicate]

I want a counter that the Most significant bit toggles every 2 seconds, and gets values 0 and 1.So for example it will have 0 for 2 seconds and after 1 for another 2 seconds etc.. I need it like that ...
3
votes
0answers
109 views

Explanation of performance graph of FPGA design

After implementing a mathematical function on a FPGA chip. The following graph shows for ~40 inputs the time response, i.e. how long it took to get the output calculated. This data is part of the ...
1
vote
2answers
43 views

Altera III Cyclone FPGA input synchronization problem

I have a problem with the asynchronous input signal synchronization. I am trying to make the IIC_Slave based on Cyclone III FPGA Starter Kit. I saw 3 cases: 1) If I not use synchronization ...