A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".

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FPGA temporal partitioning

Okay, I have very large designs to implement on FPGAs and heard about this concept of temporal partitioning that allows us to implement designs which swap in and out parts of the designs Although I ...
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28 views

18bit Serdes - Xilinx Spartan6

In a project with FPGA stereo vision I use two MT9V032 cameras. The cameras are connected as in the application example in the data sheet. In stereo output mode the data length is 18bits long. ...
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2answers
46 views

Altera FPGA I/O weak pull ups

In altera FPGA documentation they make reference to a "I/O weak pullup" functionality. I would like to use internal weak pull up instead of external pullups , avoiding a PCB modification. It seems ...
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38 views

bare-metal software and FreeRTOS run in ARM Cortex A9

Is that possible to run bare-metal software in CPU0 and FreeRTOS in CPU1 since the ARM Cortex A9 is a dual core processor. I am asking this out of curiosity. If anyone has accomplished this before, do ...
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1answer
32 views

Altera Quartus not creating symbol files

I'm looking to create a schematic block from a vhdl file in Altera'a Quartus software. I've been using File->Create/Update->Create Symbol Files for Current file The file compiles okay and I get the ...
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23 views

Alternative to double dabble for binary to BCD conversions in FPGA?

I want to design a binary to BCD converter. While the double dabble algorithm is easy, it also takes a long time to execute because you can't do the whole calculation in parallel. Are there any ...
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1answer
35 views

Inferring RAM block usage with FIFO

I'm trying to infer the usage of a RAM block of my FPGA, but I fail to understand what are the hints needed. I use Synplify Pro as my synthesis tool. If I'm not mistaken, this is a dual port ...
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2answers
51 views

Timing complexity for correlation implementation on FPGA

Let's say we have a database of five thousand 512 point discrete signals. Each database entry is unique in itself. The important point to note about the signals in the database is that out of the 512 ...
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1answer
22 views

Can't Find Further Documentation on Spartan3E IO

I am trying to find some further detail on the IO resources for a Spartan 3E. Using ISE, when I open PlanAhead to look at the floor plan I see a lot of names, organization and acronyms that I do not ...
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22 views

Help in Alterra DE0-Nano Clock

I am having trouble using the On-board 50MHz Clock of my DE0-Nano. I have this code: ...
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25 views

vhdl coding for ram design with ip core [closed]

i written code for counter which feeds the data to the dual port ram block coming from the ip core generator here m facing port mapping problems please help me its urgent..... this is my codes <...
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51 views

Finding Fmax in FPGA design without adding extra cycle

I'm trying to find the Fmax of my VHDL design in Quartus II. I know that you need to have a register-to-register path for finding the Fmax. However, when I register the input, another cycle is added. ...
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4answers
823 views

Can a NOT gate be used to achieve 180 degree phase shift?

I have seen from various sources which say that a NOT gate cannot be used to achieve an 180-degree phase shift. Is this claim true? Edit: The question is definitely sounding unclear because that is ...
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28 views

How do I tell when this Xilinx AXI BRAM Controller is reading data?

I am using a XILINX IP AXI BRAM Controller (document here) which is connected to another XILINX IP BRAM memory unit. The AXI Controller is used to connect the BRAM memory to PCIe. I want to replace ...
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52 views

VHDL: pipeline with a for loop

Question moved to: http://codereview.stackexchange.com/questions/135868/vhdl-pipeline-with-a-for-loop I'm implementing an AXI4-Stream module. The module uses three DSP blocks (DSP49E1, UG479 - Xilinx)...
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1answer
39 views

Does a signal need to be in a clocked process to be registered (VHDL)?

I understand that it is best practice to register the outputs of all modules; so, I want to do that. However, I'm unsure what exactly it means to register an output signal. I.e. Do I have to include ...
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21 views

Facing problem with AXI Interconnect based DDR3 SDRAM

I am using DDR3 for our USB3.0 project to extend the memory of a device. Previously we were using 2 BRAM controllers(1 BRAM for Code storage and 1 BRAM for Data storage). With 2 BRAM controllers, our ...
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1answer
30 views

Effective Capacitance of an FPGA board

I am currently designing a processor on an Altera DE0 Nano and found out that the power consumption of my design may be computed by this equation: P = C * V^2 * (a * f) where P is the power ...
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1answer
40 views

FPGA Interrupt in FreeRTOS

I am using freeRTOS in Zedboard. I am able to enable the PL-PS interrupt in bare-metal program. I couldn't really find any documentation/tutorial on how to link the FreeRTOS and the PL interrupt ...
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34 views

How do I debug my ADC FMC card? [closed]

I have an FMC card that has 4 ADC's, and it connects to an FPGA carrier board. The FMC card isn't working at the moment, and I don't see many ways to debug it. Does there exist some type of prototype/...
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1answer
36 views

Why is this logic vector assignment delayed?

I'm a beginner in FPGAs programming, and I've came across this issue recently: In a synchronous process, what is the logical explanation for a signal not being able to be read right after its ...
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31 views

Debugging FreeRTOS Task in Xilinx SDK

I am using the FreeRTOS for my Zedboard and I would like to debug a task created in the freertos. I have installed the stateviewer plugin in order to preview the task, but when I press debug (GDB), ...
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1answer
88 views

Why am i not getting a constant delay circuit for any input size?

I'm trying to design the following circuit: The circuit should have a constant delay for any input size. However, when I change the input size from 10 bits to 12 bits, the circuit becomes slower. The ...
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1answer
10 views

VC707 SMA input voltage

I am trying to integrate with Raspberry Pi (RPI) and VC707 (FPGA board from Xilinx). VC707 has two GPIO SMA ports but it's input voltage is 1.8V according to manual. As output voltage of RPI is 3....
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2answers
32 views

Initialize variable used in always_ff block

I have a bunch of (System) Verilog code that uses initialization statements. This is code for an Altera FPGA. I test the code using automated testbenches in the version of modelsim that ships with ...
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1answer
39 views

Altera FPGA Configuration using Flash

During my current PCB design using Altera FPGA, I happened to come across knowledge that Altera EPCS devices are to be used for FPGA configuration. After further research, I realized the same job can ...
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1answer
56 views

Write operations on eMMC chip (not SPI) with data incoming from MCU

I'm working on integrating an eMMC ship to a FPGA. As for now, the initialization is working fine, I've managed to receive the CSD and CID registers properly, and I can select and move the chip to ...
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1answer
77 views

FPGA: How do LUT's change their logic

I've looked at a couple of posts on this topic, but I can't really get a feel to them. Does the LUT have an input where the logic address is given, or does the LUT read from the D Latch? If anyone has ...
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1answer
56 views

Will inout ports used only as in or out be optimized?

I am writing a VHDL design in Xilinx Vivado. I received an example code for an FMC card where all the ports are designated as inout. If I use an ...
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43 views

How to output any intermediate signals in VHDL?

I have the following code, which describes a simple element with two registers and an adder. There are also some control signals, which are basically "load enables" for those registers. Each register ...
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68 views

FPGA Multiplication and Division

Background I am trying to estimate the speed of a quadrature encoder with the following equation v = Δx/Δt Δx is a 16 bit signed integer and Δt is a 16 bit ...
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3answers
113 views

Why does Altera DE2-115 board GPIO expansion header contain 5V & 3.3V power but the IO standard has no 5V?

The altera DE2-115 board user manual section 4.8 page 47 describes the GPIO expansion header. It is clear that it has 3.3V and 5V power supply. However, it later says that "The voltage level of the I/...
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SPI readings are shifted, inconsistent (nRF Master, FPGA Slave)

I'll try to simplify my project as much as possible to make this understandable. I'm wiring an nRF52 PCA10040 board to an iCE5LP (Lattice) FPGA. I'm having an issue with the bytes coming in to the ...
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1answer
23 views

Xilinx FPGA Editor + Line Names?

I am playing around with the FPGA editor and looking at a Spartan3E. When I click the different lines the console displays what I guess is a name for each individual line: What exactly do these mean? ...
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32 views

tvalid delay in AXIS

I am trying to feed the cosine wave from the DDS compiler to the multiplier and multiply with another cosine wave. The output of the multiplier is then feed into a CIC compiler as shown below. I ...
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59 views

FPGA Performance of Routing

I am trying to learn more about the performance of different routings in my design using Xilinx ISE. I've figured out how to move logic around by changing which CLB/Slice holds which piece of using ...
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2answers
335 views

Is this BRAM being fully utilized if I use a different data width?

Background I am using a Xilinx FPGA from the Kintek-7 family. The documentation for the memory resources can be found here. Here are some important excerpts from the document (referencing pages 11 ...
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1answer
37 views

AXI SPI of MicroBlaze connected to SD card

I would like to connect SPI IP core of microblaze on custom board but I have some problem. I need 100-400 KHZ clock but the system clk is 100MHz and SPI Clock is 6.25 MHz. Is it necessary to reduce ...
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34 views

CPLD: How to buffer data with short delay?

I have the following case: I have 2 logic(1/0) input signals (parallel and at 5MHz) into the CPLD. I want to capture the 2 paralell input signals at the same time and convert them into a serial output ...
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51 views

Spartan 3E FPGA and TFT display

I am trying to display white color on TFT monitor using Spartan 3E FPGA Kit. I am not able to get the following verilog to run: ...
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48 views

FPGA based BLDC control [closed]

I am designing Zynq-7000 BLDC motor (actually 4 of them) control solution now for low voltage (7.4V/11.1V/14.7V) application - low voltage quadrotor flight controller. I want to use that dev kit as ...
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1answer
96 views

Is RAM with read ahead (Look ahead) possible?

Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports? A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed ...
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111 views

MMC/eMMC Boot sequence

I've been trying to hook up an eMMC chip to a FPGA, that receives commands via a micro-controller to initialize and trigger write/read operations on given sectors. I'm having trouble with the boot ...
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Altera DE2 - LCD (CFAH1602B-TMC-JP) Initialization Sequence

I have a Terrasic DE2 and am trying to initialize the LCD and then turn on the backlight for confirmation. I've modeled the sequence all the way up to the final point described in the datasheet (link ...
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29 views

SystemVerilog Memory Addressing

Just to preface this I am new to HDL. I had a semester long course on it last year but we didn't cover buses or memory in enough detail. I have been modifying some System Verilog code I was give as a ...
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90 views

Make DE0 Nano board to be Bootable and use SDRAM to store hardware and software

I have been stuck with this problem for MONTHS, please help me. I am currently working on a Nios II based design using the DE0-Nano board and the on board 32Mb sdram. My system is as follows: ...
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48 views

What is the OV5642's pixel clock?

I'm trying to implement with OV5642 omnivision's ov5642 in the FPGA. it has the input clock 6~27Mhz. But there is no any information about the pixel clock. I have to know the pixel clock to interface ...
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51 views

Nios II system generated by Qsys looks awful (All pin are at one side). Can we make it look better?

I have tried Quartus 16.0 and 14.1. Both of them generate Nios II system that looks very awful as shown in the figure below. Is there any way to make it look better like the previous version as ...
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74 views

How do I build an interface between MicroBlaze and the FTDI FT600

I would like to implement USB 3.0 communication (instead of UART) with a custom FPGA board using Microblaze. I have already testing basic communication functionality in verilog, writing and reading ...
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63 views

SPI Master: High impedance on MOSI?

I'm interfacing the Nordic nRF52 chip with an FPGA, and sometimes I need MOSI to be at a high impedance state (read "Z" in VHDL). Else the slave won't acknowledge that the data has been transferred ...