Tagged Questions

-5
votes
0answers
61 views

Applications with kernels that can be accelerated in hardware [closed]

Could you give me a list of applications with kernels that can be accelerated in hardware? Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others. To ...
4
votes
1answer
89 views

Triple modular redundancy (TMR) in hardware

I would like to know if there are already ASICs/FPGAs implemented on top triple modular redundancy for fault tolerance/if they themselves implement TMR for fault correction. Any reference to research ...
0
votes
2answers
212 views

Has an FPGA ever caused health issues?

Considering the number of people here who work closely with always on FPGAs, ASICs etc, and how materials react to heat, etc. Are there any known health issues when dealing with hot electronics ...
0
votes
1answer
116 views

set and reset of D flip-flops : always physically present?

On various technology (discrete, ASIC, FPGA), I'd like to know if the asynchronous signals set and reset are always present on D (edge-triggered) flip-flops. If not how the reset process can be ...
0
votes
1answer
139 views

Regular or Irregular Hardware?

I have a hardware structure (described in logic diagram consisting of adders and multipliers) that is extremely regular, i.e., one small hardware is repeated again and again in the structure with ...
3
votes
1answer
181 views

Price History of FPGA

My goal is to extrapolate (or estimate) the future prices of FPGAs and/or ASICs. Does anyone know of the price history of FPGAs or ASICs? I am looking for a source of information. I know that ...
2
votes
2answers
63 views

Is every in-field stimulus replay-able during simulation?

I always though that simulation of hardware architectures (FPGA/ASIC) cannot cover every possible stimulus and corner-case that can be encountered in real conditions, and that hardware-accelerated ...
12
votes
1answer
582 views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
7
votes
4answers
1k views

Reset: synchronous vs asynchronous

I've been working with fpgas for years, and always used synchronous resets for every parts (that need it) of my circuits. It helps the circuit to be globally reset at a given clock cycle. However, I ...
5
votes
3answers
168 views

What options do I have when synthesising control registers?

When your design includes control registers that are set/read on a dedicated clock domain (SPI or I2C etc), how do you usually deal with those? For instance: Do you keep them on their own clock ...