Tagged Questions

-1
votes
0answers
40 views

HD-SDI to SD-SDI

I need to convert a HD-SDI signal to SD-SDI. I have been looking into deserializers and fpga, but have not found a good solution yet. How can this be done? Preferred is a "simple" solution, that ...
1
vote
1answer
64 views

Interfacing 3.3V Flex 6000 FPGA to a 5V CMOS DSP (Multivolt IO Question)

I'm going to interface a 5V CMOS DSP to the 3.3V Flex 6000 FPGA. This FPGA supports 3.3V and 5V IO according to the below figure from the datasheet: Since the FPGA I found in stock is the 3.3V ...
1
vote
0answers
61 views

Calculating delay caused by the voltage translator chip GTL2000/NVT2000

I want to interface a 5V DSP to a 3.3V FPGA so I need to use voltage/Logic translators for the data, address and control buses. I found this translator: GTL2000 , It's available in a 22-bit package ...
2
votes
1answer
245 views

Should I use pull up resistors in this configuration?

I am interfacing a 3.3V FPGA to a 5V DSP. I am using this bidirectional voltage transceiver: http://www.nxp.com/documents/data_sheet/GTL2000.pdf In the diagram in page 4 they're using pull up ...
-1
votes
1answer
239 views

Need an advice with choosing FPGA kit to be used for wireless application [closed]

I need to implement a Wireless (802.11n) firewall as a FPGA application, so basically what i need is an FPGA kit that can handle the trans-receiver part for me, while giving me the ability to process ...
9
votes
5answers
9k views

Code example for FIR/IIR filters in VHDL?

I'm trying to get started with DSP in my Spartan-3 board. I made a AC97 board with a chip from an old motherboard, and so far I got it to do ADC, multiply the samples for a number <1 (decrease ...
7
votes
1answer
622 views

All Digital Phase Lock Loop

I'm looking to implement a phase lock in an FPGA without using any external components (other than the ADC). For simplicity locking to a simple binary pulse is adequate. The frequency of the signals ...