Tagged Questions

3
votes
1answer
59 views

Free linting tool for Verilog

Is there an opensource linting tool for Verilog. I've seen HDL companion and other but they all come with a price tag.
2
votes
1answer
39 views

ModelSim Altera: simulating the “lpm_add_sub” module?

I'm trying to simulate a verilog module that uses the "lpm_add_sub" module to provide an adder with a separate carry in (for some reason Quartus II doesn't recognise that ...
1
vote
2answers
56 views

Parameterized net width in Verilog

Is something like this possible ? parameter width; wire[width-1] a_net = (width)'b0; I basically need a variable to control the width of the right hand side. I ...
-5
votes
0answers
67 views

Applications with kernels that can be accelerated in hardware [closed]

Could you give me a list of applications with kernels that can be accelerated in hardware? Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others. To ...
2
votes
4answers
144 views

Most efficient way to select between 10 large buses?

I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so? Currently I have the following SystemVerilog implementation ...
2
votes
1answer
66 views

In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?

I'm writing some verilog and simulating it using modelsim. I have a block that looks like this: ...
-7
votes
1answer
55 views

3-phase lock loop in verilog

I want to implement a phase lock loop in verilog hdl. The input is the source voltage (which is a sine wave) and the output is theta(in terms of sin and cos).
0
votes
2answers
138 views

Square law device using FPGA

I am trying to implement Square Law Device on Virtex 5 Family FPGA but before burning it to the FPGA I was trying to simulate it in the Xilinx ISE kit. I am not sure whether the code is correct or not ...
4
votes
1answer
108 views

Difference between @* and @(*) in verilog

What is the difference between always @* and always @(*) in verilog?
0
votes
1answer
141 views

Problem initializing Xilinx BRAM

A while ago I added a feature to GNU binutils to convert files to verilog mem files, suitable for reading with $readmemh. The output is very close to what you might get with xilinx's data2mem ...
2
votes
3answers
178 views

Open Source verilog synthesizer

I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no ...
1
vote
2answers
318 views

How to Add the Xilinx Library to Modelsim

I'm trying to simulate an example design of an IP Core, but the version of ModelSim I have installed (Altera Edition/Linux) does not link to the Xilinx library. How can I permanently or temporarily ...
0
votes
1answer
86 views

How can I detect a pulse from a device with the AC'97 component of a Xilinx Atlys board?

I have a digital device which transmits rapid pulses over a 3.5mm audio cable, indicating that some event has occurred. I want to connect that device to my 3.5mm line in jack on my Atlys board and ...
2
votes
2answers
354 views

MUX verilog code

Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it. ...
1
vote
2answers
268 views

Feedback loop in Verilog

I have a problem with writing Verilog HDL code. I want to design a simple PID controller in FPGA I am using Cyclone II family. I want to feedback my output value as an input in a previous stage of ...
1
vote
1answer
425 views

Fixed Point Division in verilog for Spartan 6

I am developing a core on Spartan 6 which needs to do divisions like 1/6,2/4 etc... so the values are always between 0 and 1. As I dont need the precision of floating point I am want to use a fixed ...
2
votes
2answers
139 views

How to generate wait until division is over in verilog?

I am using a division module which has two signals other than inputs "go" to indicate start of division. "done" to indicate stop of division. It is taking approx 300 clock cycles for the division to ...
2
votes
1answer
109 views

Design doesnot work properly when clock net delay is slightly higher in spartan3a fpga

I am running my design on spartan3a 3s700afg484 at 50 mhz. There is no set up and hold time violations. There is only one global clock net. My clock report for two runs are RUN 1: Info: [707]: | ...
3
votes
1answer
226 views

What are the XGMII control pins?

The 10 Gigabit Media Independent Interface (XGMII) is an interface standard that uses 72 data pins for both RX and TX. As far as I understand, of those 72 pins, only 64 are actually data, the ...
3
votes
1answer
423 views

TCP/IP stack in Verilog

I am about to write a TCP/IP stack in Verilog. I would have thought this was a relatively common thing, and that implementations would readily be available online. The obvious Google search for a ...
2
votes
1answer
268 views

DVI-D Single Link to FPGA

I'm using LatticeXP2 family FPGA. DVI-D Single link operating at 720p is connected to FPGA. I somehow need to read RGB and XY coordinates of pixels. I know I need TMDS decoder, but I'm not sure how to ...
0
votes
0answers
103 views

NetFPGA testbench

I'm aware of the normal way to build a new project for verilog and I'm aware that normally the projects are initiated with a script, however; can I ask if their are any standalone testbenchs that I ...
4
votes
3answers
230 views

LUT vs. hard IP based multipliers on Spartan-3 FPGA for constant coefficient multiplication

Before I get to my question, here are the specs for the board and synthesis tool I am using: Family: Spartan3 Device: XC3S200 Speed: -5 Synthesis Tool: XST My 4-bit multiplier is in my design's ...
1
vote
1answer
120 views

Can I create a verilog file to both simulate and synthesize?

Recently I was reading a Verilog study book. I finally realized that a Verilog file may not be synthesizable, because some Verilog statements are for simulation use only. But I'm too lazy to make one ...
0
votes
3answers
282 views

Designing FPGA code in block diagrams

I've briefly flirted with FPGA development in Verilog, and its admittedly somewhat slower than writing the same program on an MCU (defining pins, and their behaviour, no modules available, etc). I've ...
5
votes
0answers
111 views

Minimal redistributable coregen output for command-line rebuilds

I'm building an SoC with my own soft-core, and I want people to be able to easily rebuild it using Xilinx webpack command-line tools. I'm using coregen's Clock Wizard to create a clock module, but ...
0
votes
1answer
140 views

String manipulation in synthesisable Verilog

I am interested in implementing an ASCII-based communication protocol in Verilog for an FPGA. The communication protocol is FIX, and would require various string manipulations. What tools/libraries ...
2
votes
1answer
173 views

My design is not meeting timing. What can I do?

I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one. Now one isolated module in my design, which deals with ...
4
votes
3answers
1k views

What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24): To ...
4
votes
4answers
1k views

Using both edges of a clock

I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
2
votes
2answers
202 views

Merge a differential pair into one signal

I have an LVDS ADC connecting to an Altera Cyclone IV FPGA. The data pins come in 7 differential pair channels, for a total of 14 pins. Although each differential pair is physically 2 pins, my ...
3
votes
2answers
1k views

Verilog UART Transmitter Sends Bytes Out of Order

I have the following Verilog code which sends 8 bytes to the serial port successively after a button is pressed. The problem is, the bytes are sent out of order as to what I would expect. For ...
3
votes
1answer
224 views

Cyclone II FPGA Starter Kit Configuration Seems to be Giving Bogus Results

I've been trying to get my Cyclone II FPGA (from the Starter Kit, EP2C20) to work. I've gotten the Quartus II software to work on my Ubuntu setup and it' ALMOST working - I can write some Verilog, ...
-2
votes
2answers
501 views

FPGA or Microprocessor for Computer Vision based Robot for Indoor Navigation [closed]

I'm building an Indoor navigation robot which can be used in offices and factories especially in closed spaces with good lighting. I've already found out the algorithm i need to use for Indoor ...
3
votes
1answer
135 views

FPGA “physical view” visualiser with Verilog simulation

I find the 'Physical View' provided with most FPGA tools somewhat memorising for a complex design. Tens of thousands of switchboxes, LUTs, latches and multiplexers all configured mysteriously from the ...
1
vote
0answers
187 views

Any good tutorials for Altera DE2 with cyclone II? [closed]

Is there any good tutorials for verilog and the university board of altera DE2, I found this list, but are they any good video tutorials? or printed as well?
0
votes
1answer
72 views

What is the DONE_cycle startup option?

In ISE, it is possible to select various "Startup Options" for the generate FPGA image by right-clicking "Generate Programming File", selecting "Process Properties", and then clicking "Startup ...
1
vote
1answer
87 views

On the use of “BLOCK INTERCLOCKDOMAIN PATHS”

I based an FPGA design on Lattice reference code that, in the timing constraints .lpf file, specifies: ...
4
votes
2answers
218 views

Flip-flop vs combinatorial description - what exactly is the difference?

I was going through some reference design from Altera's Wiki and ran into the following piece of code: ...
3
votes
1answer
796 views

Birectional I/O pin in verilog

I'm wanting eventually to interface some memory to my fpga. This will require pins on the fpga that can both read data and write output to the ram. I'm far away from doing any of that yet, but as a ...
4
votes
5answers
306 views

Stress testing an FPGA's power supply

I have an FPGA (Xilinx Spartan 6) for which I want to stress test the power supply in "steps" (e.g. the FPGA runs in loops of 1 seconds: full steam for 900 ms, halted for 100 ms) to check that the ...
0
votes
1answer
169 views

Verilog: Pass a vector as a port to a module

I have two modules counter: Output is a vector called error_count. lcd: Module to display the code on an LCD. Input includes clock and error_count. Following snippet of the code is most relevant ...
1
vote
1answer
69 views

Verilog - syntax doubt

In an FPGA code, if I have something like the following: (* LOC="M18" *) output reg lcd_e; where lcd_e is an input/output port. Does this mean that I do ...
4
votes
2answers
282 views

how to implement a low pin count stereo display (FPGA)

I need to design a TX/RX pair which functions like a HDMI 1.4 3D, for a proprietary HUD. The source signals are 2 distinct TFT output in RGB， and the sinks are also two separate OLEDs, and a stereo ...
4
votes
3answers
325 views

Help wanted explaining signals coming with higher frequency than clock and how to handle them

I am getting my hands on Verilog and FPGA programming. So I wrote a simple module that handles two inputs - button signal and a clock. Initially, it lights up two LEDs and when the user presses and ...
3
votes
6answers
2k views

Random bit sequence using Verilog

I want to generate a random bit sequence using Verilog. i.e. the random bit sequence would be composed of 1 and 0. Can someone guide me as to how to do it? Does anything equivalent of rand() in C/C++ ...
1
vote
3answers
1k views

What is the I2C ACK, and how do I detect it?

I am writing an FPGA driver in Verilog for a temperature sensor (datasheet available here). The communication protocol is SMBus, a close cousin of I2C. Now reading the datasheet, I understand that the ...
3
votes
2answers
361 views

Dealing with bidirectional communication over 1 pin

I am writing a Verilog driver for a simple temperature sensor connected to an FPGA. (The temperature sensor datasheet is available here.) Communications occur over one pin, the ...
0
votes
1answer
429 views

Working with Spartan-6 LX9 clock

I am a novice in digital design and are learning things using "Advanced Digital Design with the Verilog HDL" along with a Spartan-6 LX9 board by Xilinx. So far I have managed to blink few leds on the ...
14
votes
2answers
671 views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...

1 2