Tagged Questions

0
votes
1answer
165 views

System generator frequency issue

I have a design in Xilinx system generator which meets maximum frequency of 50MHz (I found this from Timing and Power Analyzer of System generator). However, my FPGA board offers 100MHz clock rate. ...
2
votes
1answer
138 views

System Generator: a block similar to a three state logic

does anyone what is the xilinx block for getting a three state logic?
0
votes
1answer
293 views

System Generator: How to make an implementation a mathematical function through a ROM

I want to put in a ROM a vector of values I have in the workspace. Does anyone know how to do it? Thank you to all possible references, articles or comments.
0
votes
1answer
258 views

System Generator: a block to change sign of a floating point

I´m working with floating point numbers in System Generator. I need to perform this arithmetic operation y = x*(-1) . I think it could be done by using the mult block, but I don´t like this way ...
0
votes
2answers
217 views

System Generator: How to know if my FPGA could have enough resources to perform a design

I am doing a design using System Generator, and I have some doubts if my design could be performed in a Virtex 4 FPGA. Does anyone know what can I do to check this?
-1
votes
1answer
349 views

Choosing a tool for development: System Generator vs Xilinx ISE

I am trying to make a an implementation of a vhdl design. It´s an application for signal processing. Does anyone know what is the fastest development tool Xilinx System Generator or Xilinx ISE. Thank ...
1
vote
2answers
320 views

System Generator: How to configure the pins for the signals of your design?

I am programming a FPGA by System Generator. I have done this design: I don´t know what are the respectives pins of my FPGA for the blocks of my design called 'Gateway In' and 'Gateway Out'. I would ...
1
vote
1answer
438 views

System Generator: How to generate a .bit file?

I am using System Generator and I would like to generate a .bit file in order to load into my FPGA. Does anyone know how to generate a .bit file with SG? Thank you.
1
vote
1answer
588 views

System Generator: How to configure the CORDIC divider block?

He all, I was wondering how should be the parameters fo the CORDIC divider block in order to get proper results. In this example I´m trying to get 0.1/0.2 = 0.5 but I don´t get it and I don´t know ...