HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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What arguments to use to switch from graphical design entry (HDL)? [on hold]

I am an experienced FPGA designer with background in Information Technology and therefore used to GIT and Test Driven development for FPGA designs. Of course flow was automated by Make scripts, so ...
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0answers
30 views

I am trying to build a 4 bit squarer [duplicate]

I need some help with building a 4-bit squarer block diagram. Can anyone help me or know a link to a 4 bit squarer block diagram or a verilog code for it? Thanks in advance.
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62 views

I need some assistance on improving my Verilog code

Basically, I am using a lookup table to output in bcd the square of a single digit bcd. I need help on improving my code. So, when I input a number I get a square. But what I want to do is output the ...
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2answers
79 views

creating a bcd squarer using verilog

Basically, I am using a lookup table to output in bcd the square of a single digit bcd. The problem that I have is that it is not outputting the correct answer. For example: the result I get for the ...
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1answer
31 views

Multiplier 4-bit with verilog using just full adders

I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right. here's a pic to give you some idea of what i am ...
2
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1answer
57 views

Do I need a license to design IP cores with AXI interfaces?

Many IP cores especially from Xilinx have an AXI interface from ARM. (AXI, AXI-Lite, AXI-Stream, APB, ... are parts of AMBA - ARM's bus architecture). The AXI interface standard is free for download ...
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0answers
30 views

How can I connect two design units in modelsim simulation

Motivation: When I build a hardware component that consist of many sub components, then I need to test the sub components before I connect them all up and make a thorough testbench in VHDL. In some ...
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1answer
47 views

VHDL to Verilog conversion for Parking Sensor

I am trying to do parking sensor with verilog and I have its vhdl code and trying to translate it to verilog can you please help me to find out what is my problem. There is no error the error is only ...
3
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1answer
44 views

Converting Bin-to-BCD code from VHDL to Verilog

Hello guys I am trying to translate following VHDL code to Verilog, however it does not work even if they look like pretty same. I get no errors however it is not working with Verilog one but works ...
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3answers
88 views

Should HDL languages be taught before software languages? [closed]

I'm a Computer Engineering student and learned the basic sequential programming languages (C/assembly/Java) way before I was even introduced to HDLs. Thus, my whole programming logic was based upon ...
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1answer
51 views

Split a 512 bit numbers into 16 words of 32 bits using HDL [closed]

How to split a 512 bit binary number into 32 words of 16 bits using HDL?
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3answers
242 views

Pipeline vs Parallelism

Let's consider an algorithm (for instance encryption) that has 8 strictly identical steps (the output is used as input of the next step). Considering that I have enough resources to put 8 ...
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48 views

Altera “fiftyfivenm” and “twentynm” - What is that?

I know many Altera products from Arria, Cyclon, Stratix and co, but what are the: fiftyfivenm twentynm devices? I assume these are devices, because there are ...
0
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3answers
82 views

Linear Feedback Shift Registers on FPGA's

I want to put 256 linear feedback shift registers on a FPGA and each LFSR will have just two tap positions for the XNOR feedback and each register is 63 cells . I don't care if the LFSR'S are not ...
0
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1answer
47 views

Converting int to float and vice-versa in HDL

I am trying to write an HDL code for converting floating point numbers in IEEE-754 format to integers and vice-versa. For eg. ...
1
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1answer
61 views

How can I calculate Exponential using CORDIC for numbers outside [-1, 1]? [closed]

I am not able to understand the math behind calculating exponential of a number outside the range [-1, 1) (actually I am not sure what is a good range to compute exp using CORDIC, some place I read ...
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1answer
72 views

Unable to understand Verilog syntax

I found an example Verilog code as following: module test #(parameter p=1) (); localparam [1:0] lp = ~(p)'(1'b0); endmodule I'm unable to undestand the ...
3
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1answer
89 views

Can I implement a FM Radio Rx on the the Spartan 3E kit?

Can I implement a FM Radio Rx on the the Spartan 3E kit? Starting Problems I am facing- How do I interface the Antenna with the Spartan 3E kit? Implementing the A/D converter.
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0answers
45 views

2 bit Full Adder Code in Chisel HDL

I am new to Chisel HDL and would be glad to receive help regarding the following 2-bit adder program I wrote: ...
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0answers
58 views

What is the easiest/cheapest way to get relative ASIC area estimates from a HDL design?

I've been working on some HDL designs and testing them on an FPGA. I have various possible ways I can go with the design with differing tradeoffs between amount of logic, registers, and width/depth ...
2
votes
2answers
214 views

Why does my ALU design delay outputting the results for two clock cycles since input of valid data?

Hello EE StackExchange! I have been trying to design a simple 8-bit CPU for several months now. However, I am experiencing a problem: The ALU outputs the result of the operation two clock cycles ...
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1answer
133 views

systemverilog structure initialization with default = '1

Can someone shed light on what this SystemVerilog code should do: ...
0
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1answer
38 views

VHDL signal assignement

Is there any difference between : Type word is STD_logic_vector(15 downto 0) And Signal word:STD_logic_vector(15 downto 0) ...
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0answers
80 views

HDLcompiler warning189

I am new to xilinx and verilog and am trying some basic stuff when I got this error. I know we can define input and output bus sizes using parameters like parameter width = 32; output [width-1:0] ...
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2answers
417 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
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2answers
94 views

Tools used to manufacture entire digital systems

I am new to electronics and am trying to wrap my head around the various tools used for producing various digital components. My understanding of HDL languages like VHDL and Verilog is that they ...
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3answers
318 views

Asynchronous reset in verilog

I am new to verilog and having a bit of trouble getting along with it. I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am ...
2
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2answers
238 views

What are some things that can be done in VHDL but not in verilog and vice versa?

VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though. What are some things which are easier to do in VHDL but not so easy or even ...
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4answers
299 views

SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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3answers
89 views

Using FPGA specific hardware components when writing RTL

I have heard at times that someone writing a digital circuit design may want to use actual primitives present on the FPGA directly in the design. This means including the library which contains those ...
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2answers
282 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
3
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1answer
195 views

How to use IO Buffer with defined location in VHDL?

I am tring to program the ADF4158 PLL Synthesizer with SPARTAN 6 FPGA using Microboard LX9. I studied VHDL for a semster 4 years earlier, and no practical use after that. So I need some experts ...
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1answer
76 views

What is the definition of unsigned() function in VHDL?

I am unable to find the function signature of unsigned() function in vhdl. what types does it accept as an argument?
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1answer
456 views

What is the difference between a static and non-static expression in vhdl?

suppose if I have two signal declarations as follows signal x:std_logic_vector(1 downto 0) := (others => '0'); signal y:std_logic_vector(1 downto 0); does ...
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2answers
58 views

Verilog: Check, if a signal is 100 ticks active?

I have one input and one output. And I want to turn the output to 1, if the input was 100 ticks active (100 cycles). ...
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5answers
973 views

How do you design processors / microprocessor [ not broad ]

Apologies for this vague title, but my question is a little specific. I have two concerns : During my digital electronics class, I was told that the design of the processor is first carried on an ...
0
votes
1answer
114 views

Blocking and Nonblocking statements in same procedural block

Code module block; reg a; reg b = 1'b0; reg c = 1'b1; initial begin c = b; a <= c; end endmodule I simulated the code fragment shown in ...
4
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2answers
111 views

Secure signals on boot time to prevent unwanted operations

How can I be sure that at boot time my module won't get random values to it's control signals and write to an address* before I reset the module? *(or anything that shouldn't be done before reset) ...
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1answer
307 views

How can I read in an image in Verilog?

I have a .mif image that I want to encrypt in Verilog. To do so, I need to read the image into the program and store it in an array. The image would be 160 by 120 and I would like to store it in an ...
4
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2answers
278 views

How does someone initially design a digital system for HDL?

So I have really been hitting the example code hard this week in an attempt to better understand some HDL design basics, specifically FPGAs with VHDL. The book I am using (if anyone is interested) is ...
5
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4answers
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What's the motivation in using Verilog or VHDL over C?

I come from a programming background and not messed around too much with hardware or firmware (at most a bit electronics and Arduino). What is the motivation in using hardware description languages ...
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4answers
181 views

How is procedural code converted into a circuit?

With non-procedural code, the digital circuit the code represents is relatively obvious. However with procedural code, it's hard/impossible to see how it translates into a circuit. The only method I ...
5
votes
1answer
117 views

How appropriate are the open source licences currently in use for inclusion of HDL cores in a commercial product?

HDL IP cores targeted towards ASICs, FPGAs or both are often very useful for adding functionality to a project quickly. Commercially licences cores are available from many sources for a range of ...
2
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2answers
236 views

When is the concurrent signal assignment executed?

Having the next code: ...
6
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2answers
2k views

My serial receiver verilog implementation does not act as expected

I have coded my own implementation of a serial receiver. It will work for incoming data at a baud rate of 115200. Here's my code: ...
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2answers
282 views

How do I transmit an FM signal from the VGA_R port on the DE2-115?

The best reference for my question would be this youtube video: https://www.youtube.com/watch?v=4VW017qPT6Y I'm trying to do exactly what they did with the following resources: Matlab 2013a with ...
2
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1answer
595 views

How to reference subsets of logic[31:0] in SystemVerilog?

(I have two questions for you at the end.) I'm using SystemVerilog to do various exercises (for personal edification) in Digital Design and Computer Architecture's chapter 7. I'm using Altera's ...
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1answer
188 views

How is machine code handled by the microprocessor? [closed]

And no I don't mean "How do you write a program for a processor". What I want to know is how does a processor interpret some aribtrary instruction, say 100001 as ...
0
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1answer
95 views

High Level Language to HDL [closed]

I need to convert a simple program (C or Java) to HDL (especially Verilog). However, I have no idea about this conversion. Another problem is that the resulting code must be gate level. Now, This ...
0
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1answer
160 views

How to design a fair Synchronous Arbiter?

The problem i am facing is this, i need a Hardware circuit which decides fair between for example bus requests which happen at the same time. Example: A and B are the two components which do memory ...