HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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Verilog Concatenation Setting LED'sin casex

If I have a casex statement and I have something such as {`idle, `left}: {next, LED} = {`state1 ,`turn1liteON }; and LED corresponds to LEDR[7:0] and ...
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25 views

Synthing HDL down to waveform-testable format using Synopsys

I've worked a bit with the Quartus II toolset to create small systems that I could construct in Verilog and then test by applying a waveform. Then I could check the output against a Golden Waveform to ...
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2answers
96 views

When is the concurrent signal assignment executed?

Having the next code: ...
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320 views

My serial receiver verilog implementation does not act as expected

I have coded my own implementation of a serial receiver. It will work for incoming data at a baud rate of 115200. Here's my code: ...
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43 views

Shorthand for Multiple Chips in Nand to Tetris Hardware Simulator

In the Nand to Tetris course HDL, is there a way to handle many different chips without typing them out as below? Can it be done using the a[0..15] shorthand or in some similar fashion. Now, I'm just ...
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2answers
110 views

How do I transmit an FM signal from the VGA_R port on the DE2-115?

The best reference for my question would be this youtube video: https://www.youtube.com/watch?v=4VW017qPT6Y I'm trying to do exactly what they did with the following resources: Matlab 2013a with ...
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1answer
114 views

How to reference subsets of logic[31:0] in SystemVerilog?

(I have two questions for you at the end.) I'm using SystemVerilog to do various exercises (for personal edification) in Digital Design and Computer Architecture's chapter 7. I'm using Altera's ...
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1answer
153 views

How is machine code handled by the microprocessor? [closed]

And no I don't mean "How do you write a program for a processor". What I want to know is how does a processor interpret some aribtrary instruction, say 100001 as ...
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71 views

High Level Language to HDL [closed]

I need to convert a simple program (C or Java) to HDL (especially Verilog). However, I have no idea about this conversion. Another problem is that the resulting code must be gate level. Now, This ...
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1answer
79 views

How to design a fair Synchronous Arbiter?

The problem i am facing is this, i need a Hardware circuit which decides fair between for example bus requests which happen at the same time. Example: A and B are the two components which do memory ...
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1answer
130 views

How Verilog or VHDL projects are implement as physical chips?

In real life, how would I implement a circuit design using Verilog and VHDL as physical chip? Do I send the code to some third party so it manufactures the chip, like with PCB printing providers?
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1answer
141 views

Do I have to explicitly connect all pins of the ethernet chip in the FPGA when designing a new controller?

Regarding the Ethernet peripheral of the Spartan 3E FPGA specifically the SMSC LAN83C185 Ethernet chip. The task is to create our own interface between the PLB and the ethernet chip. So far, I've been ...
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164 views

Correct way to define propagation delays in VHDL

I'm currently learning VHDL. As an exercise I decided to implement some of the 7400 series chips. Below is the 74153 and while testing it with ghdl/gtkwave it seems to work. But I'm sure this ...
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3answers
141 views

Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?

I am synthesizing some multiplication units in Verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using Booth Encoding when ...
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3answers
338 views

Logic design for FPGAs using C

I am well aware about programming processors and microcontrollers in C. But can C code (not SystemC) be used for logic design for FPGAs? Are there any specific software tools for this purpose?
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1answer
132 views

Curious state transitions in state machine RTL simulation

I have a simple state machine as part of my Verilog module: ...
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2answers
70 views

Verilog - Weird blocking/nonblocking problem

In the rst block in the following code I get a strange error whenever I use non-blocking assignment/ The State_SENDSYNC last for two cycles even though it's supposed to only last one cycle. Changing ...
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1answer
216 views

How to use HDL designs in hobby circuits and how to do transistor level tuning [closed]

Please excuse the noobness. What is the process a lone (or few) individual can send an HDL design off to a fab (tools, file formats, potential fabs)? I have played around with FPGAs but I'm curious ...
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1answer
69 views

Grouping input and output signals with the corresponding clock

In my Verilog design, I have two asynchronous clocks, clk1 and clk2. Associated with each clock is a bunch of inputs and ...
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3answers
136 views

Timings constrains for isochronous clocks

In my Verilog design, I have two clocks of the same frequency, but of different phase. At the moment, my timing constraints look like this: ...
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2answers
1k views

RTL vs HDL? Whats the difference

What is the main difference between RTL and HDL? To be honest I searched / googled it yet people are divided in their opinions. I remember one saying that HDL is the computer language used to describe ...
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1answer
118 views

Adjustable clock in HDL

I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag - there is no need to recompile the code). ...
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1answer
169 views

3-phase lock loop in verilog

I want to implement a phase lock loop in verilog hdl. The input is the source voltage (which is a sine wave) and the output is theta(in terms of sin and cos).
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5answers
731 views

Mismatch between RTL-level simulation and post-synthesis simulation using xilinx xst

I have written a verilog code and RTL simulation is working fine. After this I synthesized the design using XST tool in Xilinx ISE 13.2. The post-synthesis simulation is showing some unexpected ...
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134 views

HDL Designer: What's the difference between a project and a library?

Which should I use? I'd like to use it to model circuits for homework and to possibly reuse parts circuits in other designs.
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3answers
821 views

Difference between RTL and Behavioral verilog

Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
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1answer
134 views

Processor - L1 Data cache interface

Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer: I'm ...
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3answers
254 views

VHDL Error (Simple Expression Expected)

I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the ...
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5answers
537 views

Simulating FPGA design without having the actual hardware

I'm new to FPGA and currently taking HDL (Verilog particularly) class. I have sufficient knowledge in digital design like combinational and sequential circuits. I want to create a project similar to ...
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2answers
330 views

Developing hardware in FPGA with LED Driver Chip

I asked related TI TLC5944 LED Driver questions here, here and here Actually initially I was supposed to simulate the following design. I had to simulate the driver functionality also (as the driver ...
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4answers
267 views

In which cases should I use Z as output in HDL?

I created a simple multiplexer which feeds different input into output depending on statemachine. Now there are states when I do not need the output so I usually set it to 0. ...
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1answer
422 views

What is backdoor memory access?

There is a term in HDL simulation/verification called "backdoor memory access". I've heard this a lot of times though I'm not sure how is this implemented. Also, there are a few references for this ...
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1answer
214 views

Simulating IBIS Model in modelSim

I am developing a logic in an FPGA that will act as a controller for a chip by TI. I got the TI chip IBIS model from the TI website. My controller is ready and I want to simulate it using ModelSim. ...
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2answers
162 views

Automating test vector in Verilog HDL

This is my first attempt at learning Verilog HDL testbench for an AND gate: ...
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1answer
61 views

What is the best way to understand a large existing HDL core?

Groundhog is a open source SATA host bus adapter core written in Verilog. I was wondering if anyone had tips on how to begin to understand how it operates? Is it to go from the high-level to ...
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2answers
221 views

Developing for an FPGA using Impulse C

I am considering using Impulse C to write C code that will compile down to HDL for my FPGA. I'm curious as to what experiences people have had with Impulse C, to better understand the advantages and ...
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2answers
2k views

What is a false path timing constraint?

In FPGA world, what exactly are false path constraints for an HDL compiler? Why are they useful?
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5answers
7k views

Why are inferred latches bad?

My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be ...
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3answers
292 views

Where is the software / hardware boundary in modern computer systems?

Computers are pogrammed in (and controlled by) software. That software is often run by other software (e.g. Java compiled into bytecode, run by a Java VM coded in machine instructions), which is in ...
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3answers
1k views

What happens when an FPGA is “programmed”?

From what I understand, the process of programming an FPGA comes in two parts: Encode the hardware description into bits that the FPGA can understand (i.e. write some HDL and compile it) Load the ...
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2answers
2k views

Verilog: Check for two negedges in always block

i try to do something like this: always @ (negedge speed_dec or negedge speed_inc) begin do something end This doesn't work as checking for 2 negative edges ...
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2answers
5k views

How to assign value to bidirectional port in verilog?

I'm trying to use a bidirectional port in Verilog so I can send a receive data through it. My problem is that when I try to assign a value to the port inside a task, but I keep getting an error. ...
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1answer
127 views

What was the motivation for making behavioral descriptions such a big part of Verilog?

I don't use Verilog for anything serious, but I use it in my classes, and I'm starting to think I must be missing something about the appeal of behavioral hardware description. When I write Verilog I ...
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9answers
13k views

VHDL or Verilog?

VHDL and Verilog are the HDLs of the day. What are the advantages of either for someone who has no experience with HDLs at all?
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432 views

recommandation webpage/book to learn asmd chart over using verilog

I have searched so many website to take background about how asm chart is used in verilog code.However, I could not find any web cite with sufficient examples to learn asm chart. Can anyone give or ...
2
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1answer
615 views

Is there a free/low-cost bus monitor in VHDL/Verilog for ARM AXI/AXI4 and/or AXI4-Stream protocols?

I am looking for something to log the read and writes on an AXI 4 bus to a file. And similar for AXI4-Stream. For what it is worth, this is for Xilinx. I could roll my own, but I hoped someone else ...
2
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1answer
369 views

How does Xilinx ISE determine compilation order?

Iā€™m working on a VHDL project which is a small SDRAM test. I have these entities: top sdramwrapper sdram <ā€“ generated IP core sdrampkg <ā€“ contains a package containing constants used several ...
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2answers
3k views

how to write output of the monitor to a file

I have a testbench and a verilog modules. I want to write ouput of the testbench to a file anmed as output.txt. While doing this job, I want to use $monitor. Is it possible ? If yes, can you give me ...
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1answer
210 views

What language is Cadence's Emanger *.ecom files written in?

I know this is a long shot but I thought I would ask while I am waiting for the FAE to get back to me. This is related to Cadence Verilog simulations and regressions. I am trying to debug an *.ecom ...
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2answers
293 views

System Generator: How to make a channel selector?

I want a system with two inputs,sel and in, and at least two outputs channel A and ...