HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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SystemVerilog Memory Addressing

Just to preface this I am new to HDL. I had a semester long course on it last year but we didn't cover buses or memory in enough detail. I have been modifying some System Verilog code I was give as a ...
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Verilog - creating a timer to count a second [duplicate]

I'm using a FPGA (BEMICROMAX10) to create a digital clock using seven segment displays on a breadboard, and I'm having issues getting the seconds to count exactly 1 second. The clock system input I'm ...
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31 views

Verilog 'cannot match operand(s)' & 'multiple constant drivers'

I'm working on a Verilog project using a FPGA (BEMICROMAX10) and some breadboard components. The project is to make a digital clock in which you can also set the time using the buttons on the FPGA. I ...
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Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing ...
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2answers
94 views

Correctly initialize a shift register (Verilog)

I've been struggling with a very simple Verilog program. It's a 4 bit shift register that gets rotated at every clock cycle and drives four LEDs. (As you can tell I'm new to FPAGs and HDLs.) The ...
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62 views

How can assign a synthesizable string to a byte array in SystemVerilog?

I want to initialize a byte array (or any other possible type) to a long string. For example define: string str = "abcdefg". I read these two links (1 & 2) but ...
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74 views

For loop in `define Macro

I searched on SO, and on web, no where found the ans. I have following code, where It success fully parsed `define and generate expected results, but if number of times calling of macro is large then, ...
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1answer
90 views

Dividing a clock in Verilog - is it OK?

Dividing a clock down in Verilog is a basic exercise, and there are loads of answers online about how to do it. What I want to know is whether it is OK to use a clock that has been divided down using ...
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52 views

Task doesn't work in verilog

I created a module that first sorts a byte array then choose last element as minimum.(just for practice). When I moved sort to the task block, it doesn't worked as well as before. How can use task ...
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36 views
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178 views

Different ways of using DSP slices in Spartan 6 FPGA

I am reading the Spartan 6 DSP slice user guide, and I need to use the DSP slice in a project of mine. I stumbled upon this question, which basically suggests 3 ways of using the DSP slices 1) ...
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32 views

Register for Headers in HDL

I have a protocol that has a header, to simplify code writing, I created a struct with the different header fields. ...
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2answers
68 views

What arguments to use to switch from graphical design entry (HDL)? [closed]

I am an experienced FPGA designer with background in Information Technology and therefore used to GIT and Test Driven development for FPGA designs. Of course flow was automated by Make scripts, so ...
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112 views

creating a bcd squarer using verilog

Basically, I am using a lookup table to output in bcd the square of a single digit bcd. The problem that I have is that it is not outputting the correct answer. For example: the result I get for the ...
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1answer
179 views

Multiplier 4-bit with verilog using just full adders

I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right. here's a pic to give you some idea of what i am ...
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1answer
116 views

Do I need a license to design IP cores with AXI interfaces?

Many IP cores especially from Xilinx have an AXI interface from ARM. (AXI, AXI-Lite, AXI-Stream, APB, ... are parts of AMBA - ARM's bus architecture). The AXI interface standard is free for download (...
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78 views

How can I connect two design units in modelsim simulation

Motivation: When I build a hardware component that consist of many sub components, then I need to test the sub components before I connect them all up and make a thorough testbench in VHDL. In some ...
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1answer
120 views

VHDL to Verilog conversion for Parking Sensor

I am trying to do parking sensor with verilog and I have its vhdl code and trying to translate it to verilog can you please help me to find out what is my problem. There is no error the error is only ...
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1answer
76 views

Converting Bin-to-BCD code from VHDL to Verilog

Hello guys I am trying to translate following VHDL code to Verilog, however it does not work even if they look like pretty same. I get no errors however it is not working with Verilog one but works ...
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3answers
103 views

Should HDL languages be taught before software languages? [closed]

I'm a Computer Engineering student and learned the basic sequential programming languages (C/assembly/Java) way before I was even introduced to HDLs. Thus, my whole programming logic was based upon ...
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57 views

Split a 512 bit numbers into 16 words of 32 bits using HDL [closed]

How to split a 512 bit binary number into 32 words of 16 bits using HDL?
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3answers
282 views

Pipeline vs Parallelism

Let's consider an algorithm (for instance encryption) that has 8 strictly identical steps (the output is used as input of the next step). Considering that I have enough resources to put 8 "step-...
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3answers
90 views

Linear Feedback Shift Registers on FPGA's

I want to put 256 linear feedback shift registers on a FPGA and each LFSR will have just two tap positions for the XNOR feedback and each register is 63 cells . I don't care if the LFSR'S are not ...
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73 views

Converting int to float and vice-versa in HDL

I am trying to write an HDL code for converting floating point numbers in IEEE-754 format to integers and vice-versa. For eg. ...
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1answer
95 views

How can I calculate Exponential using CORDIC for numbers outside [-1, 1]? [closed]

I am not able to understand the math behind calculating exponential of a number outside the range [-1, 1) (actually I am not sure what is a good range to compute exp using CORDIC, some place I read [-...
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1answer
80 views

Unable to understand Verilog syntax

I found an example Verilog code as following: module test #(parameter p=1) (); localparam [1:0] lp = ~(p)'(1'b0); endmodule I'm unable to undestand the ...
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1answer
100 views

Can I implement a FM Radio Rx on the the Spartan 3E kit?

Can I implement a FM Radio Rx on the the Spartan 3E kit? Starting Problems I am facing- How do I interface the Antenna with the Spartan 3E kit? Implementing the A/D converter.
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2answers
325 views

Why does my ALU design delay outputting the results for two clock cycles since input of valid data?

Hello EE StackExchange! I have been trying to design a simple 8-bit CPU for several months now. However, I am experiencing a problem: The ALU outputs the result of the operation two clock cycles ...
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621 views

systemverilog structure initialization with default = '1

Can someone shed light on what this SystemVerilog code should do: ...
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1answer
38 views

VHDL signal assignement

Is there any difference between : Type word is STD_logic_vector(15 downto 0) And Signal word:STD_logic_vector(15 downto 0) ...
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2answers
804 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, LEDG[0]...
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100 views

Tools used to manufacture entire digital systems

I am new to electronics and am trying to wrap my head around the various tools used for producing various digital components. My understanding of HDL languages like VHDL and Verilog is that they ...
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3answers
685 views

Asynchronous reset in verilog

I am new to verilog and having a bit of trouble getting along with it. I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am ...
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2answers
257 views

What are some things that can be done in VHDL but not in verilog and vice versa?

VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though. What are some things which are easier to do in VHDL but not so easy or even ...
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598 views

SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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3answers
105 views

Using FPGA specific hardware components when writing RTL

I have heard at times that someone writing a digital circuit design may want to use actual primitives present on the FPGA directly in the design. This means including the library which contains those ...
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2answers
383 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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1answer
248 views

How to use IO Buffer with defined location in VHDL?

I am tring to program the ADF4158 PLL Synthesizer with SPARTAN 6 FPGA using Microboard LX9. I studied VHDL for a semster 4 years earlier, and no practical use after that. So I need some experts ...
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87 views

What is the definition of unsigned() function in VHDL?

I am unable to find the function signature of unsigned() function in vhdl. what types does it accept as an argument?
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1answer
750 views

What is the difference between a static and non-static expression in vhdl?

suppose if I have two signal declarations as follows signal x:std_logic_vector(1 downto 0) := (others => '0'); signal y:std_logic_vector(1 downto 0); does ...
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2answers
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Verilog: Check, if a signal is 100 ticks active?

I have one input and one output. And I want to turn the output to 1, if the input was 100 ticks active (100 cycles). ...
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5answers
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How do you design processors / microprocessor [ not broad ]

Apologies for this vague title, but my question is a little specific. I have two concerns : During my digital electronics class, I was told that the design of the processor is first carried on an ...
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137 views

Blocking and Nonblocking statements in same procedural block

Code module block; reg a; reg b = 1'b0; reg c = 1'b1; initial begin c = b; a <= c; end endmodule I simulated the code fragment shown in ...
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2answers
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Secure signals on boot time to prevent unwanted operations

How can I be sure that at boot time my module won't get random values to it's control signals and write to an address* before I reset the module? *(or anything that shouldn't be done before reset) ...
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447 views

How can I read in an image in Verilog?

I have a .mif image that I want to encrypt in Verilog. To do so, I need to read the image into the program and store it in an array. The image would be 160 by 120 and I would like to store it in an ...
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2answers
324 views

How does someone initially design a digital system for HDL?

So I have really been hitting the example code hard this week in an attempt to better understand some HDL design basics, specifically FPGAs with VHDL. The book I am using (if anyone is interested) is "...
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6answers
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What's the motivation in using Verilog or VHDL over C?

I come from a programming background and not messed around too much with hardware or firmware (at most a bit electronics and Arduino). What is the motivation in using hardware description languages (...
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4answers
253 views

How is procedural code converted into a circuit?

With non-procedural code, the digital circuit the code represents is relatively obvious. However with procedural code, it's hard/impossible to see how it translates into a circuit. The only method I ...
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125 views

How appropriate are the open source licences currently in use for inclusion of HDL cores in a commercial product?

HDL IP cores targeted towards ASICs, FPGAs or both are often very useful for adding functionality to a project quickly. Commercially licences cores are available from many sources for a range of ...
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When is the concurrent signal assignment executed?

Having the next code: ...