High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.

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Via fences or pickets important parameters for design

What is more important for EMI shielding effectiveness with respect to guard traces and via fences, the width of the copper trace that circles around the area or the distance between the vias to ...
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32 views

Affordable burst >1000 FPS GigE Vision Camera with 1920 x 1080 resolution [closed]

we are trying to find a monochrome digital camera connected to GigE (preferable via GigE Vision) with a very high frame rate at a resolution of 1920 x 1080 or higher. Of course, such a frame rate is ...
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1answer
209 views

PCIe, diagnosing and improving an eye diagram

I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector). The root ...
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1answer
35 views

How do I determine if the clock signal suffers from high speed effects

I need to determine if the clock signal inside a multichip module shall suffer from high speed effects i.e reflection and ringing. I have: (1) IBIS models of the components inside the multi-chip ...
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24 views

How to carry out signal integrity simulation with IBIS models

I need to determine if there will be high speed effects on the clock signal. I have not done such a simulation before. I have the IBIS models of the circuit components involved. I think I still need ...
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405 views

Making prototypes with high speed SMD components

Even today we have breadboard and strip board on which one can make "quick and dirty" circuits and also test prototypes. However, we have now moved into an era of predominantly surface mount ...
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71 views

high speed ADC interfacing

now I'm pretty lost , recently I've taken it upon myself to try build an oscilloscope for fun. I want to do it with high speed ADCs (unless anyone knows of a better way?) I'm hoping for about ...
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2answers
711 views

Trace Length Tolerance Calculation - High Speed PCB Design

I have to interface a video format converter with a ADC IC, which converters RGB analog data to digital. The connection between this ADC and Converter is a 20 bit data bus which clocks at about ...
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1answer
67 views

High-speed clock line crossing under data lines

I'm interfacing an SDI video de-serializer with an HDMI transmitter. The de-serializer splits the video signal into 20 parallel lines and one clock line. Because the digital video data is high speed ...
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376 views

Precision high speed peak detector

As a follow-up to my previous question, where I seek to determine the amplitude of a 2 MHz sine wave, I've settled for an op amp based solution. To recall, my input has a maximum 240 mV amplitude -- ...
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1answer
50 views

fast 5v High Side switch controlled bz 3.3v

For my led cube, I need to switch 5V (common anode layers) with 3.3v (pic32). This should happen at a high frequency. In recent builds I used pfets, but because I'm using 3.3v now, a pfet wouldn't ...
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57 views

the thick copper trace

I need your help to find the answer for 2 questions: What is exact name of the golden trace in the red area? What is its purpose, and how to draw it in the PCB Thanks for your help
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1answer
196 views

PCB data trace lengths tolerable difference for high frequency

I have to interface a camera to a controller using the DCMI protocol for my project. I have around 17 (data+control) lines which are used with the camera. The frequency of operation is about 10 MHz. ...
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108 views

Looking for a high speed, high powered motor [closed]

So I'm trying something that has been attempted before and that is to have an electric turbo charger. essentially the goal is to spin a compressor wheel (20 grams) at 150k RPMS and sustain it for ...
4
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1answer
435 views

Why don't I need to consider trace width for a high speed oscillator crystals?

I have followed some reference designs that uses crystals like 40 MHz for the MCU, and I have not considered the trace width to do impedance matching. The result is that the boards works fine (I kept ...
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1answer
57 views

Isolation spacing in CPW-G

Is there any thumb of rules how to determine optimum spacing (marked with S below) for a RF signal (@2.45 GHz) on Coplanar Waveguide with ground (CPW-G)?
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116 views

Discrete MOSFET driver control IC

I am building a Marx bank, which consists of multiple MOSFETs connected in parallel when charging and in series when discharging. I have each stage of the pulse generator designed, including isolated ...
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2answers
261 views

Under what conditions does an optocoupler work fastest?

I want to use the optocoupler FODM452R2 in my design. I want this optocoupler to run as fast as it can (i.e.; work with minimum propagation delay and least rise/fall times). What is the optimum R1, R2 ...
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2answers
246 views

Is it possible to use capacitor for isolation instead of optocoupler?

I designed a Buck converter which drives several LEDs. The PWM signal, which has a certain fixed duty cycle, is generated by a 555 timer IC. The circuit which drives the Buck MOSFET, including the ...
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2answers
183 views

Complexity involved in building a single board computer [closed]

Our high school has tasked my and a friend of mine with with building a web connected controller for a hydroponics system. The school has budgeted 5k for us to spend as we like, and we are intent on ...
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1answer
65 views

Current-Mode Logic Explanation

I was reading about the HDMI standard and therefore the CML logic, and some alegations are not clear for me about the advantages of the CML. One of its advantages is the low output voltage swing, so ...
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2answers
427 views

I2C at 2.4 MHz with five microcontrollers over 2 meters

I have five Teensy 3.1 and I would like to interface them with I2C running at 2.4 MHz. The maximum Line Length will be around 2 meters. Will it work? What's the best way I can wire this up? ...
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1answer
357 views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...
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135 views

660 Mbits per second photo-diode amplifier on 3.3V rail

I've got a 10mW laser diode that can transmit at 660 Mbits per second, I've got the laser driver circuit that can do this, I've got a photodiode from Hamamatsu that looks good for this speed (-3 dB ~1 ...
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2answers
83 views

CML signal to ground terminated line or peak sensing ADC for short pulse

I'm currently designing the prototype of a timing instrument. One sensor gives an analog CML (current-mode logic) signal, from an amplifier (ADN2880). One end of the pair is routed to a comparator ...
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71 views

Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...
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156 views

Calculating Signal Loss (dB) Through Vias

Does anyone have any useful calculations or links to material covering good ways to calculate signal loss through vias? What would be perfect is a graph with typical loss in dB over the range 1GHz ...
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1answer
187 views

Distributing a 40MHz clock to several PCBs

I need to run four PCBs with a very accurately synchronised clock. The source clock is 40MHz, but each PCB contains a 1GHz PLL, and will be timing events in the analogue domain with a final ...
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3answers
3k views

Max switching frequency of GPIO pins of modern cheap FPGA

How can we estimate maximum switching frequency of GPIO FPGA pins? What is maximum data rate achievable when connecting two FPGAs together without using of integrated high-speed transceivers? Or when ...
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567 views

Terminating shielded/screened twisted pair correctly

Theoretically, I can't see a problem if the twisted pair has an end of cable termination that is: - A single resistor (R) that matches the characteristic impedance of the cable placed across the two ...
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1answer
3k views

How to select an appropriate capacitor for input voltage stabilization

I have a design where I have some high speed ICs and need to put a capacitor on the input voltage line to stabilize the voltage and protect from spikes or dips. I am operating at 5v and between 300 ...
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0answers
185 views

What are the limitations, if any, of free EDA tools with respect to high speed design?

I've read this excellent post by Some Hardware Guy, and I'm aiming toward something similar to what OP was doing which is a Beagleboard derivative. I've done some more research and it seems that ...
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1answer
218 views

SMA to rp-SMA cable selection

I need to buy a 6-7m long SMA to rp-SMA cable to connect a Wifi radio unit (2.4 GHz and U.FL connector) and an external antenna ...
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1answer
437 views

How does this Logic Analyser front end work?

Hi I was reading on EEVBlog, some guy has reverse engineered the Logic Analyzer within the new Hantek MSO5102D MSO. I had a question about the front end part: This is a 4-channel section of the ...
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122 views

Analysing Signal quality through pogo pins using Hyperlynx

I have successfully modeled Linesim and boardsim schematics for quite a few designs in the past and we have been able to do the required SI simulations. I had one question though: On one of our ...
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1answer
234 views

How exactly do all FPGAs work together on this board to carry out high speed calculations

The board I am referring to is called "Merrick 3" from "Enterpoint (ltd)". The web page can be found here: http://enterpoint.co.uk/products/asic-development-high-performance-computing/merrick-3/ I ...
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272 views

How does less cable impedance, source/termination impedance, lead to longer cable length for higher data rates?

This question is about high speed digital transmission on a transmission line, I need to know about how does the (1) impedance of the transmission line and the (2) source impedance and (3) ...
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823 views

Ground vias on high speed PCBs

I know that if I use vias on high speed traces that I need to reduce the inductance effect of the via. So I will put ground vias next to these vias to help returning current. I have seen a picture ...
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2answers
2k views

Implementing a very high frame rate (~1Khz) OLED display

I'm interested in developing a very high frame rate OLED display capable of displaying ~1000fps with a resolution of around 1200x800 or so. This obviously has some pretty severe bandwidth ...
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3answers
337 views

Has anyone transmitted data across a badly coupled transformer and recovered the data correctly

EDITED June 9th 2013 to give more detail (hopefully) I've recently set-up a data transmission system on a rotating machine. The data was collected and serialized from several ADCs connected to strain ...
5
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3answers
2k views

PIC problem: Touching the crystal capacitor makes the system slows down

I am experiencing a very unusual problem (at least for me). When I touch with my fingers, or the oscilloscope probes, on the crystal or it's capacitors, the PIC runs slower...and A LOT slower then it ...
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2answers
350 views

ARM (Cortex-A8) High Speed Bus?

I need to communicate from FPGA to ARM with about 16GBits/s... Is there a Bus which I can use? Or how to solve this problem? The FPGA receives data over LVDS. This data schould be post-processed in ...
5
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2answers
185 views

Can I slow a CMOS output through an RC filter?

Is it good practice to slow down the slew rate of a CMOS output by putting an RC filter on it? What happens with impedance matching after I do this? Or can I just set the RC filter with such a low ...
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743 views

Boundary scan - High speed interfaces

I was given the task to evaluate existing boundary scan systems. At this moment, we are using a simple solution which allows us to define boundary scan vectors which we can check. This is fine for ...
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4answers
2k views

USB differential pair length

I am routing a PCB that uses a USB connection. The differential pair traces are 10 mil distant from each other, and they are about 1mm different in length. Is it going to be a problem? What is the ...
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2answers
444 views

How should we account for the length of series termination resistors for length matching?

In some cases, we need to length match several different nets between two ICs, based on the specifications of the driving or receiving IC. Sometimes, some of these nets have a series termination ...
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3answers
3k views

Question about trace length matching patterns for high speed signals

A colleague and I had a discussion and a disagreement about the different ways high speed signals can be length-matched. We were going with an example of a DDR3 layout. All the signals in the ...
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2answers
893 views

3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?

I need to run a 3.2 Gb/s interface over 50m. My client is keen on Cat6e. The lower the price, the better. These are my findings so far: I'm looking at using a Spartan 6 GTP Tranceiver with copper ...
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1answer
3k views

2-layer USB 2.0 High-Speed routing

First off: This is for a one-off (or two-off) hobby project, nothing more serious. If this were a commercial design, I would go 4-layer at once (though I wouldn't be designing such a project in the ...
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329 views

Hyperlynx Boardsim for multiboard design

I have used 'linesim' in hyperlynx before for evaluating PCIe and other high speed devices using respective IBIS models. However, for our new project, we have a system where say 'Board 1' has a SOC ...