High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.

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19
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2answers
2k views

Why would you stack a resistor and capacitor on top of each other?

I've inherited an charge amplifier/shaping circuit from my predecessor. When he wanted to make a low-pass filter with current-to-voltage conversion, he had a standard circuit like: simulate ...
2
votes
3answers
106 views

How to choose trace width for very high current PCB?

I am currently designing a PCB layout for my team's high current, high voltage project and am having trouble with choosing my trace width. The circuit is composed of 12 inductors placed in series ...
2
votes
1answer
69 views

Help on defining the 8-layer stack-up for a high speed design

In many of the PCBs of my company we have done the stack-up as following: (stack-up A) Pads/GND/Some LF signals Signal1 Signal2 GND plane PWR planes (more than one due to several secondary supplies ...
0
votes
1answer
38 views

IBIS model of capacitors

I have started the design of a high speed digital design multi-gbps interfaces. I would like to use Altium designer for PCB analysis (signal integrity). But I am wondering if altium uses the IDEAL ...
0
votes
1answer
44 views

How to reduce a pulse voltage maintaining a high impedance?

I have one pulse with 200ns and 60 V. I have to reduce this voltage until 10 V min because of the monostable multivibrator. After this, I will extend the pulse with a monostable multivibrator and then ...
0
votes
0answers
29 views

Extending the length of MIPI D-PHY

I have several devices which use MIPI's D-PHY standard, limiting the data transmission length to ~25cm on a standard FR4 PCB with a reasonable trace thickness -- however, I need to transfer this data ...
0
votes
0answers
66 views

How to create a control loop using a 100Msps digital signal as input

I would like to know what type of microcontroller should I buy for this control loop task. Scenario: I have a digital signal coming from the following equipment: UPDATE ::::: Ultrasonic ...
1
vote
0answers
87 views

How to network hundreds of sensors over a serial connection?

So I'm looking for a way to connect hundreds (300-400) sensors (like an accelerometer) together over a serial connection to a micro-controller. The sensors would transmit about 500kbps each. I've ...
0
votes
1answer
59 views

when do we need to apply high speed PCB rules ?

i'm new to pcb design and i'm wondering that starting from which frequency range we need to apply the high speed PCB design rules and techniques ?
3
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1answer
70 views

can high speed memory interfaces like GDDR5 or XDR ever become mainstream?

Given the limited memory on GPUs, I'm wondering why there are no socketed GDDR5 memory modules so that you can install more RAM. The main challenge seems to be maintaining signal integrity since ...
0
votes
1answer
50 views

Radio data transfer too slow [closed]

I need to send data from a camera recorder to a pc. The camera is about 1024/1000 pixels with 15 fps. Now the transmission distance should be at least 100 meters so I'm trying to use radio, but i ...
8
votes
1answer
286 views

How to construct High Speed Log Amplifiers

Objective : converting laser pulses from photo diode ranging from 10nA - 100mA to digital format, for measuring pulse width exactly pulse width 10ns-150ns and repeating at a rate of >20us up to ...
0
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2answers
95 views

Why is a reference plane needed in differential signalling?

As I understand differential signaling, return current goes via the "-" (minus) line, so why we do we need to provide a reference ground plane for differential signals?
0
votes
1answer
104 views

Lattice MachXO3L: MIPI CSI2 bridge

I would like to design a MIPI CSI2 bridge with a MachXO3L. I leverage the LVDS25 input/output of this FPGA family with the adequate resistors for HS traffic. (I think) I don't care about LP as the ...
3
votes
3answers
255 views

CAN bus layout design

I am trying to design a CAN bus node. The CAN bus shall be split-terminated with 120Ohm, 60Ohm for each line. Therefore i tried using this paper to calculate a characteristic impedance of 60Ohm for a ...
0
votes
0answers
40 views

difference between rising and falling time from the pulse response of transmission line

Attached is output pulse response of a transmission line (s-parameter). In the high-speed serial link design, we usually see more # of post-cursur ISI than pre-cursor ISI. One of the main reason is ...
0
votes
1answer
189 views

Which interface to choose SPI MIPI or Parallel?

I'm trying to connect the AR sensor module (AR0331) with the IMX6 processor and the problem is the camera uses a HiSPI & parallel line. Similarly, there is MI-PI (CSI) and Parallel line in the ...
0
votes
1answer
86 views

Using IR21531 as a simple 1 channel gate driver

I've bought the only gate driver I've found on the local hardware store (IR21531). I want to use it only to drive a IRF630 with a PWM 3.3V signal. How should I do the wiring? As you can see on the ...
4
votes
1answer
220 views

Buffer for 5V, 500ps to 10 ns pulses

I am trying to make a buffer for short, 5V pulses. The pulses are negative (form 5 to 0 V) and last for 500 ps to 10 ns (Half maximum, full width). The load is capacitive, around 50pF, and as close as ...
2
votes
1answer
154 views

No driver IC on net in Hyperlynx problem

I am getting the 'no driver IC on net' problem in Hyperlynx signal integrity software. Does anyone have any idea bout it? This is my PCB: It has an SMD connector and an AD9767 DAC. I have added the ...
4
votes
1answer
153 views

High-Speed PCB Design - Routing on Power Plane Layer?

I am working on designing my first high-speed PCB with 4 layers (in order): Top Layer: Single-ended/TTL signals Internal Layer 1: Power Plane (3.3V) Internal Layer 2: Ground Plane Bottom Layer: ...
5
votes
1answer
131 views

Aternative diode classes for high frequency(10GHz) applications

I'm trying to design a voltage clamping circuit for a 10GHz signal. I've modeled it in spice using several schottky diodes and it works but only when the signal pulse is at least a few nanoseconds ...
6
votes
2answers
727 views

What are these small stubs on the USB data pins of this device?

When disassembling a failing USB 2.0 flash drive, I noticed a feature on the USB data pins, that I do not understand from the perspective of a student just getting started with PCB layout: They're ...
0
votes
1answer
52 views

How to create a single line model (SLM), multi line model (MLM) and/or IBIS model of an interconnect for simulation?

I want to create a single line model, multi line model and/or IBIS model of an interconnect for simulation in Hyperlynx software but can't understand how to do it when the manufacturer has given no ...
1
vote
1answer
211 views

Duplicate MIPI CSI2 camera (one camera, two receivers)

I would like to feed two processors with the same MIPI CSI2 camera. I cannot afford to have one of the processors to play the role of proxy to the other. Though I searched hard, I'm not aware of any ...
3
votes
1answer
134 views

What references cover DDR3 layout considerations?

I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that ...
0
votes
4answers
129 views

High Speed Op-Amp recommendation [closed]

I am tasked with the issue of driving an IC that wants 5V input signals from an FPGA (3.3V outputs). Now, the most daunting part of it is the slew-rate requirements, with rise time \$t_r = 1.5 \text{...
0
votes
3answers
134 views

Via fences or pickets important parameters for design

What is more important for EMI shielding effectiveness with respect to guard traces and via fences, the width of the copper trace that circles around the area or the distance between the vias to ...
15
votes
1answer
581 views

PCIe, diagnosing and improving an eye diagram

I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector). The root ...
0
votes
1answer
70 views

How do I determine if the clock signal suffers from high speed effects

I need to determine if the clock signal inside a multichip module shall suffer from high speed effects i.e reflection and ringing. I have: (1) IBIS models of the components inside the multi-chip ...
0
votes
0answers
128 views

How to carry out signal integrity simulation with IBIS models

I need to determine if there will be high speed effects on the clock signal. I have not done such a simulation before. I have the IBIS models of the circuit components involved. I think I still need ...
3
votes
3answers
822 views

Making prototypes with high speed SMD components

Even today we have breadboard and strip board on which one can make "quick and dirty" circuits and also test prototypes. However, we have now moved into an era of predominantly surface mount ...
6
votes
2answers
5k views

Trace Length Tolerance Calculation - High Speed PCB Design

I have to interface a video format converter with a ADC IC, which converters RGB analog data to digital. The connection between this ADC and Converter is a 20 bit data bus which clocks at about 170MHz....
2
votes
2answers
204 views

High-speed clock line crossing under data lines

I'm interfacing an SDI video de-serializer with an HDMI transmitter. The de-serializer splits the video signal into 20 parallel lines and one clock line. Because the digital video data is high speed (...
3
votes
2answers
2k views

Precision high speed peak detector

As a follow-up to my previous question, where I seek to determine the amplitude of a 2 MHz sine wave, I've settled for an op amp based solution. To recall, my input has a maximum 240 mV amplitude -- ...
0
votes
1answer
77 views

fast 5v High Side switch controlled bz 3.3v

For my led cube, I need to switch 5V (common anode layers) with 3.3v (pic32). This should happen at a high frequency. In recent builds I used pfets, but because I'm using 3.3v now, a pfet wouldn't ...
1
vote
2answers
58 views

the thick copper trace

I need your help to find the answer for 2 questions: What is exact name of the golden trace in the red area? What is its purpose, and how to draw it in the PCB Thanks for your help
3
votes
1answer
353 views

PCB data trace lengths tolerable difference for high frequency

I have to interface a camera to a controller using the DCMI protocol for my project. I have around 17 (data+control) lines which are used with the camera. The frequency of operation is about 10 MHz. ...
0
votes
2answers
121 views

Looking for a high speed, high powered motor [closed]

So I'm trying something that has been attempted before and that is to have an electric turbo charger. essentially the goal is to spin a compressor wheel (20 grams) at 150k RPMS and sustain it for ...
4
votes
1answer
559 views

Why don't I need to consider trace width for a high speed oscillator crystals?

I have followed some reference designs that uses crystals like 40 MHz for the MCU, and I have not considered the trace width to do impedance matching. The result is that the boards works fine (I kept ...
0
votes
1answer
116 views

Isolation spacing in CPW-G

Is there any thumb of rules how to determine optimum spacing (marked with S below) for a RF signal (@2.45 GHz) on Coplanar Waveguide with ground (CPW-G)?
2
votes
2answers
1k views

Under what conditions does an optocoupler work fastest?

I want to use the optocoupler FODM452R2 in my design. I want this optocoupler to run as fast as it can (i.e.; work with minimum propagation delay and least rise/fall times). What is the optimum R1, R2 ...
1
vote
2answers
581 views

Is it possible to use capacitor for isolation instead of optocoupler?

I designed a Buck converter which drives several LEDs. The PWM signal, which has a certain fixed duty cycle, is generated by a 555 timer IC. The circuit which drives the Buck MOSFET, including the 555,...
0
votes
2answers
222 views

Complexity involved in building a single board computer [closed]

Our high school has tasked my and a friend of mine with with building a web connected controller for a hydroponics system. The school has budgeted 5k for us to spend as we like, and we are intent on ...
0
votes
1answer
85 views

Current-Mode Logic Explanation

I was reading about the HDMI standard and therefore the CML logic, and some alegations are not clear for me about the advantages of the CML. One of its advantages is the low output voltage swing, so ...
0
votes
2answers
678 views

I2C at 2.4 MHz with five microcontrollers over 2 meters

I have five Teensy 3.1 and I would like to interface them with I2C running at 2.4 MHz. The maximum Line Length will be around 2 meters. Will it work? What's the best way I can wire this up? ...
6
votes
1answer
579 views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...
5
votes
2answers
171 views

660 Mbits per second photo-diode amplifier on 3.3V rail

I've got a 10mW laser diode that can transmit at 660 Mbits per second, I've got the laser driver circuit that can do this, I've got a photodiode from Hamamatsu that looks good for this speed (-3 dB ~1 ...
2
votes
2answers
104 views

CML signal to ground terminated line or peak sensing ADC for short pulse

I'm currently designing the prototype of a timing instrument. One sensor gives an analog CML (current-mode logic) signal, from an amplifier (ADN2880). One end of the pair is routed to a comparator (...
2
votes
0answers
114 views

Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...