High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.

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Complexity involved in building a single board computer [closed]

Our high school has tasked my and a friend of mine with with building a web connected controller for a hydroponics system. The school has budgeted 5k for us to spend as we like, and we are intent on ...
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46 views

Current-Mode Logic Explanation

I was reading about the HDMI standard and therefore the CML logic, and some alegations are not clear for me about the advantages of the CML. One of its advantages is the low output voltage swing, so ...
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157 views

I2C at 2.4 MHz with five microcontrollers over 2 meters

I have five Teensy 3.1 and I would like to interface them with I2C running at 2.4 MHz. The maximum Line Length will be around 2 meters. Will it work? What's the best way I can wire this up?
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200 views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...
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93 views

660 Mbits per second photo-diode amplifier on 3.3V rail

I've got a 10mW laser diode that can transmit at 660 Mbits per second, I've got the laser driver circuit that can do this, I've got a photodiode from Hamamatsu that looks good for this speed (-3 dB ~1 ...
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2answers
61 views

CML signal to ground terminated line or peak sensing ADC for short pulse

I'm currently designing the prototype of a timing instrument. One sensor gives an analog CML (current-mode logic) signal, from an amplifier (ADN2880). One end of the pair is routed to a comparator ...
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49 views

Close Vias cause a Signal problem on high speeds?

I have designed a 4-layer board (signal + GND + PWR + signal). Have an SDRAM (using it about 80MHz). My stack up is: ...
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48 views

Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...
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1answer
83 views

Calculating Signal Loss (dB) Through Vias

Does anyone have any useful calculations or links to material covering good ways to calculate signal loss through vias? What would be perfect is a graph with typical loss in dB over the range 1GHz ...
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1answer
133 views

Distributing a 40MHz clock to several PCBs

I need to run four PCBs with a very accurately synchronised clock. The source clock is 40MHz, but each PCB contains a 1GHz PLL, and will be timing events in the analogue domain with a final ...
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3answers
1k views

Max switching frequency of GPIO pins of modern cheap FPGA

How can we estimate maximum switching frequency of GPIO FPGA pins? What is maximum data rate achievable when connecting two FPGAs together without using of integrated high-speed transceivers? Or when ...
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387 views

Terminating shielded/screened twisted pair correctly

Theoretically, I can't see a problem if the twisted pair has an end of cable termination that is: - A single resistor (R) that matches the characteristic impedance of the cable placed across the two ...
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2k views

How to select an appropriate capacitor for input voltage stabilization

I have a design where I have some high speed ICs and need to put a capacitor on the input voltage line to stabilize the voltage and protect from spikes or dips. I am operating at 5v and between 300 ...
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132 views

What are the limitations, if any, of free EDA tools with respect to high speed design?

I've read this excellent post by Some Hardware Guy, and I'm aiming toward something similar to what OP was doing which is a Beagleboard derivative. I've done some more research and it seems that ...
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1answer
137 views

SMA to rp-SMA cable selection

I need to buy a 6-7m long SMA to rp-SMA cable to connect a Wifi radio unit (2.4 GHz and U.FL connector) and an external antenna ...
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1answer
334 views

How does this Logic Analyser front end work?

Hi I was reading on EEVBlog, some guy has reverse engineered the Logic Analyzer within the new Hantek MSO5102D MSO. I had a question about the front end part: This is a 4-channel section of the ...
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95 views

Analysing Signal quality through pogo pins using Hyperlynx

I have successfully modeled Linesim and boardsim schematics for quite a few designs in the past and we have been able to do the required SI simulations. I had one question though: On one of our ...
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1answer
204 views

How exactly do all FPGAs work together on this board to carry out high speed calculations

The board I am referring to is called "Merrick 3" from "Enterpoint (ltd)". The web page can be found here: http://enterpoint.co.uk/products/asic-development-high-performance-computing/merrick-3/ I ...
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212 views

How does less cable impedance, source/termination impedance, lead to longer cable length for higher data rates?

This question is about high speed digital transmission on a transmission line, I need to know about how does the (1) impedance of the transmission line and the (2) source impedance and (3) ...
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2answers
427 views

Ground vias on high speed PCBs

I know that if I use vias on high speed traces that I need to reduce the inductance effect of the via. So I will put ground vias next to these vias to help returning current. I have seen a picture ...
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2answers
1k views

Implementing a very high frame rate (~1Khz) OLED display

I'm interested in developing a very high frame rate OLED display capable of displaying ~1000fps with a resolution of around 1200x800 or so. This obviously has some pretty severe bandwidth ...
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3answers
295 views

Has anyone transmitted data across a badly coupled transformer and recovered the data correctly

EDITED June 9th 2013 to give more detail (hopefully) I've recently set-up a data transmission system on a rotating machine. The data was collected and serialized from several ADCs connected to strain ...
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PIC problem: Touching the crystal capacitor makes the system slows down

I am experiencing a very unusual problem (at least for me). When I touch with my fingers, or the oscilloscope probes, on the crystal or it's capacitors, the PIC runs slower...and A LOT slower then it ...
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307 views

ARM (Cortex-A8) High Speed Bus?

I need to communicate from FPGA to ARM with about 16GBits/s... Is there a Bus which I can use? Or how to solve this problem? The FPGA receives data over LVDS. This data schould be post-processed in ...
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164 views

Can I slow a CMOS output through an RC filter?

Is it good practice to slow down the slew rate of a CMOS output by putting an RC filter on it? What happens with impedance matching after I do this? Or can I just set the RC filter with such a low ...
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508 views

Boundary scan - High speed interfaces

I was given the task to evaluate existing boundary scan systems. At this moment, we are using a simple solution which allows us to define boundary scan vectors which we can check. This is fine for ...
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4answers
1k views

USB differential pair length

I am routing a PCB that uses a USB connection. The differential pair traces are 10 mil distant from each other, and they are about 1mm different in length. Is it going to be a problem? What is the ...
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356 views

How should we account for the length of series termination resistors for length matching?

In some cases, we need to length match several different nets between two ICs, based on the specifications of the driving or receiving IC. Sometimes, some of these nets have a series termination ...
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Question about trace length matching patterns for high speed signals

A colleague and I had a discussion and a disagreement about the different ways high speed signals can be length-matched. We were going with an example of a DDR3 layout. All the signals in the ...
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2answers
688 views

3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?

I need to run a 3.2 Gb/s interface over 50m. My client is keen on Cat6e. The lower the price, the better. These are my findings so far: I'm looking at using a Spartan 6 GTP Tranceiver with copper ...
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1answer
2k views

2-layer USB 2.0 High-Speed routing

First off: This is for a one-off (or two-off) hobby project, nothing more serious. If this were a commercial design, I would go 4-layer at once (though I wouldn't be designing such a project in the ...
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257 views

Hyperlynx Boardsim for multiboard design

I have used 'linesim' in hyperlynx before for evaluating PCIe and other high speed devices using respective IBIS models. However, for our new project, we have a system where say 'Board 1' has a SOC ...
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3k views

Lengthening a 5 ns pulse

I have a 5 ns pulse width High coming out of a comparator that is asynchronous. I am attempting to count this pulse. My current microcontroller (dsPIC33FJ) has an asynchronous counter on board, ...
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2answers
1k views

Maximum input frequency of 74HC Logic gates

I have a clock that is running at 25.175MHz I want to run that signal through some basic logic gates from the 74HC series. I have looked on the datasheet for the 74HC08 (AND Gate), I can't seem to ...
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1answer
826 views

Does the TI CC2540 support Bluetooth High Speed protocol?

The Bluetooth High Speed (HS) protocol is included in the Bluetooth 4.0 spec, but I can't find whether or not standard Bluetooth 4.0 modules such as the TI CC2540 support the high speed part of the ...
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172 views

Ultra high bandwidth serial data stream

I have a ultra high bandwidth data stream (USB 2.0 Highspeed), on which I need to add an header for synchronization. This needs to be done, since the datastream needs to be transmitted wireless on a ...
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237 views

Cheap high speed oscillator [closed]

What is the fastest oscillator I can build for less than $1 in parts ? Further specifications: SMT only Pricing for Quantity 1000 Stable frequency Sine wave preferable I don't care too much what ...
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1answer
779 views

What is ground bounce?

From David's comment to this answer I understand that it's an undesirable effect in high speed designs. Can someone explain in detail?