High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.

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Extending the length of MIPI D-PHY

I have several devices which use MIPI's D-PHY standard, limiting the data transmission length to ~25cm on a standard FR4 PCB with a reasonable trace thickness -- however, I need to transfer this data ...
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63 views

How to create a control loop using a 100Msps digital signal as input

I would like to know what type of microcontroller should I buy for this control loop task. Scenario: I have a digital signal coming from the following equipment: UPDATE ::::: Ultrasonic ...
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82 views

How to network hundreds of sensors over a serial connection?

So I'm looking for a way to connect hundreds (300-400) sensors (like an accelerometer) together over a serial connection to a micro-controller. The sensors would transmit about 500kbps each. I've ...
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1answer
59 views

when do we need to apply high speed PCB rules ?

i'm new to pcb design and i'm wondering that starting from which frequency range we need to apply the high speed PCB design rules and techniques ?
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1answer
67 views

can high speed memory interfaces like GDDR5 or XDR ever become mainstream?

Given the limited memory on GPUs, I'm wondering why there are no socketed GDDR5 memory modules so that you can install more RAM. The main challenge seems to be maintaining signal integrity since ...
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49 views

Radio data transfer too slow [closed]

I need to send data from a camera recorder to a pc. The camera is about 1024/1000 pixels with 15 fps. Now the transmission distance should be at least 100 meters so I'm trying to use radio, but i ...
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277 views

How to construct High Speed Log Amplifiers

Objective : converting laser pulses from photo diode ranging from 10nA - 100mA to digital format, for measuring pulse width exactly pulse width 10ns-150ns and repeating at a rate of >20us up to ...
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2answers
85 views

Why is a reference plane needed in differential signalling?

As I understand differential signaling, return current goes via the "-" (minus) line, so why we do we need to provide a reference ground plane for differential signals?
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1answer
87 views

Lattice MachXO3L: MIPI CSI2 bridge

I would like to design a MIPI CSI2 bridge with a MachXO3L. I leverage the LVDS25 input/output of this FPGA family with the adequate resistors for HS traffic. (I think) I don't care about LP as the ...
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3answers
167 views

CAN bus layout design

I am trying to design a CAN bus node. The CAN bus shall be split-terminated with 120Ohm, 60Ohm for each line. Therefore i tried using this paper to calculate a characteristic impedance of 60Ohm for a ...
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35 views

difference between rising and falling time from the pulse response of transmission line

Attached is output pulse response of a transmission line (s-parameter). In the high-speed serial link design, we usually see more # of post-cursur ISI than pre-cursor ISI. One of the main reason is ...
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150 views

Which interface to choose SPI MIPI or Parallel?

I'm trying to connect the AR sensor module (AR0331) with the IMX6 processor and the problem is the camera uses a HiSPI & parallel line. Similarly, there is MI-PI (CSI) and Parallel line in the ...
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86 views

Using IR21531 as a simple 1 channel gate driver

I've bought the only gate driver I've found on the local hardware store (IR21531). I want to use it only to drive a IRF630 with a PWM 3.3V signal. How should I do the wiring? As you can see on the ...
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215 views

Buffer for 5V, 500ps to 10 ns pulses

I am trying to make a buffer for short, 5V pulses. The pulses are negative (form 5 to 0 V) and last for 500 ps to 10 ns (Half maximum, full width). The load is capacitive, around 50pF, and as close as ...
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1answer
142 views

No driver IC on net in Hyperlynx problem

I am getting the 'no driver IC on net' problem in Hyperlynx signal integrity software. Does anyone have any idea bout it? This is my PCB: It has an SMD connector and an AD9767 DAC. I have added the ...
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1answer
142 views

High-Speed PCB Design - Routing on Power Plane Layer?

I am working on designing my first high-speed PCB with 4 layers (in order): Top Layer: Single-ended/TTL signals Internal Layer 1: Power Plane (3.3V) Internal Layer 2: Ground Plane Bottom Layer: ...
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1answer
128 views

Aternative diode classes for high frequency(10GHz) applications

I'm trying to design a voltage clamping circuit for a 10GHz signal. I've modeled it in spice using several schottky diodes and it works but only when the signal pulse is at least a few nanoseconds ...
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2answers
720 views

What are these small stubs on the USB data pins of this device?

When disassembling a failing USB 2.0 flash drive, I noticed a feature on the USB data pins, that I do not understand from the perspective of a student just getting started with PCB layout: They're ...
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1answer
49 views

How to create a single line model (SLM), multi line model (MLM) and/or IBIS model of an interconnect for simulation?

I want to create a single line model, multi line model and/or IBIS model of an interconnect for simulation in Hyperlynx software but can't understand how to do it when the manufacturer has given no ...
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1answer
163 views

Duplicate MIPI CSI2 camera (one camera, two receivers)

I would like to feed two processors with the same MIPI CSI2 camera. I cannot afford to have one of the processors to play the role of proxy to the other. Though I searched hard, I'm not aware of any ...
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1answer
128 views

What references cover DDR3 layout considerations?

I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that ...
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4answers
128 views

High Speed Op-Amp recommendation [closed]

I am tasked with the issue of driving an IC that wants 5V input signals from an FPGA (3.3V outputs). Now, the most daunting part of it is the slew-rate requirements, with rise time \$t_r = 1.5 \text{...
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3answers
122 views

Via fences or pickets important parameters for design

What is more important for EMI shielding effectiveness with respect to guard traces and via fences, the width of the copper trace that circles around the area or the distance between the vias to ...
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1answer
530 views

PCIe, diagnosing and improving an eye diagram

I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector). The root ...
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1answer
68 views

How do I determine if the clock signal suffers from high speed effects

I need to determine if the clock signal inside a multichip module shall suffer from high speed effects i.e reflection and ringing. I have: (1) IBIS models of the components inside the multi-chip ...
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111 views

How to carry out signal integrity simulation with IBIS models

I need to determine if there will be high speed effects on the clock signal. I have not done such a simulation before. I have the IBIS models of the circuit components involved. I think I still need ...
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800 views

Making prototypes with high speed SMD components

Even today we have breadboard and strip board on which one can make "quick and dirty" circuits and also test prototypes. However, we have now moved into an era of predominantly surface mount ...
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4k views

Trace Length Tolerance Calculation - High Speed PCB Design

I have to interface a video format converter with a ADC IC, which converters RGB analog data to digital. The connection between this ADC and Converter is a 20 bit data bus which clocks at about 170MHz....
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2answers
189 views

High-speed clock line crossing under data lines

I'm interfacing an SDI video de-serializer with an HDMI transmitter. The de-serializer splits the video signal into 20 parallel lines and one clock line. Because the digital video data is high speed (...
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2answers
2k views

Precision high speed peak detector

As a follow-up to my previous question, where I seek to determine the amplitude of a 2 MHz sine wave, I've settled for an op amp based solution. To recall, my input has a maximum 240 mV amplitude -- ...
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1answer
73 views

fast 5v High Side switch controlled bz 3.3v

For my led cube, I need to switch 5V (common anode layers) with 3.3v (pic32). This should happen at a high frequency. In recent builds I used pfets, but because I'm using 3.3v now, a pfet wouldn't ...
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58 views

the thick copper trace

I need your help to find the answer for 2 questions: What is exact name of the golden trace in the red area? What is its purpose, and how to draw it in the PCB Thanks for your help
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333 views

PCB data trace lengths tolerable difference for high frequency

I have to interface a camera to a controller using the DCMI protocol for my project. I have around 17 (data+control) lines which are used with the camera. The frequency of operation is about 10 MHz. ...
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120 views

Looking for a high speed, high powered motor [closed]

So I'm trying something that has been attempted before and that is to have an electric turbo charger. essentially the goal is to spin a compressor wheel (20 grams) at 150k RPMS and sustain it for ...
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1answer
550 views

Why don't I need to consider trace width for a high speed oscillator crystals?

I have followed some reference designs that uses crystals like 40 MHz for the MCU, and I have not considered the trace width to do impedance matching. The result is that the boards works fine (I kept ...
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1answer
110 views

Isolation spacing in CPW-G

Is there any thumb of rules how to determine optimum spacing (marked with S below) for a RF signal (@2.45 GHz) on Coplanar Waveguide with ground (CPW-G)?
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2answers
1k views

Under what conditions does an optocoupler work fastest?

I want to use the optocoupler FODM452R2 in my design. I want this optocoupler to run as fast as it can (i.e.; work with minimum propagation delay and least rise/fall times). What is the optimum R1, R2 ...
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2answers
559 views

Is it possible to use capacitor for isolation instead of optocoupler?

I designed a Buck converter which drives several LEDs. The PWM signal, which has a certain fixed duty cycle, is generated by a 555 timer IC. The circuit which drives the Buck MOSFET, including the 555,...
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216 views

Complexity involved in building a single board computer [closed]

Our high school has tasked my and a friend of mine with with building a web connected controller for a hydroponics system. The school has budgeted 5k for us to spend as we like, and we are intent on ...
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1answer
84 views

Current-Mode Logic Explanation

I was reading about the HDMI standard and therefore the CML logic, and some alegations are not clear for me about the advantages of the CML. One of its advantages is the low output voltage swing, so ...
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2answers
657 views

I2C at 2.4 MHz with five microcontrollers over 2 meters

I have five Teensy 3.1 and I would like to interface them with I2C running at 2.4 MHz. The maximum Line Length will be around 2 meters. Will it work? What's the best way I can wire this up? ...
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1answer
562 views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...
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2answers
171 views

660 Mbits per second photo-diode amplifier on 3.3V rail

I've got a 10mW laser diode that can transmit at 660 Mbits per second, I've got the laser driver circuit that can do this, I've got a photodiode from Hamamatsu that looks good for this speed (-3 dB ~1 ...
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2answers
101 views

CML signal to ground terminated line or peak sensing ADC for short pulse

I'm currently designing the prototype of a timing instrument. One sensor gives an analog CML (current-mode logic) signal, from an amplifier (ADN2880). One end of the pair is routed to a comparator (...
2
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0answers
110 views

Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...
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1answer
385 views

Calculating Signal Loss (dB) Through Vias

Does anyone have any useful calculations or links to material covering good ways to calculate signal loss through vias? What would be perfect is a graph with typical loss in dB over the range 1GHz ...
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1answer
271 views

Distributing a 40MHz clock to several PCBs

I need to run four PCBs with a very accurately synchronised clock. The source clock is 40MHz, but each PCB contains a 1GHz PLL, and will be timing events in the analogue domain with a final ...
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3answers
7k views

Max switching frequency of GPIO pins of modern cheap FPGA

How can we estimate maximum switching frequency of GPIO FPGA pins? What is maximum data rate achievable when connecting two FPGAs together without using of integrated high-speed transceivers? Or when ...
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2answers
780 views

Terminating shielded/screened twisted pair correctly

Theoretically, I can't see a problem if the twisted pair has an end of cable termination that is: - A single resistor (R) that matches the characteristic impedance of the cable placed across the two ...
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1answer
6k views

How to select an appropriate capacitor for input voltage stabilization

I have a design where I have some high speed ICs and need to put a capacitor on the input voltage line to stabilize the voltage and protect from spikes or dips. I am operating at 5v and between 300 ...